From: wdenk Date: Mon, 23 Apr 2001 22:19:40 +0000 (+0000) Subject: * Fixes for HYMOD board X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f6fea1a46008302306c99de9a9a773b68a7766c4;p=users%2Frw%2Fppcboot.git * Fixes for HYMOD board (Patch by Murray Jensen, 23 Apr 2001) * Fixes for I2C Code (Patch by Murray Jensen, 23 Apr 2001) * Fix for flash support on MBX board; added additional flash chips on MBX board (Patch by Marius Gröger, 23 Apr 2001) * Fix copy&paste error in common/cmd_i2c.c (David Petersen, 22 Apr 2001) * Added support for Embedded Planet RPX Super Board (Patch by Frank Morauf, 19 Apr 2001) * Fix defines for SMC2 clock source on MPC82xx (Patch by Kevin Fry, 16 Apr 2001) * Additional flash chip support (28F160S3, 28F320S3) for IP860 board --- diff --git a/CHANGELOG b/CHANGELOG index a928090..9198120 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Open Issues: ====================================================================== +* cpu/mpc8xx/soft_i2c.c - function write_addr(): accessing a + non-existent device will cause an infinite loop + * Enabling too many BOOTP Vendor Extensions easily overflows the 64 byte limit imposed by the BOOTP header definition. While this is not a problem on our side, some DHCP servers will complain. Should @@ -49,6 +52,31 @@ To do: * "last user address" is set even if bootp is used without parameters (and it uses default address). +====================================================================== +Modifications for 0.9.1: +====================================================================== + +* Fixes for HYMOD board + (Patch by Murray Jensen, 23 Apr 2001) + +* Fixes for I2C Code + (Patch by Murray Jensen, 23 Apr 2001) + +* Fix for flash support on MBX board; + added additional flash chips on MBX board + (Patch by Marius Gröger, 23 Apr 2001) + +* Fix copy&paste error in common/cmd_i2c.c + (David Petersen, 22 Apr 2001) + +* Added support for Embedded Planet RPX Super Board + (Patch by Frank Morauf, 19 Apr 2001) + +* Fix defines for SMC2 clock source on MPC82xx + (Patch by Kevin Fry, 16 Apr 2001) + +* Additional flash chip support (28F160S3, 28F320S3) for IP860 board + ====================================================================== Modifications for 0.9.0: ====================================================================== diff --git a/CREDITS b/CREDITS index af67409..324767a 100644 --- a/CREDITS +++ b/CREDITS @@ -84,6 +84,10 @@ N: Jay Monkman E: jtm@smoothsmoothie.com D: EST SBC8260 support +N: Frank Morauf +E: frank.morauf@salzbrenner.com +D: Support for Embedded Planet RPX Super Board + N: Stefan Roese E: stefan.roese@esd-electronics.com D: IBM PPC401/403/405GP Support; Windows environment support diff --git a/MAKEALL b/MAKEALL index 2d63506..994b8d7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -17,7 +17,7 @@ LIST="" LIST="$LIST \ TQM823L TQM850L FPS850L TQM855L TQM860L SM850 \ ETX094 SPD823TS IVMS8 IVML24 \ - hermes IP860 lwmon \ + hermes IP860 lwmon pcu_e \ ESTEEM192E \ SXNI855T \ FADS823 FADS850SAR FADS860T ADS860 \ @@ -55,6 +55,7 @@ LIST="$LIST \ cogent_mpc8260 \ rsdproto \ sbc8260 \ + RPXsuper \ " [ $# = 0 ] && set $LIST diff --git a/Makefile b/Makefile index 915bfb7..1d8d021 100644 --- a/Makefile +++ b/Makefile @@ -79,7 +79,7 @@ OBJS += common/libcommon.a all: ppcboot.srec ppcboot.bin install: all - #cp ppcboot.bin /tftpboot/ppcboot.bin + cp ppcboot.bin /tftpboot/ppcboot.bin cp ppcboot.bin /net/gatekeeper/tftpboot/ppcboot.bin ppcboot.srec: ppcboot @@ -201,6 +201,14 @@ lwmon_config: unconfig echo "CPU = mpc8xx" >>config.mk ; \ echo "#include " >config.h +pcu_e_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = pcu_e" >>config.mk ; \ + echo "CPU = mpc8xx" >>config.mk ; \ + echo "#include " >config.h + ESTEEM192E_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd include ; \ @@ -376,6 +384,14 @@ GTH_config: unconfig echo "CPU = mpc8xx" >>config.mk ; \ echo "#include " >config.h +RPXsuper_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = rpxsuper" >>config.mk ; \ + echo "CPU = mpc8260" >>config.mk ; \ + echo "#include " >config.h + ######################################################################### clean: diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 7f13b6d..f83980f 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -190,15 +190,48 @@ const iop_conf_t iop_conf_tab[4][32] = { /* * AMI FS6377 Clock Generator configuration table * - * the table indexes 0 - 15 correspond to FS6377 registers 0 - 15. the - * data is written to the FS6377 via the i2c bus - hence the addr var. + * the "fs6377_regs[]" table entries correspond to FS6377 registers + * 0 - 15 (total of 16 bytes). + * + * the data is written to the FS6377 via the i2c bus using address in + * "fs6377_addr" (address is 7 bits - R/W bit not included). */ uchar fs6377_addr = 0x5c; uchar fs6377_regs[16] = { - 12, 75, 64, 25, 144, 128, 24, 75, - 224, 18, 75, 192, 224, 16, 16, 248 + 12, 75, 64, 25, 144, 128, 25, 192, + 224, 25, 192, 192, 224, 68, 68, 248 +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Philips SAA7111A Enhanced Video Input Processor (EVIP) configuration table + * + * the "saa7111a_regs[]" table entries correspond to SAA7111A registers + * 0x00 - 0x1f (total of 32 bytes). + * + * the data is written to the SAA7111A via the i2c bus using address in + * "saa7111a_addr" (address is 7 bits - R/W bit not included). + * + * NOTEs: + * - register 0x00 must be written with 0 before being read; + * - registers 0x01, 0x0f, 0x14, 0x18, 0x19, 0x1d and 0x1e are + * reserved and should be written with 0; + * - registers 0x1a, 0x1b, 0x1c and 0x1f are read-only. + */ + +#define RSVD 0x00 +#define NOWR 0x00 + +uchar saa7111a_addr = 0x24; + +uchar saa7111a_regs[32] = { + /* regs 0x00 - 0x07 */ 0x00, RSVD, 0xc0, 0x23, 0x00, 0x00, 0x00, 0x00, + /* regs 0x08 - 0x0f */ 0x88, 0x01, 0x80, 0x47, 0x40, 0x00, 0x01, RSVD, + /* regs 0x10 - 0x17 */ 0x40, 0x0c, 0x00, 0x40, RSVD, 0x00, 0x00, 0x00, + /* regs 0x18 - 0x1f */ RSVD, RSVD, NOWR, NOWR, NOWR, RSVD, RSVD, NOWR }; /* ------------------------------------------------------------------------- */ @@ -219,9 +252,9 @@ board_postclk_init(void) i2c_init(50000, 0xfe); /* slave address not important */ - i2c_newio(&state); - /* + * Initialise the FS6377 clock chip + * * the secondary address is the register number from where to * start the write - I want to write all the registers * @@ -229,11 +262,26 @@ board_postclk_init(void) * to print it on, nor any RAM to store it in - it will be obvious * if this doesn't work */ + i2c_newio(&state); + (void) i2c_send(&state, fs6377_addr, 0, I2CF_ENABLE_SECONDARY|I2CF_START_COND|I2CF_STOP_COND, sizeof (fs6377_regs), fs6377_regs); (void) i2c_doio(&state); + + /* + * Initialise the SAA7111A video input chip + * + * similar comments apply + */ + i2c_newio(&state); + + (void) i2c_send(&state, saa7111a_addr, 0, + I2CF_ENABLE_SECONDARY|I2CF_START_COND|I2CF_STOP_COND, + sizeof (saa7111a_regs), saa7111a_regs); + + (void) i2c_doio(&state); } /* ------------------------------------------------------------------------- */ diff --git a/board/ip860/flash.c b/board/ip860/flash.c index 5e237de..e0b0b72 100644 --- a/board/ip860/flash.c +++ b/board/ip860/flash.c @@ -110,9 +110,16 @@ static void flash_get_offsets (ulong base, flash_info_t *info) { int i; + /* all possible flash types + * (28F016SV, 28F160S3, 28F320S3) + * have the same erase block size: 64 kB per chip, + * of 128 kB per bank + */ + /* set up sector start address table */ for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); + info->start[i] = base; + base += 0x00020000; } } @@ -135,6 +142,10 @@ void flash_print_info (flash_info_t *info) switch (info->flash_id & FLASH_TYPEMASK) { case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; default: printf ("Unknown Chip Type\n"); break; } @@ -177,6 +188,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = addr[0]; switch (value) { case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */ + case (INTEL_ALT_MANU & 0x00FF00FF): info->flash_id = FLASH_MAN_INTEL; break; default: @@ -189,12 +201,24 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = addr[1]; /* device ID */ switch (value) { - case (INTL_ID_28F016S): + case (INTEL_ID_28F016S): info->flash_id += FLASH_28F016SV; info->sector_count = 32; info->size = 0x00400000; break; /* => 2x2 MB */ + case (INTEL_ID_28F160S3): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F320S3): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 2x4 MB */ + default: info->flash_id = FLASH_UNKNOWN; return (0); /* => no or unknown flash */ diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index d4b556f..22fa9dc 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -1,7 +1,6 @@ /* * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. * * See file CREDITS for list of people who contributed to this * project. @@ -255,14 +254,20 @@ void reset_phy(void) { uchar c; +#ifdef DEBUG printf ("### Switch on Ethernet for SCC2 ###\n"); +#endif c = pic_read (0x61); -printf ("Old PIC read: reg_61 = 0x%02x\n", c); +#ifdef DEBUG + printf ("Old PIC read: reg_61 = 0x%02x\n", c); +#endif c |= 0x40; /* disable COM3 */ c &= ~0x80; /* enable Ethernet */ pic_write (0x61, c); -c = pic_read (0x61); -printf ("New PIC read: reg_61 = 0x%02x\n", c); +#ifdef DEBUG + c = pic_read (0x61); + printf ("New PIC read: reg_61 = 0x%02x\n", c); +#endif udelay(1000); } diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c index c1640cb..1970e82 100644 --- a/board/mbx8xx/flash.c +++ b/board/mbx8xx/flash.c @@ -111,6 +111,9 @@ void flash_print_info (flash_info_t *info) case AMD_ID_F080B: printf ("AM29F080B (8 Mbit)\n"); break; + case AMD_ID_F016D: + printf ("AM29F016D (16 Mbit)\n"); + break; default: printf ("Unknown Chip Type\n"); break; @@ -164,7 +167,12 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } else if (devid == AMD_ID_F080B) { info->flash_id = vendor << 16 | devid; - info->sector_count = 4; + info->sector_count = 16; + info->size = 4 * info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F016D) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 32; info->size = 4 * info->sector_count * 0x10000; } else { diff --git a/board/pcu_e/Makefile b/board/pcu_e/Makefile new file mode 100644 index 0000000..c137d4b --- /dev/null +++ b/board/pcu_e/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pcu_e/config.mk b/board/pcu_e/config.mk new file mode 100644 index 0000000..10f3773 --- /dev/null +++ b/board/pcu_e/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Siemens PCU E Boards +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/pcu_e/flash.c b/board/pcu_e/flash.c new file mode 100644 index 0000000..6b32fae --- /dev/null +++ b/board/pcu_e/flash.c @@ -0,0 +1,548 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+CFG_MONITOR_LEN-1, + &flash_info[1]); + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +void flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/pcu_e/pcu_e.c b/board/pcu_e/pcu_e.c new file mode 100644 index 0000000..103dfa9 --- /dev/null +++ b/board/pcu_e/pcu_e.c @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +/* + * 50 MHz SDRAM access using UPM A + */ +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, + 0x1ffddc47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, + 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ + printf ("Siemens PCU E\n"); + return (1); +} + +/* ------------------------------------------------------------------------- */ + +long int +initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + long int size_b0, reg; + int i; + + /* + * Configure UPMA for SDRAM + */ + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = CFG_MPTPR; + + /* burst length=4, burst type=sequential, CAS latency=2 */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 2 to the SDRAM bank at preliminary address. + */ + //memctl->memc_or2 = CFG_OR2_PRELIM; + //memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or5 = CFG_OR5_PRELIM; /* XXX Test Board only XXX */ + memctl->memc_br5 = CFG_BR5_PRELIM; /* XXX Test Board only XXX */ + + /* initialize memory address register */ + memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */ + + /* mode initialization (offset 5) */ + udelay(200); /* 0x80006105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05); + + /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ + udelay(1); /* 0x80006130 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30); + udelay(1); /* 0x80006130 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30); + + udelay(1); /* 0x80006106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06); + + reg = memctl->memc_mamr; + reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */ + reg |= MAMR_TLFB_4X; /* ... to 4x */ + reg |= MAMR_PTBE; /* enable refresh */ + memctl->memc_mamr = reg; + + udelay(200); + + /* Need at least 10 DRAM accesses to stabilize */ + for (i=0; i<10; ++i) { + volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM; + unsigned long val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* + * Check Bank 0 Memory Size for re-configuration + */ + size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); + + memctl->memc_mamr = CFG_MAMR | MAMR_PTBE; + + /* + * Final mapping: + */ + + //memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; + //memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; +/* XXX Test Board only XXX */ + memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; +/* XXX Test Board only XXX */ + udelay(1000); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + volatile long int *addr; + long int cnt, val; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + return (0); + } + + for (cnt = 1; ; cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + + if (val != (~cnt)) { + return (cnt * sizeof(long)); + } + } + /* NOTREACHED */ +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/pcu_e/ppcboot.lds b/board/pcu_e/ppcboot.lds new file mode 100644 index 0000000..68fa411 --- /dev/null +++ b/board/pcu_e/ppcboot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/pcu_e/ppcboot.lds.debug b/board/pcu_e/ppcboot.lds.debug new file mode 100644 index 0000000..6d788f1 --- /dev/null +++ b/board/pcu_e/ppcboot.lds.debug @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile new file mode 100644 index 0000000..85ea1fc --- /dev/null +++ b/board/rpxsuper/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := rpxsuper.o flash.o mii_phy.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/rpxsuper/config.mk b/board/rpxsuper/config.mk new file mode 100644 index 0000000..4b8c5d3 --- /dev/null +++ b/board/rpxsuper/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0x80F00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c new file mode 100644 index 0000000..c885a87 --- /dev/null +++ b/board/rpxsuper/flash.c @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD 29F080B devices + * Added support for 64bit and AMD 29DL323B + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define RD_SWP32(x) in_le32((volatile u32*)x) + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD "); + break; + case (FUJ_MANUFACT & FLASH_VENDMASK): + printf ("FUJITSU "); + break; + case (SST_MANUFACT & FLASH_VENDMASK): + printf ("SST "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_DL323B & FLASH_TYPEMASK): + printf("AM29DL323B (32 MBit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + vu_long vendor[2], devid[2]; + ulong base = (ulong)addr; + + /* Reset and Write auto select command: read Manufacturer ID */ + addr[0] = 0xf0f0f0f0; + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0x90909090; + addr[1] = 0xf0f0f0f0; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0x90909090; + udelay (1000); + + vendor[0] = RD_SWP32(&addr[0]); + vendor[1] = RD_SWP32(&addr[1]); + if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) { + info->size = 0; + goto out; + } + + devid[0] = RD_SWP32(&addr[2]); + devid[1] = RD_SWP32(&addr[3]); + + if (devid[0] == AMD_ID_DL323B) { + /* + * we have 2 Banks + * Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte + * Bank 2 (48 Sectors): 23-70=64kbyte + */ + info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_DL323B & FLASH_TYPEMASK); + info->sector_count = 71; + info->size = 4 * (8 * 8 + 63 * 64) * 1024; + } + else { + info->size = 0; + goto out; + } + + /* set up sector start address table */ + for (i = 0; i < 8; i++) { + info->start[i] = base + (i * 0x8000); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address */ + addr = (volatile unsigned long *)(info->start[i]); + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0x90909090; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0x90909090; + udelay (1000); + base = RD_SWP32(&addr[4]); + base |= RD_SWP32(&addr[5]); + info->protect[i] = base & 0x00010001 ? 1 : 0; + } + addr = (vu_long*)info->start[0]; + +out: + /* reset command */ + addr[0] = 0xf0f0f0f0; + addr[1] = 0xf0f0f0f0; + + return info->size; +} + + +/*----------------------------------------------------------------------- + */ + +void flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0x80808080; + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0x80808080; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + udelay (100); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x30303030; + addr[1] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ( (addr[0] & 0x80808080) != 0x80808080 || + (addr[1] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + addr[1] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if ((dest & 0x00000004) == 0) { + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0xA0A0A0A0; + } + else { + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0xA0A0A0A0; + } + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c new file mode 100644 index 0000000..5ce7c6d --- /dev/null +++ b/board/rpxsuper/mii_phy.c @@ -0,0 +1,108 @@ +#include +#include "mii_phy.h" +#include "rpxsuper.h" + +#define MII_MDIO 0x01 +#define MII_MDCK 0x02 +#define MII_MDIR 0x04 + +void +mii_discover_phy(void) +{ + int known; + unsigned short phy_reg; + unsigned long phy_id; + + known = 0; + printf("Discovering phy @ 0: "); + phy_id = mii_phy_read(2) << 16; + phy_id |= mii_phy_read(3); + if ((phy_id & 0xFFFFFC00) == 0x00137800) { + printf("Level One "); + if ((phy_id & 0x000003F0) == 0xE0) { + printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); + known = 1; + } + else printf("unknown type\n"); + } + else printf("unknown OUI = 0x%08lX\n", phy_id); + + phy_reg = mii_phy_read(1); + if (!(phy_reg & 0x0004)) printf("Link is down\n"); + if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); + if (phy_reg & 0x0002) printf("Jabber condition detected\n"); + if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); + + if (known) { + phy_reg = mii_phy_read(17); + if (phy_reg & 0x0400) + printf("Phy operating at %d MBit/s in %s-duplex mode\n", + phy_reg & 0x4000 ? 100 : 10, + phy_reg & 0x0200 ? "full" : "half"); + else + printf("bad link!!\n"); +/* +left off: no link, green 100MBit, yellow 10MBit +right off: no activity, green full-duplex, yellow half-duplex +*/ + mii_phy_write(20, 0x0452); + } +} + +unsigned short +mii_phy_read(unsigned short reg) +{ + int i; + unsigned short tmp, val = 0, adr = 0; + t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + + tmp = 0x6002 | (adr << 7) | (reg << 2); + regs->bcsr4 = 0xC3; + for (i = 0; i < 64; i++) { + regs->bcsr4 ^= MII_MDCK; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + tmp <<= 1; + } + regs->bcsr4 |= MII_MDIR; + for (i = 0; i < 16; i++) { + val <<= 1; + regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); + if (regs->bcsr4 & MII_MDIO) val |= 1; + regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); + } + return val; +} + +void +mii_phy_write(unsigned short reg, unsigned short val) +{ + int i; + unsigned short tmp, adr = 0; + t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + + tmp = 0x5002 | (adr << 7) | (reg << 2); + regs->bcsr4 = 0xC3; + for (i = 0; i < 64; i++) { + regs->bcsr4 ^= MII_MDCK; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + tmp <<= 1; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (val & 0x8000) MII_REG |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + val <<= 1; + } +} + diff --git a/board/rpxsuper/ppcboot.lds b/board/rpxsuper/ppcboot.lds new file mode 100644 index 0000000..9d6977b --- /dev/null +++ b/board/rpxsuper/ppcboot.lds @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme new file mode 100644 index 0000000..2212bbd --- /dev/null +++ b/board/rpxsuper/readme @@ -0,0 +1,30 @@ +Hi, + +so this is the port to the Embedded Planet RPX Super Board. + +ATTENTION +This code is only tested on the AY-Version, which is an early release with some +hardware bugs. The main problem is that this board uses the default Hard Reset +Configuration Word and not the 4 bytes located at start of FLASH because at +0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be +carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low +byte. + +The icache can only manually be enabled after reset. +The FLASH and main SDRAM is working with icache enabled. +The local SDRAM can only be used as data memory when icache is enabled. +If ppcboot runs in local SDRAM, TFTP does not work. +The functions in mii_phy.c are all working. Call mii_phy_discover() out of +eth_init() and solve the linker error. +I2C, RTC/NVRAM and PCMCIA are not working yet. + +TODO +The 32MB local SDRAM is working but not shown in the startup messages of +ppcboot. If you locate ppcboot or any other program to this area it won't run. +Turning the ichache off does not solve this problem. + +As I won't buy another RPX Super there might be some little work to do for you +getting this ppcboot port running on the final board. + + +frank.morauf@salzbrenner.com diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c new file mode 100644 index 0000000..a418e39 --- /dev/null +++ b/board/rpxsuper/rpxsuper.c @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "rpxsuper.h" + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ + /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Setup CS4 to enable the Board Control/Status registers. + * Otherwise the smcs won't work. +*/ +int board_pre_init(void) +{ + volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + memctl->memc_br4 = CFG_BR4_PRELIM; + memctl->memc_or4 = CFG_OR4_PRELIM; + regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ + regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ + return 0; +} + +void +reset_phy(void) +{ + volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + regs->bcsr4 = 0xC3; +} + +/* + * Check Board Identity: + */ + +int checkboard(void) +{ + volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + printf ("Embedded Planet RPX Super, Revision %d\n", regs->bcsr0 >> 4); + + return 1; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0, *ramaddr; + ulong psdmr, lsdmr, bcr; + long size = 0; + int i; + + psdmr = CFG_PSDMR; + lsdmr = CFG_LSDMR; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + size = CFG_SDRAM0_SIZE; + bcr = immap->im_siu_conf.sc_bcr; + immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); + + memctl->memc_mptpr = CFG_MPTPR; + + ramaddr = (uchar *)(CFG_SDRAM0_BASE); + memctl->memc_psrt = CFG_PSRT; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + immap->im_siu_conf.sc_bcr = bcr; + +#ifndef CFG_RAMBOOT +// size += CFG_SDRAM1_SIZE; + ramaddr = (uchar *)(CFG_SDRAM1_BASE); + memctl->memc_lsrt = CFG_LSRT; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; +#endif + + /* return total ram size */ + return (size * 1024 * 1024); +} diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h new file mode 100644 index 0000000..af31060 --- /dev/null +++ b/board/rpxsuper/rpxsuper.h @@ -0,0 +1,25 @@ +#ifndef __RPX8260_H__ +#define __RPX8260_H__ + +typedef struct tt_rpx_regs +{ + volatile unsigned char bcsr0; + volatile unsigned char bcsr1; + volatile unsigned char bcsr2; + volatile unsigned char bcsr3; + volatile unsigned char bcsr4; + volatile unsigned char bcsr5; + volatile unsigned char bcsr6; + volatile unsigned char bcsr7; + volatile unsigned char bcsr8; + volatile unsigned char bcsr9; + volatile unsigned char bcsr10; + volatile unsigned char bcsr11; + volatile unsigned char bcsr12; + volatile unsigned char bcsr13; + volatile unsigned char bcsr14; + volatile unsigned char bcsr15; +} t_rpx_regs; +typedef t_rpx_regs* tp_rpx_regs; + +#endif diff --git a/common/board.c b/common/board.c index b4bf919..b11040e 100644 --- a/common/board.c +++ b/common/board.c @@ -152,7 +152,8 @@ board_init_f (ulong bootflag) defined(CONFIG_WALNUT405) || \ defined(CONFIG_CPCIISER4) || \ defined(CONFIG_ADCIOP) || \ - defined(CONFIG_LWMON) + defined(CONFIG_LWMON) || \ + defined(CONFIG_RPXSUPER) board_pre_init(); /* very early board init code (fpga boot, etc.) */ #endif @@ -503,7 +504,8 @@ void board_init_r (bd_t *bd, ulong dest_addr) defined(CONFIG_IVMS8) || \ defined(CONFIG_IVML24) || \ defined(CONFIG_IP860) || \ - defined(CONFIG_LWMON) ) + defined(CONFIG_LWMON) || \ + defined(CONFIG_RPXSUPER) ) # ifdef DEBUG puts (" Reset Ethernet PHY\n"); # endif diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 7ee4a2a..10c3675 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -184,11 +184,11 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) i2c_newio (&state); - rc = i2c_receive (&state, i2c_addr, sec_addr, + rc = i2c_send (&state, i2c_addr, sec_addr, I2CF_ENABLE_SECONDARY|I2CF_START_COND|I2CF_STOP_COND, size, data_addr); if (rc) { - printf ("i2c_receive FAILED rc=%d\n", rc); + printf ("i2c_send FAILED rc=%d\n", rc); return; } diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index ec0c917..e405f50 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -67,6 +67,9 @@ #define CPMFCR_RAMTYPE 0 #define FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) #endif +#if defined(CONFIG_RPXSUPER) +#error "on RPX Super ethernet must be FCC3" +#endif #elif (CONFIG_ETHER_INDEX == 2) @@ -112,6 +115,9 @@ #define CPMFCR_RAMTYPE 0 #define FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) #endif +#if defined(CONFIG_RPXSUPER) +#error "on RPX Super ethernet must be FCC3" +#endif #elif (CONFIG_ETHER_INDEX == 3) @@ -131,6 +137,20 @@ #define CPMFCR_RAMTYPE 0 #define FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) #endif +#if defined(CONFIG_RPXSUPER) +/* + * Attention: this is board-specific + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Half Duplex in FSMR + */ +#define CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +#define CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +#define CPMFCR_RAMTYPE 0 +//#define FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) +#define FCC_PSMR 0 +#endif #else #error "FCC Ethernet not correctly defined" diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index 3dfc310..29593cf 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -292,7 +292,10 @@ int i2c_send(i2c_state_t *state, } } else + { + txbd->length = size; /* Length of message */ i = 0; + } /* set up txbd */ txbd->status = BD_SC_READY; diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index eeb0655..0ce3949 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -175,6 +175,13 @@ boot_warm: bl cogent_init_8260 #endif /* CONFIG_COGENT */ +#if defined(CONFIG_DEFAULT_HRCW) + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + lis r4, 0x00010000@h + stw r3, 0x1A8(r4) +#endif /* CONFIG_DEFAULT_HRCW */ + /* Initialise the MPC8260 processor core */ /*--------------------------------------------------------------*/ diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 24d9196..8a3ec01 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -120,6 +120,7 @@ cpu_init_f (volatile immap_t *immr) defined(CONFIG_SXNI855T) || \ defined(CONFIG_RPXLITE) || \ defined(CONFIG_GTH) || \ + defined(CONFIG_PCU_E) || \ (defined(CONFIG_MPC860T) && defined(CONFIG_FADS)) /* XXX - FIXME - XXX * I still don't understand why some systems work only with this @@ -171,6 +172,21 @@ cpu_init_f (volatile immap_t *immr) memctl->memc_br4 = CFG_BR4_PRELIM; #endif +#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; +#endif + +#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) + memctl->memc_or6 = CFG_OR6_PRELIM; + memctl->memc_br6 = CFG_BR6_PRELIM; +#endif + +#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) + memctl->memc_or7 = CFG_OR7_PRELIM; + memctl->memc_br7 = CFG_BR7_PRELIM; +#endif + #endif /* ! CONFIG_MBX */ diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index 75a348e..bb5ec0b 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -22,6 +22,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ #include @@ -283,6 +286,8 @@ i2c_send(i2c_state_t *state, PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + if (flags & I2CF_START_COND) + { PRINTD(("[I2C] Formatting addresses...\n")); if (flags & I2CF_ENABLE_SECONDARY) { @@ -297,6 +302,12 @@ i2c_send(i2c_state_t *state, txbd->addr[0] = address << 1; /* Write destination address to BD */ i = 1; } + } + else + { + txbd->length = size; /* Length of message */ + i = 0; + } /* set up txbd */ txbd->status = BD_SC_READY; @@ -374,8 +385,7 @@ int i2c_receive(i2c_state_t *state, rxbd->length = size_to_expect; rxbd->addr = datain; - if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; + txbd->status |= BD_I2C_TX_START; if (flags & I2CF_STOP_COND) { txbd->status |= BD_SC_LAST | BD_SC_WRAP; diff --git a/include/config_MBX.h b/include/config_MBX.h index 9c47e9b..5de2f35 100644 --- a/include/config_MBX.h +++ b/include/config_MBX.h @@ -148,8 +148,8 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ diff --git a/include/config_RPXsuper.h b/include/config_RPXsuper.h new file mode 100644 index 0000000..c471046 --- /dev/null +++ b/include/config_RPXsuper.h @@ -0,0 +1,482 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + + +/***************************************************************************** + * + * These settings must match the way _your_ board is set up + * + *****************************************************************************/ +/* for the AY-Revision which does not use the HRCW */ +#define CONFIG_DEFAULT_HRCW + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN (66 * 1000 * 1000) + +/* How is switch S2 set? We really only want the MODCK[1-3] bits, so + * only the 3 least significant bits are important. +*/ +#define CFG_SBC_S2 0x04 + +/* What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core + * 0x2 0x2 33 133 133 + * 0x2 0x4 33 133 200 + * 0x5 0x5 66 133 133 + * 0x5 0x7 66 133 200 + */ +#define CFG_SBC_MODCK_H 0x06 + +#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */ +#undef CFG_SBC_BOOT_LOW + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk + * The main FLASH is whichever is connected to *CS0. PPCBOOT expects + * this to be the SIMM. + */ +#define CFG_FLASH0_BASE 0x80000000 +#define CFG_FLASH0_SIZE 16 + +/* What should the base address of the secondary FLASH be and how big + * is it (in Mbytes)? The secondary FLASH is whichever is connected + * to *CS6. PPCBOOT expects this to be the on board FLASH. If you don't + * want it enabled, don't define these constants. + */ +#define CFG_FLASH1_BASE 0 +#define CFG_FLASH1_SIZE 0 +#undef CFG_FLASH1_BASE +#undef CFG_FLASH1_SIZE + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 64 + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM1_BASE 0x04000000 +#define CFG_SDRAM1_SIZE 32 + +/* What should be the base address of the LEDs and switch S0? + * If you don't want them enabled, don't define this. + */ +#define CFG_LED_BASE 0x00000000 + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ + +#define CONFIG_I2C 1 + +/* Define this to reserve an entire FLASH sector (256 KB) for + * environment variables. Otherwise, the environment will be + * put in the same sector as ppcboot, and changing variables + * will erase ppcboot temporarily + */ +#define CFG_ENV_IN_OWN_SECT + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* What should the console's baud rate be? */ +#define CONFIG_BAUDRATE 115200 + +/* Ethernet MAC address */ +#define CONFIG_ETHADDR 08:00:22:50:70:63 + +#define CONFIG_IPADDR 192.168.1.99 +#define CONFIG_SERVERIP 192.168.1.3 + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY -1 + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +/* What ppcboot subsytems do you want enabled? */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_REGINFO & \ + ~CFG_CMD_KGDB ) + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xF0000000 + +/* Where do the on board registers (CS4) live? */ +#define CFG_REGS_BASE 0xFA000000 + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 8 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x04000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ +#if defined(CFG_SBC_BOOT_LOW) +# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_SBC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_SBC_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ + ((CFG_IMMR & 0x01000000) >> 7) |\ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER (HRCW_BPS11 |\ + HRCW_DPPC11 |\ + CFG_SBC_HRCW_IMMR |\ + HRCW_MMR00 |\ + HRCW_LBPC11 |\ + HRCW_APPC10 |\ + HRCW_CS10PC00 |\ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\ + CFG_SBC_HRCW_BOOT_FLAGS) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000) + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 + +# ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +# else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +# endif /* CFG_ENV_IN_OWN_SECT */ +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (/*HID0_ICE |*/\ + /*HID0_DCE |*/\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (/*HID0_ICE |*/\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_EBM |\ + BCR_PLDP |\ + BCR_EAV |\ + BCR_NPQM0) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ + +#define CFG_SIUMCR (SIUMCR_L2CPC01 |\ + SIUMCR_APPC10 |\ + SIUMCR_CS10PC01) + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR (SCCR_DFBRG01) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90) + * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) + * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) + * 3 unused + * 4 60x GPCM 8 bit Board Regs, LEDs, switches + * 5 unused + * 6 unused + * 7 unused + * 8 PCMCIA + * 9 unused + * 10 unused + * 11 unused +*/ + +/* Bank 0 - FLASH + * + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_DECC_NONE |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_6_CLK |\ + ORxG_EHTR) + +/* Bank 1 - SDRAM + * + */ +#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12 |\ + ORxS_IBID) + +#define CFG_PSDMR 0x014DA412 +#define CFG_PSRT 0x79 + + +/* Bank 2 - SDRAM + * + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) + +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +#define CFG_LSDMR 0x0169A512 +#define CFG_LSRT 0x79 + +#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK) + +/* Bank 4 - On board registers + * + */ +#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR4_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ + + diff --git a/include/config_hymod.h b/include/config_hymod.h index 5acc5d9..0764206 100644 --- a/include/config_hymod.h +++ b/include/config_hymod.h @@ -336,10 +336,10 @@ * 0 60x GPCM 32 bit FLASH * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) * 2 60x SDRAM 64 bit SDRAM - * 3 Local UPMC 8 bit Main Xilinx configuration (unimplemented) - * 4 Local GPCM 32 bit Main Xilinx register mode (unimplemented) - * 5 Local UPMB 32 bit Main Xilinx port mode (unimplemented) - * 6 Local UPMC 8 bit Mezz Xilinx configuration (unimplemented) + * 3 Local UPMC 8 bit Main Xilinx configuration + * 4 Local GPCM 32 bit Main Xilinx register mode + * 5 Local UPMB 32 bit Main Xilinx port mode + * 6 Local UPMC 8 bit Mezz Xilinx configuration */ /* diff --git a/include/config_lwmon.h b/include/config_lwmon.h index cf9cd28..0258ce2 100644 --- a/include/config_lwmon.h +++ b/include/config_lwmon.h @@ -45,12 +45,13 @@ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -//#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#define CONFIG_BOOTCOMMAND "fli" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/LinuxPPC " \ - "nfsaddrs=10.0.0.99:10.0.0.2" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -353,9 +354,9 @@ */ #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ -/* used to re-map FLASH both when starting from SRAM or FLASH: +/* used to re-map FLASH: * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ diff --git a/include/config_pcu_e.h b/include/config_pcu_e.h new file mode 100644 index 0000000..47666a9 --- /dev/null +++ b/include/config_pcu_e.h @@ -0,0 +1,371 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ +#define CONFIG_MPC860T 1 +#define CONFIG_PCU_E 1 /* ...on a PCU E board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ + +#define CONFIG_BAUDRATE 19200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +#define CONFIG_SOFT_I2C /* Software I2C support enabled */ +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +# define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Atmel 24C164 has 16 byte */ + /* page write mode using last */ + /* 4 bits of the address */ + +#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE ) \ + & ~CFG_CMD_NET + +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFE000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE 0xFFF00000 // was: CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ + +#if 1 +/* Start port with environment in flash; switch to EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +//#define CFG_ENV_ADDR 0xFFFE0000 /* Address of Environment Sector */ +#define CFG_ENV_OFFSET 0x8000 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment */ +//#define CFG_ENV_SECT_SIZE 0x20000 /* we have BIG sectors only :-( */ +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 1024 +#endif +/*----------------------------------------------------------------------- + * I2C/EEPROM Configuration + */ +#define CFG_I2C_CLOCK 25000 /* I²C Clock Rate in kHz */ + +#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ +#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * External Arbitration max. priority (7), + * Debug pins configuration '11', + * Asynchronous external master enable. + */ +/* => 0x70600200 */ +#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00004080 */ +#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ +#define CFG_PLPRCR \ + ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ + ) + +#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800000 */ +#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD100 | \ + SCCR_DFALCD01) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* 0x00C3 => 0x0003 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0x0000 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) - second Flash bank optional + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +//XXX #define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ +#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ + +/* + * used to re-map FLASH: restrict access enough but not too much to + * meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) + +#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +//XXX #define CFG_OR1_REMAP CFG_OR0_REMAP +//XXX #define CFG_OR1_PRELIM CFG_OR0_PRELIM +//XXX #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CFG_OR6_REMAP CFG_OR0_REMAP +#define CFG_OR6_PRELIM CFG_OR0_PRELIM +#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR2/OR2: SDRAM + * + * Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +//XXX #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ +#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +//XXX #define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +//XXX #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MPTPR 0x0200 + +/* + * MAMR settings for SDRAM + * 0x30104118 = Timer B period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, + * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X + * 0x30904114 = - " - | Periodic Timer B Enable, MAMR_TLFB_4X + */ +/* periodic timer for refresh */ +#define CFG_MAMR_PTB 48 + +#define CFG_MAMR ( (CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ + MAMR_AMB_TYPE_1 | \ + MAMR_G0CLB_A10 | \ + MAMR_RLFB_1X | \ + MAMR_WLFB_1X | \ + MAMR_TLFB_8X ) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/flash.h b/include/flash.h index 929cf23..11ec5ee 100644 --- a/include/flash.h +++ b/include/flash.h @@ -74,13 +74,12 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); #define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */ #define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */ #define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */ +#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ #define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ -#define INTL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ - #define AMD_ID_LV040B 0x4F /* 29LV040B ID */ /* 4 Mbit, 512K x 8, */ /* 8 64K x 8 uniform sectors */ @@ -90,6 +89,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); /* 8 64K x 8 uniform sectors */ #define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */ +#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */ #define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */ #define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */ @@ -104,6 +104,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); #define AMD_ID_LV320T 0xDEADBEEF /* 29LV320T ID (32 M, top boot sector) */ #define AMD_ID_LV320B 0xDEADBEEF /* 29LV320B ID (32 M, bottom boot sect) */ +#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */ +#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sector) */ + #define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */ #define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */ #define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */ @@ -111,6 +114,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ +#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ #define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ #define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */ #define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */ @@ -124,6 +128,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); #define INTEL_ID_28F640JA3 0x00170017 /* 64M = 128K x 64 */ #define INTEL_ID_28F128JA3 0x00180018 /* 128M = 128K x 128 */ +#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ +#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ + /*----------------------------------------------------------------------- * Internal FLASH identification codes * @@ -144,34 +151,36 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); #define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ #define FLASH_AM320B 0x0009 -#define FLASH_SST200A 0x000A /* SST 39xF200A ID ( 2M = 128K x 16 ) */ -#define FLASH_SST400A 0x000B /* SST 39xF400A ID ( 4M = 256K x 16 ) */ -#define FLASH_SST800A 0x000C /* SST 39xF800A ID ( 8M = 512K x 16 ) */ -#define FLASH_SST160A 0x000D /* SST 39xF160A ID (16M = 1M x 16 ) */ - -#define FLASH_STM800AB 0x0011 /* STM M29WF800AB ID ( 8M = 512K x 16 ) */ - -#define FLASH_28F400_T 0x0022 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ -#define FLASH_28F400_B 0x0023 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ - -#define FLASH_INTEL800T 0x0034 /* INTEL 28F800B3T ID( 8M = 512K x 16 ) */ /* added by Conn */ -#define FLASH_INTEL800B 0x0035 /* INTEL 28F800B3B ID( 8M = 512K x 16 ) */ -#define FLASH_INTEL160T 0x0036 /* INTEL 28F160B3T ID( 16M = 1M x 16 ) */ -#define FLASH_INTEL160B 0x0037 /* INTEL 28F160B3B ID( 16M = 1M x 16 ) */ -#define FLASH_INTEL320T 0x0038 /* INTEL 28F320B3T ID( 32M = 2M x 16 ) */ -#define FLASH_INTEL320B 0x0039 /* INTEL 28F320B3B ID( 32M = 2M x 16 ) */ -#define FLASH_INTEL640T 0x003A /* INTEL 28F320B3T ID( 64M = 4M x 16 ) */ -#define FLASH_INTEL640B 0x003B /* INTEL 28F320B3B ID( 64M = 4M x 16 ) */ - -#define FLASH_28F320JA3 0x003C /* INTEL 28F320JA3 ID( 32M = 128K x 32 */ -#define FLASH_28F640JA3 0x003D /* INTEL 28F640JA3 ID( 64M = 128K x 64 */ -#define FLASH_28F128JA3 0x003E /* INTEL 28F128JA3 ID(128M = 128K x 128 */ - -#define FLASH_28F008S5 0x0050 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ -#define FLASH_28F016SV 0x0051 /* Intel 28F016SV (16M = 512k x 16 ) */ -#define FLASH_28F800_B 0x0053 /* Intel E28F800B ( 1M = ? ) */ -#define FLASH_AM29F800B 0x0054 /* AMD Am29F800BB ( 1M = ? ) */ -#define FLASH_28F320J5 0x0055 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ +#define FLASH_SST200A 0x000A /* SST 39xF200A ID ( 2M = 128K x 16 ) */ +#define FLASH_SST400A 0x000B /* SST 39xF400A ID ( 4M = 256K x 16 ) */ +#define FLASH_SST800A 0x000C /* SST 39xF800A ID ( 8M = 512K x 16 ) */ +#define FLASH_SST160A 0x000D /* SST 39xF160A ID ( 16M = 1M x 16 ) */ + +#define FLASH_STM800AB 0x0011 /* STM M29WF800AB ( 8M = 512K x 16 ) */ + +#define FLASH_28F400_T 0x0022 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ +#define FLASH_28F400_B 0x0023 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ + +#define FLASH_INTEL800T 0x0034 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */ +#define FLASH_INTEL800B 0x0035 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */ +#define FLASH_INTEL160T 0x0036 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL160B 0x0037 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL320T 0x0038 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL320B 0x0039 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL640T 0x003A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ +#define FLASH_INTEL640B 0x003B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ + +#define FLASH_28F320JA3 0x003C /* INTEL 28F320JA3 ( 32M = 128K x 32) */ +#define FLASH_28F640JA3 0x003D /* INTEL 28F640JA3 ( 64M = 128K x 64) */ +#define FLASH_28F128JA3 0x003E /* INTEL 28F128JA3 (128M = 128K x 128) */ + +#define FLASH_28F008S5 0x0050 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ +#define FLASH_28F016SV 0x0051 /* Intel 28F016SV ( 16M = 512k x 32 ) */ +#define FLASH_28F800_B 0x0053 /* Intel E28F800B ( 1M = ? ) */ +#define FLASH_AM29F800B 0x0054 /* AMD Am29F800BB ( 1M = ? ) */ +#define FLASH_28F320J5 0x0055 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ +#define FLASH_28F160S3 0x0056 /* Intel 28F160S3 ( 16M = 512K x 32 ) */ +#define FLASH_28F320S3 0x0058 /* Intel 28F320S3 ( 32M = 512K x 64 ) */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ diff --git a/include/mii_phy.h b/include/mii_phy.h new file mode 100644 index 0000000..a65bd66 --- /dev/null +++ b/include/mii_phy.h @@ -0,0 +1,9 @@ +#ifndef _MII_PHY_H_ +#define _MII_PHY_H_ + +void mii_discover_phy(void); +unsigned short mii_phy_read(unsigned short reg); +void mii_phy_write(unsigned short reg, unsigned short val); + +#endif + diff --git a/include/mpc8260.h b/include/mpc8260.h index 25cc941..00ec79b 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -863,9 +863,9 @@ #define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */ #define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */ -#define CMXSMR_SMC2CS_BRG8 0x10 /* SMC2 Tx and Rx Clocks are BRG8 */ -#define CMXSMR_SMC2CS_CLK19 0x20 /* SMC2 Tx and Rx Clocks are CLK19 */ -#define CMXSMR_SMC2CS_CLK20 0x30 /* SMC2 Tx and Rx Clocks are CLK20 */ +#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */ +#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */ +#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */ /*----------------------------------------------------------------------- * miscellaneous diff --git a/include/ppcboot.h b/include/ppcboot.h index 71a6aa1..4328e66 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -202,7 +202,8 @@ void misc_init_r (bd_t *); defined(CONFIG_IVMS8) || \ defined(CONFIG_IVML24) || \ defined(CONFIG_IP860) || \ - defined(CONFIG_LWMON) + defined(CONFIG_LWMON) || \ + defined(CONFIG_RPXSUPER) /* $(BOARD)/$(BOARD).c */ void reset_phy (void); #endif @@ -246,7 +247,8 @@ void hermes_start_lxt980 (int speed); defined(CONFIG_WALNUT405) || \ defined(CONFIG_CPCIISER4) || \ defined(CONFIG_ADCIOP) || \ - defined(CONFIG_LWMON) + defined(CONFIG_LWMON) || \ + defined(CONFIG_RPXSUPER) /* $(BOARD)/$(BOARD).c */ int board_pre_init (void); #endif diff --git a/include/version.h b/include/version.h index 89aea9a..e23edad 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define PPCBOOT_VERSION "ppcboot 0.9.0" +#define PPCBOOT_VERSION "ppcboot 0.9.1" #endif /* __VERSION_H__ */