From: Steven Lee <steven_lee@aspeedtech.com>
Date: Tue, 7 Sep 2021 09:55:25 +0000 (+0800)
Subject: gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler.
X-Git-Tag: xarray-5.18~950^2~2
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f6c35df22708438c94605b8896d2b4e4d5f342a3;p=users%2Fwilly%2Fxarray.git

gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler.

The current hwirq is calculated based on the old GPIO pin order(input
GPIO range is from 0 to ngpios - 1).
It should be calculated based on the current GPIO input pin order(input
GPIOs are 0, 2, 4, ..., (ngpios - 1) * 2).

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 10f303d15225..3d6ef37a7702 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
 		reg = ioread32(bank_reg(data, bank, reg_irq_status));
 
 		for_each_set_bit(p, &reg, 32)
-			generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
+			generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
 	}
 
 	chained_irq_exit(ic, desc);