From: Linus Torvalds <torvalds@linux-foundation.org> Date: Sat, 20 Jul 2024 16:11:27 +0000 (-0700) Subject: Merge tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel... X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f557af081de6b45a25e27d633b4d8d2dbc2f428e;p=users%2Fjedix%2Flinux-maple.git Merge tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for various new ISA extensions: * The Zve32[xf] and Zve64[xfd] sub-extensios of the vector extension * Zimop and Zcmop for may-be-operations * The Zca, Zcf, Zcd and Zcb sub-extensions of the C extension * Zawrs - riscv,cpu-intc is now dtschema - A handful of performance improvements and cleanups to text patching - Support for memory hot{,un}plug - The highest user-allocatable virtual address is now visible in hwprobe * tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (58 commits) riscv: lib: relax assembly constraints in hweight riscv: set trap vector earlier KVM: riscv: selftests: Add Zawrs extension to get-reg-list test KVM: riscv: Support guest wrs.nto riscv: hwprobe: export Zawrs ISA extension riscv: Add Zawrs support for spinlocks dt-bindings: riscv: Add Zawrs ISA extension description riscv: Provide a definition for 'pause' riscv: hwprobe: export highest virtual userspace address riscv: Improve sbi_ecall() code generation by reordering arguments riscv: Add tracepoints for SBI calls and returns riscv: Optimize crc32 with Zbc extension riscv: Enable DAX VMEMMAP optimization riscv: mm: Add support for ZONE_DEVICE virtio-mem: Enable virtio-mem for RISC-V riscv: Enable memory hotplugging for RISC-V riscv: mm: Take memory hotplug read-lock during kernel page table dump riscv: mm: Add memory hotplugging support riscv: mm: Add pfn_to_kaddr() implementation riscv: mm: Refactor create_linear_mapping_range() for memory hot add ... --- f557af081de6b45a25e27d633b4d8d2dbc2f428e diff --cc arch/riscv/include/asm/cmpxchg.h index 808b4c78462e,637d7acab1f8..ebbce134917c --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@@ -8,9 -8,12 +8,12 @@@ #include <linux/bug.h> + #include <asm/alternative-macros.h> #include <asm/fence.h> + #include <asm/hwcap.h> + #include <asm/insn-def.h> -#define __arch_xchg_masked(prepend, append, r, p, n) \ +#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n) \ ({ \ u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \ ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \ diff --cc arch/riscv/kernel/patch.c index ab03732d06c4,5b3f6406e8c4..69e5796fc51f --- a/arch/riscv/kernel/patch.c +++ b/arch/riscv/kernel/patch.c @@@ -200,10 -186,11 +202,9 @@@ NOKPROBE_SYMBOL(patch_insn_set) int patch_text_set_nosync(void *addr, u8 c, size_t len) { - u32 *tp = addr; int ret; - ret = patch_insn_set(tp, c, len); + ret = patch_insn_set(addr, c, len); - if (!ret) - flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len); return ret; } @@@ -232,10 -222,11 +236,9 @@@ NOKPROBE_SYMBOL(patch_insn_write) int patch_text_nosync(void *addr, const void *insns, size_t len) { - u32 *tp = addr; int ret; - ret = patch_insn_write(tp, insns, len); + ret = patch_insn_write(addr, insns, len); - if (!ret) - flush_icache_range((uintptr_t)addr, (uintptr_t)addr + len); return ret; } diff --cc arch/riscv/net/bpf_jit_comp64.c index 0795efdd3519,a01b312913bc..99f34409fb60 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@@ -15,10 -15,8 +15,11 @@@ #include <asm/percpu.h> #include "bpf_jit.h" +#define RV_MAX_REG_ARGS 8 #define RV_FENTRY_NINSNS 2 + #define RV_FENTRY_NBYTES (RV_FENTRY_NINSNS * 4) +/* imm that allows emit_imm to emit max count insns */ +#define RV_MAX_COUNT_IMM 0x7FFF7FF7FF7FF7FF #define RV_REG_TCC RV_REG_A6 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */