From: wdenk <wdenk>
Date: Mon, 10 Jun 2002 16:40:59 +0000 (+0000)
Subject: * Add support for Siemens SCM board;
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f28caa968ed3ef411e6328216d96517bfc24574b;p=users%2Frw%2Fppcboot.git

* Add support for Siemens SCM board;
  update CCM board configuration;
  use common code where possible.
---

diff --git a/CHANGELOG b/CHANGELOG
index 88b05dd..6cb222b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -14,6 +14,9 @@
 Modifications for 1.1.6:
 ======================================================================
 
+* Add support for Siemens SCM board;
+  update CCM board configuration; use common code where possible.
+
 * Patch by Steven Scholz, 17 May 2002:
   Comment MAR settings in board/tqm8xx/tqm8xx.c
   (probably useful for others, too)
diff --git a/Makefile b/Makefile
index 96c56d1..e4c4a6d 100644
--- a/Makefile
+++ b/Makefile
@@ -185,6 +185,15 @@ CCM_config:		unconfig
 	echo "VENDOR = siemens"	>>config.mk ;	\
 	echo "#include <config_$(@:_config=).h>" >config.h
 
+SCM_config:		unconfig
+	@echo "Configuring for $(@:_config=) Board..." ; \
+	cd ./include ;				\
+	echo "ARCH  = ppc"	> config.mk ;	\
+	echo "BOARD = SCM"	>>config.mk ;	\
+	echo "CPU   = mpc8260"	>>config.mk ;	\
+	echo "VENDOR = siemens"	>>config.mk ;	\
+	echo "#include <config_$(@:_config=).h>" >config.h
+
 cogent_mpc8xx_config:	unconfig
 	@echo "Configuring for $(@:_config=) Board..." ; \
 	cd ./include ;				\
diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile
index 2e45192..7d51d49 100644
--- a/board/siemens/CCM/Makefile
+++ b/board/siemens/CCM/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= ccm.o flash.o
+OBJS	= ccm.o flash.o fpga_ccm.o ../common/fpga.o
 
 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $^
diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c
index f4b6dea..dafb6d5 100644
--- a/board/siemens/CCM/ccm.c
+++ b/board/siemens/CCM/ccm.c
@@ -25,17 +25,20 @@
 #include <mpc8xx.h>
 #include <commproc.h>
 #include <command.h>
-#include <cmd_bsp.h>
 
 /* ------------------------------------------------------------------------- */
 
 static long int dram_size (long int, long int *, long int);
+#if 0
 static void puma_status (void);
 static void puma_set_mode (int mode);
 static int  puma_init_done (void);
 static void puma_load (ulong addr, ulong len);
-static void can_driver_enable (void);
-static void can_driver_disable (void);
+#endif
+void can_driver_enable (void);
+void can_driver_disable (void);
+
+int fpga_init(void);
 
 /* ------------------------------------------------------------------------- */
 
@@ -93,55 +96,6 @@ const uint sdram_table[] =
 
 /* ------------------------------------------------------------------------- */
 
-/*
- * PUMA access using UPM B
- */
-const uint puma_table[] =
-{
-	/*
-	 * Single Read. (Offset 0 in UPM RAM)
-	 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_,
-	/*
-	 * Precharge and MRS
-	 */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Read. (Offset 8 in UPM RAM)
-	 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPM RAM)
-	 */
-	0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
-					    _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPM RAM)
-	 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPM RAM)
-	 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPM RAM)
-	 */
-	0x7FFFFC07, /* last */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
 
 /*
  * Check Board Identity:
@@ -174,6 +128,37 @@ int checkboard (void)
     return (1);
 }
 
+
+/*
+ * If Power-On-Reset switch off the red Fault LED:
+ */
+#define RSR_CSRS	0x08000000
+
+int power_on_reset(void)
+{
+    /* Test Reset Status Register */
+    return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
+}
+
+#define FAULT_LED_PAR	im_cpm.cp_pbpar
+#define FAULT_LED_DIR	im_cpm.cp_pbdir
+#define FAULT_LED_ODR	im_cpm.cp_pbodr
+#define FAULT_LED_DAT	im_cpm.cp_pbdat
+#define FAULT_LED_BIT	0x20000		/* red LED is on PB.14 */
+
+static void switch_fault_led (void)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+
+    /* Check stop reset status */
+    if (power_on_reset()) {
+	immap->FAULT_LED_PAR &= ~FAULT_LED_BIT;
+	immap->FAULT_LED_ODR &= ~FAULT_LED_BIT;
+	immap->FAULT_LED_DIR |=  FAULT_LED_BIT;
+	immap->FAULT_LED_DAT &= ~FAULT_LED_BIT;
+    }
+}
+
 /* ------------------------------------------------------------------------- */
 
 long int initdram (int board_type)
@@ -269,6 +254,7 @@ long int initdram (int board_type)
     memctl->memc_mptpr = reg;
 
     can_driver_enable ();
+    switch_fault_led ();
 
     udelay(10000);
 
@@ -281,7 +267,7 @@ long int initdram (int board_type)
  * Warning - both the PUMA load mode and the CAN driver use UPM B,
  * so make sure only one of both is active.
  */
-static void can_driver_enable (void)
+void can_driver_enable (void)
 {
     volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -326,7 +312,7 @@ static void can_driver_enable (void)
     memctl->memc_br3 = CFG_BR3_CAN;
 }
 
-static void can_driver_disable (void)
+void can_driver_disable (void)
 {
     volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -395,7 +381,7 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 
 #define	ETH_CFG_BITS	(CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
 
-#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
+#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN)
 
 void	reset_phy(void)
 {
@@ -406,11 +392,11 @@ void	reset_phy(void)
 #if CFG_ETH_MDDIS_VALUE
 	immr->im_ioport.iop_padat |=   CFG_PA_ETH_MDDIS;
 #else
-	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS);	/* Set low */
+	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* Set low */
 #endif
-	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS);	/* GPIO */
-	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS);	/* active output */
-	immr->im_ioport.iop_padir |=   CFG_PA_ETH_MDDIS;	/* output */
+	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* GPIO */
+	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* active output */
+	immr->im_ioport.iop_padir |=   CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET;	/* output */
 
 	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
 	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */
@@ -419,7 +405,6 @@ void	reset_phy(void)
 
 	/* Assert Powerdown and Reset signals */
 	value |=  CFG_PB_ETH_POWERDOWN;
-	value &= ~(CFG_PB_ETH_RESET);
 
 	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
 #if CFG_ETH_CFG1_VALUE
@@ -448,190 +433,13 @@ void	reset_phy(void)
 	udelay (10000);
 
 	/* de-assert RESET signal of PHY */
-	immr->im_cpm.cp_pbdat |=   CFG_PB_ETH_RESET;
+	immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET;
 	udelay (1000);
 }
 
-/*-----------------------------------------------------------------------
- * Board Special Commands: access functions for "PUMA" FPGA
- */
-
-#define	PUMA_READ_MODE	0
-#define PUMA_LOAD_MODE	1
-
-#if (CONFIG_COMMANDS & CFG_CMD_BSP)
-
-int do_puma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-	ulong addr, len;
-
-	switch (argc) {
-	case 2:			/* PUMA reset */
-		if (strncmp(argv[1], "stat", 4) == 0) {		/* Reset */
-			puma_status ();
-			return 0;
-		}
-		break;
-	case 4:			/* PUMA load addr len */
-		if (strcmp(argv[1],"load") != 0)
-			break;
-
-		addr = simple_strtoul(argv[2], NULL, 16);
-		len  = simple_strtoul(argv[3], NULL, 16);
-
-		printf ("PUMA load: addr %08lX len %ld (0x%lX):  ",
-			addr, len, len);
-		puma_load (addr, len);
-
-		return 0;
-	default:
-		break;
-	}
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-}
-
-#endif	/* CFG_CMD_BSP */
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void puma_set_mode (int mode)
-{
-	volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immr->im_memctl;
-
-	/* disable PUMA in memory controller */
-	memctl->memc_br4 = 0;
-
-	switch (mode) {
-	case PUMA_READ_MODE:
-		memctl->memc_or4 = PUMA_CONF_OR_READ;
-		memctl->memc_br4 = PUMA_CONF_BR_READ;
-
-		/* (re-) enable CAN drivers */
-		can_driver_enable ();
-
-		break;
-	case PUMA_LOAD_MODE:
-
-		/*
-		 * We must disable the CAN drivers first because
-		 * they use UPM B, too.
-		 */
-		can_driver_disable ();
-
-		/*
-		 * Configure UPMB for PUMA
-		 */
-		upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
-
-		memctl->memc_or4 = PUMA_CONF_OR_LOAD;
-		memctl->memc_br4 = PUMA_CONF_BR_LOAD;
-		break;
-	}
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define	PUMA_INIT_TIMEOUT	1000	/* max. 1000 ms = 1 second */
-
-static void puma_load (ulong addr, ulong len)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
-	uchar *data = (uchar *)addr;
-	int i;
-
-	/* align length */
-	if (len & 1)
-		++len;
-
-	/* Reset FPGA */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT);	/* make input */
-	immr->im_ioport.iop_pcso  &= ~(CFG_PC_PUMA_INIT);
-	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
-
-	immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG);		/* GPIO */
-	immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG);		/* active output */
-	immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG);		/* Set low */
-	immr->im_cpm.cp_pbdir |=   CFG_PB_PUMA_PROG;		/* output */
-	udelay (100);
-
-	immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG;		/* release reset */
-
-	/* wait until INIT indicates completion of reset */
-	for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
-		udelay (1000);
-		if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
-			break;
-	}
-	if (i == PUMA_INIT_TIMEOUT) {
-		printf ("*** PUMA init timeout ***\n");
-		return;
-	}
-
-	puma_set_mode (PUMA_LOAD_MODE);
-
-	while (len--) {
-		*fpga_addr = *data++;
-	}
-
-	puma_set_mode (PUMA_READ_MODE);
-
-	puma_status ();
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void puma_status (void)
-{
-	/* Check state */
-	printf ("PUMA initialization is %scomplete\n",
-		puma_init_done() ? "" : "NOT ");
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static int puma_init_done (void)
-{
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
-	/* make sure pin is GPIO input */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
-	immr->im_ioport.iop_pcso  &= ~(CFG_PC_PUMA_DONE);
-	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
-
-	return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
-}
-
-/* ------------------------------------------------------------------------- */
 
 void misc_init_r (bd_t *dummy)
 {
-	ulong addr = 0;
-	ulong len  = 0;
-	char *s;
-
-	printf ("PUMA:  ");
-	if (puma_init_done()) {
-		printf ("initialized\n");
-		return;
-	}
-
-	if ((s = getenv("puma_addr")) != NULL)
-		addr = simple_strtoul(s, NULL, 16);
-
-	if ((s = getenv("puma_len")) != NULL)
-		len = simple_strtoul(s, NULL, 16);
-
-	if ((!addr) || (!len)) {
-		printf ("net list undefined\n");
-		return;
-	}
-
-	printf ("loading... ");
-
-	puma_load (addr, len);
+	fpga_init();
 }
-
 /* ------------------------------------------------------------------------- */
diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c
new file mode 100644
index 0000000..5f892e9
--- /dev/null
+++ b/board/siemens/CCM/fpga_ccm.c
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <ppcboot.h>
+
+#include "../common/fpga.h"
+ 
+fpga_t fpga_list[] = {
+    { "PUMA" , PUMA_CONF_BASE , 
+      CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE  }
+};
+int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
+
+void can_driver_enable (void);
+void can_driver_disable (void);
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*
+ * PUMA access using UPM B
+ */
+const uint puma_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+	/*
+	 * Precharge and MRS
+	 */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+ulong fpga_control (fpga_t* fpga, int cmd)
+{
+    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+    switch (cmd) {
+    case FPGA_INIT_IS_HIGH:
+	immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
+	return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
+	
+    case FPGA_INIT_SET_LOW:
+	immr->im_ioport.iop_pcdir |=  fpga->init_mask; /* output */
+	immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
+	break;
+	
+    case FPGA_INIT_SET_HIGH:
+	immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
+	immr->im_ioport.iop_pcdat |= fpga->init_mask;
+	break;
+	
+    case FPGA_PROG_SET_LOW:
+	immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
+	break;
+	
+    case FPGA_PROG_SET_HIGH:
+	immr->im_ioport.iop_pcdat |= fpga->prog_mask;
+	break;
+	
+    case FPGA_DONE_IS_HIGH:
+	return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
+	
+    case FPGA_READ_MODE:
+	/* disable FPGA in memory controller */
+	memctl->memc_br4 = 0;
+	memctl->memc_or4 = PUMA_CONF_OR_READ;
+	memctl->memc_br4 = PUMA_CONF_BR_READ;
+	
+	/* (re-) enable CAN drivers */
+	can_driver_enable ();
+	
+	break;
+
+    case FPGA_LOAD_MODE:
+	/* disable FPGA in memory controller */
+	memctl->memc_br4 = 0;
+	/*
+	 * We must disable the CAN drivers first because
+	 * they use UPM B, too.
+	 */
+	can_driver_disable ();
+	/*
+	 * Configure UPMB for FPGA
+	 */
+	upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
+	memctl->memc_or4 = PUMA_CONF_OR_LOAD;
+	memctl->memc_br4 = PUMA_CONF_BR_LOAD;
+	break;
+
+    case FPGA_GET_ID:
+	return *(volatile ulong *)fpga->conf_base;
+
+    case FPGA_INIT_PORTS:
+	immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
+	immr->im_ioport.iop_pcso  &= ~fpga->init_mask;
+	immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
+
+	immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
+	immr->im_ioport.iop_pcso  &= ~fpga->prog_mask;
+	immr->im_ioport.iop_pcdir |=  fpga->prog_mask;
+
+	immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
+	immr->im_ioport.iop_pcso  &= ~fpga->done_mask;
+	immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
+
+	break;
+
+    }
+    return 0;
+}
+
diff --git a/board/siemens/CCM/ppcboot.lds b/board/siemens/CCM/ppcboot.lds
index cbc1e6c..85cabb1 100644
--- a/board/siemens/CCM/ppcboot.lds
+++ b/board/siemens/CCM/ppcboot.lds
@@ -63,7 +63,7 @@ SECTIONS
     ppc/crc32.o		(.text)
     ppc/zlib.o		(.text)
 
-/*    . = env_offset; */
+    . = env_offset;
     common/environment.o(.text)
 
     *(.text)
diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile
new file mode 100644
index 0000000..94ba501
--- /dev/null
+++ b/board/siemens/SCM/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= scm.o flash.o  fpga_scm.o ../common/fpga.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk
new file mode 100644
index 0000000..01d2a34
--- /dev/null
+++ b/board/siemens/SCM/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Siemens SCM boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_SCM.h
+# for the "final" configuration, with ppcboot in flash, or the address
+# in RAM where ppcboot is loaded at for debugging.
+#
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c
new file mode 100644
index 0000000..b06bcd6
--- /dev/null
+++ b/board/siemens/SCM/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD devices on the TQM8260 board
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
+		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
+	flashtest_l = V_ULONG (baseaddr + 4);
+
+	switch ((int) flashtest_h) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash     */
+	}
+
+	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
+	flashtest_l = V_ULONG (baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+	} else {
+		switch (flashtest_h) {
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_DL322T:
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL322B:
+			info->flash_id += FLASH_AMDL322B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323T:
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323B:
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_LV640U:
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x02000000;
+			break;			/* 4 * 8 MB = 32 MB */
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);		/* no or unknown flash     */
+		}
+	}
+
+	if (flashtest_h == AMD_ID_LV640U) {
+
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+
+	} else {
+
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
+			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG (info->start[sect]) = 0x00300030;
+			V_ULONG (info->start[sect] + 4) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start, cl, ch;
+	int flag, i;
+
+	for (ch = 0, i = 0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word    */
+	for (cl = 0, i = 0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & ch) != ch
+		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest) = ch;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest + 4) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
+		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c
new file mode 100644
index 0000000..54ea223
--- /dev/null
+++ b/board/siemens/SCM/fpga_scm.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <ppcboot.h>
+#include <mpc8260.h>
+#include <ppcboot.h>
+#include "../common/fpga.h"
+ 
+fpga_t fpga_list[] = {
+    { "FIOX" , CFG_FIOX_BASE ,
+      CFG_PC_FIOX_INIT , CFG_PC_FIOX_PROG , CFG_PC_FIOX_DONE  },
+    { "FDOHM", CFG_FDOHM_BASE, 
+      CFG_PC_FDOHM_INIT, CFG_PC_FDOHM_PROG, CFG_PC_FDOHM_DONE }
+};
+int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
+
+
+ulong fpga_control (fpga_t* fpga, int cmd)
+{
+    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
+
+    switch (cmd) {
+    case FPGA_INIT_IS_HIGH:
+	immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
+	return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1:0;
+	
+    case FPGA_INIT_SET_LOW:
+	immr->im_ioport.iop_pdird |=  fpga->init_mask; /* output */
+	immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
+	break;
+	
+    case FPGA_INIT_SET_HIGH:
+	immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
+	immr->im_ioport.iop_pdatd |= fpga->init_mask;
+	break;
+	
+    case FPGA_PROG_SET_LOW:
+	immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
+	break;
+	
+    case FPGA_PROG_SET_HIGH:
+	immr->im_ioport.iop_pdatd |= fpga->prog_mask;
+	break;
+	
+    case FPGA_DONE_IS_HIGH:
+	return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
+	
+    case FPGA_READ_MODE:
+#if 0
+	/* disable FPGA in memory controller */
+	memctl->memc_br4 = 0;
+	memctl->memc_or4 = PUMA_CONF_OR_READ;
+	memctl->memc_br4 = PUMA_CONF_BR_READ;
+	
+	/* (re-) enable CAN drivers */
+	can_driver_enable ();
+#endif	
+	break;
+
+    case FPGA_LOAD_MODE:
+#if 0
+	/* disable FPGA in memory controller */
+	memctl->memc_br4 = 0;
+	/*
+	 * We must disable the CAN drivers first because
+	 * they use UPM B, too.
+	 */
+	can_driver_disable ();
+	/*
+	 * Configure UPMB for FPGA
+	 */
+	upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
+	memctl->memc_or4 = PUMA_CONF_OR_LOAD;
+	memctl->memc_br4 = PUMA_CONF_BR_LOAD;
+#endif
+	break;
+
+    case FPGA_GET_ID:
+	if (fpga->conf_base == CFG_FIOX_BASE)
+	    return (*(volatile ulong *)(fpga->conf_base + 0x10) >> 18) & 0xff;
+	else if (fpga->conf_base == CFG_FDOHM_BASE)
+	    return *(volatile ushort *)fpga->conf_base & 0xff;
+	else
+	    return *(volatile ulong *)fpga->conf_base;
+
+    case FPGA_INIT_PORTS:
+	immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
+	immr->im_ioport.iop_psord &= ~fpga->init_mask;
+	immr->im_ioport.iop_pdird &= ~fpga->init_mask;
+
+	immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
+	immr->im_ioport.iop_psord &= ~fpga->prog_mask;
+	immr->im_ioport.iop_pdird |=  fpga->prog_mask;
+
+	immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
+	immr->im_ioport.iop_psord &= ~fpga->done_mask;
+	immr->im_ioport.iop_pdird &= ~fpga->done_mask;
+
+	break;
+
+    }
+    return 0;
+}
+
diff --git a/board/siemens/SCM/ppcboot.lds b/board/siemens/SCM/ppcboot.lds
new file mode 100644
index 0000000..5df4cdb
--- /dev/null
+++ b/board/siemens/SCM/ppcboot.lds
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
new file mode 100644
index 0000000..32c9d29
--- /dev/null
+++ b/board/siemens/SCM/scm.c
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1]*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA9  */ {   1,   1,   1,   1,   0,   0   }, /* TDM_A1 L1TXD0 */
+	/* PA8  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RXD0 */
+	/* PA7  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1TSYNC */
+	/* PA6  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RSYNC */
+	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* FIOX_FPGA_PR */
+	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* DOHM_FPGA_PR */
+	/* PA3  */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK4 */
+	/* PA2  */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK4 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   },
+	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* BUSY */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MIN */
+	/* PB30 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MAJ */
+	/* PB29 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MIN */
+	/* PB28 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MAJ */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB25 */ {   1,   0,   0,   1,   0,   0   }, /* LED_GREEN_L */
+	/* PB24 */ {   1,   0,   0,   1,   0,   0   }, /* LED_RED_L */
+	/* PB23 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TXD */
+	/* PB22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RXD */
+	/* PB21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TSYNC */
+	/* PB20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RSYNC */
+	/* PB19 */ {   1,   0,   0,   0,   0,   0   }, /* UID */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   },
+        /* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+        /* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+        /* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+        /* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+        /* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+        /* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+        /* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+        /* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+        /* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+        /* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+        /* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+        /* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+        /* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+        /* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK1 */
+	/* PC30 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK1 */
+	/* PC29 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK3 */
+	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK3 */
+	/* PC27 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK2 */
+	/* PC26 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK2 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   },
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC18 */ {   0,   1,   0,   0,   0,   0   },
+        /* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+        /* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* RES_PHY_L */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC9  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TSYNC */
+	/* PC8  */ {   1,   0,   0,   0,   0,   0   }, /* FEP_RDY */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC6  */ {   1,   0,   0,   0,   0,   0   }, /* UC4_ALARM_L */
+	/* PC5  */ {   1,   0,   0,   0,   0,   0   }, /* UC3_ALARM_L */
+	/* PC4  */ {   1,   0,   0,   0,   0,   0   }, /* UC2_ALARM_L */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* RES_MISC_L */
+	/* PC2  */ {   1,   0,   0,   1,   0,   0   }, /* RES_OH_L */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* RES_DOHM_L */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* RES_FIOX_L */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* INIT_F */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_F */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* INIT_D */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_D */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TXD */
+	/* PD21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RXD */
+	/* PD20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RSYNC */
+	/* PD19 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPISEL */
+	/* PD18 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPICLK */
+	/* PD17 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSI */
+	/* PD16 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSO */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TXD */
+	/* PD12 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RXD */
+	/* PD11 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TSYNC */
+	/* PD10 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RSYNC */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   },
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   },
+	/* PD5  */ {   1,   0,   0,   1,   0,   1   }, /* PROG_F */
+	/* PD4  */ {   1,   0,   0,   1,   0,   1   }, /* PROG_D */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard(void)
+{
+    unsigned char str[64];
+    int i = getenv_r ("serial#", str, sizeof(str));
+
+    if (!i || strncmp(str, "TQM8260", 7)) {
+    	printf ("### No HW ID - assuming TQM8260\n");
+	return (1);
+    }
+
+    puts(str);
+    putc ('\n');
+
+    return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init(volatile memctl8260_t *memctl, ulong sdmr, ulong orx,
+		  volatile uchar * base)
+{
+    volatile uchar	c = 0xff;
+    ulong		cnt, val;
+    volatile ulong *	addr;
+    volatile uint *	sdmr_ptr;
+    volatile uint *	orx_ptr;
+    int			i;
+    ulong		save[32];	/* to make test non-destructive */
+    ulong		maxsize;
+
+    /* We must be able to test a location outsize the maximum legal size
+     * to find out THAT we are outside; but this address still has to be
+     * mapped by the controller. That means, that the initial mapping has
+     * to be (at least) twice as large as the maximum expected size.
+     */
+    maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+    /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+     * we are configuring CS1 if base != 0
+     */
+    sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+    orx_ptr  = base ? &memctl->memc_or2   : &memctl->memc_or1;
+
+    *orx_ptr = orx;
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     */
+
+    *sdmr_ptr = sdmr | PSDMR_OP_PREA;
+    *base = c;
+
+    *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*base = c;
+
+    *sdmr_ptr = sdmr | PSDMR_OP_MRW;
+    *(base + CFG_MRS_OFFS) = c;		/* setting MR on address lines */
+
+    *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *base = c;
+
+    /*
+     * Check memory range for valid RAM. A simple memory test determines
+     * the actually available RAM size between addresses `base' and
+     * `base + maxsize'. Some (not all) hardware errors are detected:
+     * - short between address lines
+     * - short between data lines
+     */
+    i = 0;
+    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+	addr = (volatile ulong *)base + cnt;	/* pointer arith! */
+	save[i++] = *addr;
+	*addr = ~cnt;
+    }
+
+    addr = (volatile ulong *)base;
+    save[i] = *addr;
+    *addr = 0;
+
+    if ((val = *addr) != 0) {
+	*addr = save[i];
+ 	return (0);
+    }
+
+    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+        addr = (volatile ulong *)base + cnt;	/* pointer arith! */
+	val = *addr;
+	*addr = save[--i];
+	if (val != ~cnt) {
+	    /* Write the actual size to ORx
+	     */
+    	    *orx_ptr = orx | ~(cnt * sizeof(long) - 1);
+	    return (cnt * sizeof(long));
+	}
+    }
+    return (maxsize);
+}
+
+/*
+ * Test Power-On-Reset.
+ */
+int power_on_reset(void)
+{
+    /* Test Reset Status Register */
+    return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
+}
+
+long int initdram(int board_type)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+#ifndef CFG_RAMBOOT
+    long size8, size9;
+#endif
+    long psize, lsize;
+
+    psize = 16 * 1024 * 1024;
+    lsize = 0;
+
+    memctl->memc_psrt = CFG_PSRT;
+    memctl->memc_mptpr = CFG_MPTPR;
+
+#if 0	/* Just for debugging */
+#define	prt_br_or(brX,orX) do {				\
+    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
+    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
+    printf ("\n"					\
+    	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
+	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
+	start, start+sizem, (sizem+1)>>20);		\
+    } while (0)
+    prt_br_or(br0,or0);
+    prt_br_or(br1,or1);
+    prt_br_or(br2,or2);
+    prt_br_or(br3,or3);
+#endif
+
+#ifndef CFG_RAMBOOT
+    /* 60x SDRAM setup:
+     */
+    size8 = try_init(memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+		(uchar *) CFG_SDRAM_BASE);
+    size9 = try_init(memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
+		(uchar *) CFG_SDRAM_BASE);
+
+    if (size8 < size9) {
+	psize = size9;
+	printf("(60x:9COL - %ld MB, ", psize >> 20);
+    } else {
+	psize = try_init(memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+		(uchar *) CFG_SDRAM_BASE);
+	printf("(60x:8COL - %ld MB, ", psize >> 20);
+    }
+
+    /* Local SDRAM setup:
+     */
+#ifdef CFG_INIT_LOCAL_SDRAM
+    memctl->memc_lsrt = CFG_LSRT;
+    size8 = try_init(memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+		(uchar *) SDRAM_BASE2_PRELIM);
+    size9 = try_init(memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+		(uchar *) SDRAM_BASE2_PRELIM);
+
+    if (size8 < size9) {
+	lsize = size9;
+	printf("Local:9COL - %ld MB) using ", lsize >> 20);
+    } else {
+	lsize = try_init(memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+		(uchar *) SDRAM_BASE2_PRELIM);
+	printf("Local:8COL - %ld MB) using ", lsize >> 20);
+    }
+
+#if 0
+    /* Set up BR2 so that the local SDRAM goes
+     * right after the 60x SDRAM
+     */
+    memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
+		       (CFG_SDRAM_BASE + psize);
+#endif
+#endif /* CFG_INIT_LOCAL_SDRAM */
+#endif /* CFG_RAMBOOT */
+
+    icache_enable();
+
+    return (psize);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The TQM8xxL / TQM82xx Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset 0x0003FFC0
+ * - size 0x00000040
+ *
+ * Internal structure:
+ * - sequence of ASCII character strings
+ * - fields separated by a single space character (0x20)
+ * - last field terminated by NUL character (0x00)
+ * - remaining space filled with NUL characters (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) Serial Number
+ * 3) First MAC Address
+ * 4) Number of additional MAC addresses
+ */
+
+void load_sernum_ethaddr (bd_t *bd)
+{
+	unsigned char *hwi;
+	unsigned char  serial [CFG_HWINFO_SIZE];
+	unsigned char  ethaddr[CFG_HWINFO_SIZE];
+	unsigned short ih, is, ie, part;
+	
+	hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
+	ih = is = ie = 0;
+
+	if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) {
+		return;
+	}
+
+	part = 1;
+
+	/* copy serial # / MAC address */
+	while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) {
+		if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
+			return;
+		}
+		switch (part) {
+		default:		/* Copy serial # */
+			if (hwi[ih] == ' ') {
+				++part;
+			}
+			serial[is++] = hwi[ih];
+			break;
+		case 3:			/* Copy MAC address */
+			if (hwi[ih] == ' ') {
+				++part;
+				break;
+			}
+			ethaddr[ie++] = hwi[ih];
+			if ((ie % 3) == 2)
+				ethaddr[ie++] = ':';
+			break;
+		}
+		++ih;
+	}
+	serial[is]  = '\0';
+	if (ie && ethaddr[ie-1] == ':')
+		--ie;
+	ethaddr[ie] = '\0';
+
+	/* set serial# and ethaddr if not yet defined */
+	if (getenv("serial#") == NULL) {
+		setenv ("serial#", serial);
+	}
+
+	if (getenv("ethaddr") == NULL) {
+		setenv ("ethaddr", ethaddr);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+void misc_init_r (bd_t *dummy)
+{
+	fpga_init();
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/common/README b/board/siemens/common/README
new file mode 100644
index 0000000..81e8eaf
--- /dev/null
+++ b/board/siemens/common/README
@@ -0,0 +1,27 @@
+CCM/SCM-Ergaenzungen fuer PPCboot und Linux:
+-------------------------------------------
+
+Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
+
+  => help fpga
+  fpga fpga status [name] - print FPGA status
+  fpga reset  [name] - reset FPGA
+  fpga load [name] addr - load FPGA configuration data
+
+Der Name kann beim CCM-Module auch weggelassen werden.
+Die Laengenangabe und damit "puma_len" ist nicht mehr 
+noetig:
+
+  => fpga load puma 40600000
+  FPGA load PUMA: addr 40600000: (00000005)... done
+
+Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
+geben werden:
+
+  => printenv addmtd
+  addmtd=setenv bootargs $(bootargs) 
+    mtdparts=0:256k(PPCboot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
+
+Die Portierung auf SMC ist natuerlich noch nicht getestet.
+
+Wolfgang Grandegger (04.06.2002)
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
new file mode 100644
index 0000000..db5cd7c
--- /dev/null
+++ b/board/siemens/common/fpga.c
@@ -0,0 +1,328 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <ppcboot.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <ppcboot.h>
+#include <cmd_boot.h>
+#include <cmd_bsp.h>
+
+#include "fpga.h"
+
+int  power_on_reset(void);
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+fpga_t* fpga_get(char* fpga_name)
+{
+    char name[FPGA_NAME_LEN];
+    int i;
+
+    if (strlen(fpga_name) >= FPGA_NAME_LEN)
+	goto failure;
+    for (i = 0; i < strlen(fpga_name); i++)
+	name[i] = toupper(fpga_name[i]);
+    name[i] = '\0';
+    for (i = 0; i < fpga_count; i++) {
+	if (strcmp(name, fpga_list[i].name) == 0)
+	    return &fpga_list[i];
+    }
+ failure:
+    printf("FPGA: name %s is invalid\n", fpga_name);
+    return NULL;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void fpga_status (fpga_t* fpga)
+{
+    /* Check state */
+    if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
+	printf ("%s is loaded (%08lx)\n", 
+		fpga->name, fpga_control(fpga, FPGA_GET_ID));
+    else
+	printf ("%s is NOT loaded\n", fpga->name);
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
+
+static int fpga_reset (fpga_t* fpga)
+{
+    int i;
+    
+    /* Set PROG to low and wait til INIT goes low */
+    fpga_control(fpga, FPGA_PROG_SET_LOW);
+    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
+	udelay (100);
+	if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_RESET_TIMEOUT)
+	goto failure;
+
+    /* Set PROG to high and wait til INIT goes high */
+    fpga_control(fpga, FPGA_PROG_SET_HIGH);
+    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
+	udelay (100);
+	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_RESET_TIMEOUT)
+	goto failure;
+
+    return 0;
+ failure:
+    return 1;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
+
+static int fpga_load (fpga_t* fpga, ulong addr)
+{
+    volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
+    image_header_t hdr;
+    ulong len, checksum;
+    uchar *data = (uchar *)&hdr;
+    char *s, msg[32];
+    int verify, id, i;
+    
+    /* 
+     * Check the image header and data of the net-list
+     */
+    memcpy (&hdr, (char *)addr, sizeof(image_header_t));
+    
+    if (hdr.ih_magic != IH_MAGIC) {
+	strcpy (msg, "Bad Image Magic Number");
+        goto failure;
+    }
+    
+    len  = sizeof(image_header_t);
+	
+    checksum = hdr.ih_hcrc;
+    hdr.ih_hcrc = 0;
+    
+    if (crc32 (0, data, len) != checksum) {
+	strcpy (msg, "Bad Image Header CRC");
+	goto failure;
+    }
+    
+    data = (uchar*)(addr + sizeof(image_header_t));
+    len  = hdr.ih_size;
+
+    s = getenv ("verify");
+    verify = (s && (*s == 'n')) ? 0 : 1;
+    if (verify) {
+	if (crc32 (0, data, len) != hdr.ih_dcrc) {
+	    strcpy (msg, "Bad Image Data CRC");
+	    goto failure;
+	}
+    }
+
+    id   = simple_strtoul (hdr.ih_name, NULL, 16);
+    
+    /* align length */
+    if (len & 1)
+	++len;
+    
+    /* 
+     * Reset FPGA and wait for completion
+     */
+    if (fpga_reset(fpga)) {
+	strcpy (msg, "Reset Timeout");
+	goto failure;
+    }
+
+    printf ("(%s)... ", hdr.ih_name);
+    /*
+     * Copy data to FPGA
+     */
+    fpga_control (fpga, FPGA_LOAD_MODE);
+    while (len--) {
+	*fpga_addr = *data++;
+    }
+    fpga_control (fpga, FPGA_READ_MODE);
+    
+    /* 
+     * Wait for completion and check error status if timeout
+     */
+    for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
+	udelay (100);
+	if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_LOAD_TIMEOUT) {
+	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    strcpy(msg, "Invalid Size");
+	else
+	    strcpy(msg, "CRC Error");
+	goto failure;
+    }
+
+    printf("done\n");
+    return 0;
+
+ failure:
+
+    printf("ERROR: %s\n", msg);
+    return 1;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+int do_fpga (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+    ulong addr = 0;
+    int i;
+    fpga_t* fpga;
+    
+    if (argc < 2)
+	goto failure;
+
+    if (strncmp(argv[1], "stat", 4) == 0) {		/* status */
+	if (argc == 2) {
+	    for (i = 0; i < fpga_count; i++) {
+		fpga_status (&fpga_list[i]);
+	    }
+	}
+	else if (argc == 3) {
+	    if ((fpga = fpga_get(argv[2])) == 0) 
+		goto failure;
+	    fpga_status (fpga);
+	}
+	else
+	    goto failure;
+    }
+    else if (strcmp(argv[1],"load") == 0) {		/* load */
+	if (argc == 3 && fpga_count == 1) {
+	    fpga = &fpga_list[0];
+	}
+	else if (argc == 4) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	}
+	else
+	    goto failure;
+
+	addr = simple_strtoul(argv[argc-1], NULL, 16);
+	
+	printf ("FPGA load %s: addr %08lx: ",
+		fpga->name, addr);
+	fpga_load (fpga, addr);
+	
+    }
+    else if (strncmp(argv[1], "rese", 4) == 0) {	/* reset */
+	if (argc == 2 && fpga_count == 1) {
+	    fpga = &fpga_list[0];
+	}
+	else if (argc == 3) {
+	    if ((fpga = fpga_get(argv[2])) == 0) 
+		goto failure;
+	}
+	else 
+	    goto failure;
+	
+	printf ("FPGA reset %s: ", fpga->name);
+	if (fpga_reset(fpga))
+	    printf ("ERROR: Timeout\n");
+	else
+	    printf ("done\n");
+    }
+    else
+	goto failure;
+
+    return 0;
+
+ failure:
+    printf ("Usage:\n%s\n", cmdtp->usage);
+    return 1;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_BSP */
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+int fpga_init (void)
+{
+    ulong addr;
+    ulong new_id, old_id = 0;
+    image_header_t *hdr;
+    fpga_t* fpga;
+    int do_load, i, j;
+    char name[16], *s;
+    
+    /* 
+     *  Port setup for FPGA control
+     */
+    for (i = 0; i < fpga_count; i++) {
+	fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
+    }
+    
+    /* 
+     * Load FPGA(s): a new net-list is loaded if the FPGA is 
+     * empty, Power-on-Reset or the old one is not up-to-date
+     */
+    for (i = 0; i < fpga_count; i++) {
+	fpga = &fpga_list[i];
+	printf ("%s:  ", fpga->name);
+
+	for (j = 0; j < strlen(fpga->name); j++)
+	    name[j] = tolower(fpga->name[j]);
+	name[j] = '\0';
+	sprintf(name, "%s_addr", name);
+	addr = 0;
+	if ((s = getenv(name)) != NULL)
+	    addr = simple_strtoul(s, NULL, 16);
+
+	if (!addr) {
+	    printf ("env. variable %s undefined\n", name);
+	    return 1;
+	} 
+	
+	hdr = (image_header_t *)addr;
+	new_id = simple_strtoul(hdr->ih_name, NULL, 16);
+	do_load = 1;
+
+	if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
+	    old_id = fpga_control(fpga, FPGA_GET_ID);
+	    if (new_id <= old_id) 
+		do_load = 0;
+	}
+
+	if (do_load) {
+	    printf ("loading ");
+	    fpga_load (fpga, addr);
+	} else {
+	    printf ("loaded (%08lx)\n", old_id);
+	}
+    }
+
+    return 0;
+}
diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h
new file mode 100644
index 0000000..2de25b0
--- /dev/null
+++ b/board/siemens/common/fpga.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#define FPGA_INIT_IS_HIGH   0
+#define FPGA_INIT_SET_HIGH  1
+#define FPGA_INIT_SET_LOW   2
+#define FPGA_PROG_SET_HIGH  3
+#define FPGA_PROG_SET_LOW   4
+#define FPGA_DONE_IS_HIGH   5
+#define	FPGA_READ_MODE      6
+#define FPGA_LOAD_MODE      7
+#define FPGA_GET_ID         8
+#define FPGA_INIT_PORTS     9
+
+#define FPGA_NAME_LEN       8
+typedef struct {
+    char  name[FPGA_NAME_LEN];
+    ulong conf_base;
+    uint  init_mask;
+    uint  prog_mask;
+    uint  done_mask;
+} fpga_t;
+
+extern fpga_t fpga_list[];
+extern int    fpga_count;
+
+ulong fpga_control (fpga_t* fpga, int cmd);
+
+#endif /* _FPGA_H_ */
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index da068a9..7f1a90d 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -109,9 +109,11 @@ int do_eeprom (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc,
 
 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM)
 
+#ifndef CONFIG_SPI
 #if !defined(CFG_I2C_EEPROM_ADDR_LEN) || CFG_I2C_EEPROM_ADDR_LEN < 1 || CFG_I2C_EEPROM_ADDR_LEN > 2
 #error CFG_I2C_EEPROM_ADDR_LEN must be 1 or 2
 #endif
+#endif
 
 int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
 {
diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h
index df56de1..281432e 100644
--- a/include/cmd_bsp.h
+++ b/include/cmd_bsp.h
@@ -58,7 +58,7 @@ int do_lsb (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
 
 /* ----- PCU E -----------------------------------------------------------------
  */
-#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM)
+#if defined(CONFIG_PCU_E)
 
 #define CMD_TBL_BSP	MK_CMD_TBL_ENTRY(					\
 	"puma",	4,	4,	1,	do_puma,				\
@@ -68,7 +68,23 @@ int do_lsb (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
 ),
 int do_puma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
 
-#endif	/* CONFIG_PCU_E, CONFIG_CCM */
+#endif	/* CONFIG_PCU_E */
+/* ----------------------------------------------------------------------------*/
+
+/* ----- CCM/SCM ---------------------------------------------------------------
+ */
+#if defined(CONFIG_CCM) || defined(CONFIG_SCM) 
+
+#define CMD_TBL_BSP	MK_CMD_TBL_ENTRY(					\
+	"fpga",	4,	4,	1,	do_fpga,				\
+	"fpga    - access FPGA(s)\n",						\
+	"fpga status [name] - print FPGA status\n"				\
+	"fpga reset  [name] - reset FPGA\n"					\
+	"fpga load [name] addr - load FPGA configuration data\n"		\
+),
+int do_fpga (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+
+#endif	/* CONFIG_CCM, CONFIG_SCM */
 /* ----------------------------------------------------------------------------*/
 
 /* ----- PIP405 -----------------------------------------------------------------
diff --git a/include/config_CCM.h b/include/config_CCM.h
index 57cdf3e..979f374 100644
--- a/include/config_CCM.h
+++ b/include/config_CCM.h
@@ -35,48 +35,50 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC860		1	/* This is a MPC860 CPU	...	*/
-#define CONFIG_CCM		1	/* on a Card Controller Module	*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600 bps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
+#define CONFIG_MPC860           1   /* This is a MPC860 CPU ... */
+#define CONFIG_CCM              1   /* on a Card Controller Module  */
+
+#define CONFIG_8xx_CONS_SMC1    1   /* Console is on SMC1       */
+#undef  CONFIG_8xx_CONS_SMC2
+#undef  CONFIG_8xx_CONS_NONE
+
+/*  ENVIRONMENT */
+
+#define CONFIG_BAUDRATE         19200         /* console baudrate in bps    */
+#define CONFIG_BOOTDELAY        2             /* autoboot after 2 seconds   */
+#define CONFIG_CLOCKS_IN_MHZ    1             /* clocks passsed to Linux in MHz */
+
+#define CONFIG_IPADDR           192.168.0.42
+#define CONFIG_NETMASK          255.255.255.0 
+#define CONFIG_GATEWAYIP        0.0.0.0
+#define CONFIG_SERVERIP         192.168.0.254
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_HOSTNAME         CCM
 
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;" 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" 	\
-	"bootm"
+#define CONFIG_LOADADDR         40180000
+
+#undef	CONFIG_BOOTARGS  
+
+#define CONFIG_BOOTCOMMAND      "setenv bootargs " \
+                                "mem=$(mem) " \
+                                "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
+                                "wt_8xx=timeout:3600; " \
+                                "bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CFG_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
 
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
 
-#define	CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM"	*/
+#define	CONFIG_PRAM		512	/* reserve 512kB "protected RAM"*/
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
 #define	CONFIG_SPI			/* enable SPI driver		*/
 #define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/
 
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef  CONFIG_SOFT_I2C
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE           0x7F
-
-
 /* ----------------------------------------------------------------
  * Offset to initial SPI buffers in DPRAM (used if the environment
  * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
@@ -87,6 +89,8 @@
  * ---------------------------------------------------------------- */
 #define CFG_SPI_INIT_OFFSET		0xB00
 
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-byte page size	*/
+
 
 #define CONFIG_MAC_PARTITION		/* nod used yet			*/
 #define CONFIG_DOS_PARTITION
@@ -96,7 +100,7 @@
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_BSP	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -124,12 +128,12 @@
 #define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
 
 /* Ethernet hardware configuration done using port pins */
-#define CFG_PB_ETH_RESET	0x00000020		/* PB 26	*/
-#define CFG_PA_ETH_MDDIS	0x4000			/* PA  1	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000800		/* PB 20	*/
-#define CFG_PB_ETH_CFG1		0x00000400		/* PB 21	*/
-#define CFG_PB_ETH_CFG2		0x00000200		/* PB 22	*/
-#define CFG_PB_ETH_CFG3		0x00000100		/* PB 23	*/
+#define CFG_PA_ETH_RESET 	0x0200		/* PA  6	*/
+#define CFG_PA_ETH_MDDIS	0x4000		/* PA  1	*/
+#define CFG_PB_ETH_POWERDOWN	0x00000800	/* PB 20	*/
+#define CFG_PB_ETH_CFG1		0x00000400	/* PB 21	*/
+#define CFG_PB_ETH_CFG2		0x00000200	/* PB 22	*/
+#define CFG_PB_ETH_CFG3		0x00000100	/* PB 23	*/
 
 /* Ethernet settings:
  * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
@@ -140,9 +144,9 @@
 #define CFG_ETH_CFG3_VALUE	1
 
 /* PUMA configuration */
-#define CFG_PB_PUMA_PROG	0x00000010		/* PB 27	*/
-#define CFG_PC_PUMA_DONE	0x0008			/* PC 12	*/
-#define CFG_PC_PUMA_INIT	0x0004			/* PC 13	*/
+#define CFG_PC_PUMA_PROG	0x0200		/* PC  6        */
+#define CFG_PC_PUMA_DONE	0x0008		/* PC 12	*/
+#define CFG_PC_PUMA_INIT	0x0004		/* PC 13	*/
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
@@ -203,7 +207,7 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#if 0
+#if 1
 /* Start port with environment in flash; switch to SPI EEPROM later */
 #define	CFG_ENV_IS_IN_FLASH	1
 #define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -211,8 +215,6 @@
 #else
 /* Final version: environment in EEPROM */
 #define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0
-#define CFG_I2C_EEPROM_ADDR_LEN	2
 #define CFG_ENV_OFFSET		2048
 #define CFG_ENV_SIZE		2048
 #endif
@@ -362,7 +364,7 @@
 #define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 
-/*
+/* 
  * BR4/OR4: PUMA Config
  *
  * Memory controller will be used in 2 modes:
@@ -377,7 +379,7 @@
 #define PUMA_CONF_BASE		0x10100000	/* PUMA Config */
 #define PUMA_CONF_OR_AM		0xFFFF8000	/* 32 kB */
 #define	PUMA_CONF_LOAD_TIMING	(OR_ACS_DIV2	 | OR_SCY_2_CLK)
-#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_0_CLK)
+#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_2_CLK)
 
 #define PUMA_CONF_BR_LOAD	((PUMA_CONF_BASE & BR_BA_MSK) | \
 					BR_PS_8  | BR_MS_UPMB | BR_V)
diff --git a/include/config_SCM.h b/include/config_SCM.h
new file mode 100644
index 0000000..8aa9981
--- /dev/null
+++ b/include/config_SCM.h
@@ -0,0 +1,722 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Imported from global configuration:
+ *	CONFIG_L2_CACHE
+ *	CONFIG_266MHz
+ *	CONFIG_300MHz
+ */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+
+#define CONFIG_SCM              1	/* ...on a System Controller Module	*/
+
+/* Define 60x busmode only if your TQM8260 has L2 cache! */
+#ifdef CONFIG_L2_CACHE
+#  define CONFIG_BUSMODE_60x	1	/* bus mode: 60x			*/
+#else
+#  undef  CONFIG_BUSMODE_60x		/* bus mode: 8260			*/
+#endif
+
+/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
+#ifdef CONFIG_300MHz
+#  define CONFIG_BUSMODE_60x
+#endif
+
+#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
+	"bootm"
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
+#if (CONFIG_TQM8260 <= 100)
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00020000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00020000)
+#define I2C_READ	((iop->pdat & 0x00020000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#else
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif
+
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#ifdef CONFIG_82xx_CONS_SMC1
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#endif
+#ifdef CONFIG_82xx_CONS_SMC2
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+#endif
+
+#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
+ * X.29 connector, and FCC2 is hardwired to the X.1 connector)
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK12
+ * - Tx-CLK is CLK11
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE 	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifndef CONFIG_300MHz
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#else
+#define CONFIG_8260_CLKIN	83333000	/* in Hz */
+#endif
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		19200
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH1_BASE 0x60000000
+#define CFG_FLASH0_SIZE 32
+#define CFG_FLASH1_SIZE 32
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if defined(CONFIG_266MHz)
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+				                              HRCW_MODCK_H0111)
+#elif defined(CONFIG_300MHz)
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+				                              HRCW_MODCK_H0110)
+#else
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CFG_INIT_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+                                HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#ifdef	CONFIG_BUSMODE_60x
+#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
+			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
+#else
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
+#else
+#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+                         SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  2   Local   SDRAM   32 bit  SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CFG_INIT_LOCAL_SDRAM
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
+
+#define CFG_MPTPR       0x4000
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ * In fact, the address is rather configuration data presented to the SDRAM on
+ * its address lines. Because the address lines may be mux'ed externally either
+ * for 8 column or 9 column devices, some bits appear twice in the 8260's
+ * address:
+ *
+ * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
+ * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
+ *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+                         BRx_PS_64                      |\
+                         BRx_MS_GPCM_P                  |\
+                         BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+                         ORxG_CSNT                      |\
+                         ORxG_ACS_DIV1                  |\
+                         ORxG_SCY_3_CLK                 |\
+                         ORxG_EHTR                      |\
+                         ORxG_TRLX)
+
+	/* SDRAM on TQM8260 can have either 8 or 9 columns.
+	 * The number affects configuration values.
+	 */
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20
+#define CFG_LSRT        0x20
+#ifndef CFG_RAMBOOT
+#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+                         BRx_PS_64                      |\
+                         BRx_MS_SDRAM_P                 |\
+                         BRx_V)
+
+#define CFG_OR1_PRELIM	CFG_OR1_8COL
+
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+                         ORxS_BPD_4                     |\
+                         ORxS_ROWST_PBI1_A7             |\
+                         ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+                         PSDMR_SDAM_A15_IS_A5           |\
+                         PSDMR_BSMA_A12_A14             |\
+                         PSDMR_SDA10_PBI1_A8            |\
+                         PSDMR_RFRC_7_CLK               |\
+                         PSDMR_PRETOACT_2W              |\
+                         PSDMR_ACTTORW_2W               |\
+                         PSDMR_LDOTOPRE_1C              |\
+                         PSDMR_WRC_2C                   |\
+                         PSDMR_EAMUX                    |\
+                         PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+                         ORxS_BPD_4                     |\
+                         ORxS_ROWST_PBI1_A5             |\
+                         ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+                         PSDMR_SDAM_A16_IS_A5           |\
+                         PSDMR_BSMA_A12_A14             |\
+                         PSDMR_SDA10_PBI1_A7            |\
+                         PSDMR_RFRC_7_CLK               |\
+                         PSDMR_PRETOACT_2W              |\
+                         PSDMR_ACTTORW_2W               |\
+                         PSDMR_LDOTOPRE_1C              |\
+                         PSDMR_WRC_2C                   |\
+                         PSDMR_EAMUX                    |\
+                         PSDMR_CL_2)
+
+/* Bank 2 - Local bus SDRAM
+ */
+#ifdef CFG_INIT_LOCAL_SDRAM
+#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
+                         BRx_PS_32                      |\
+                         BRx_MS_SDRAM_L                 |\
+                         BRx_V)
+
+#define CFG_OR2_PRELIM	CFG_OR2_8COL
+
+#define SDRAM_BASE2_PRELIM	0x80000000
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+                         ORxS_BPD_4                     |\
+                         ORxS_ROWST_PBI1_A8             |\
+                         ORxS_NUMR_12)
+
+#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
+                         PSDMR_SDAM_A15_IS_A5           |\
+                         PSDMR_BSMA_A13_A15             |\
+                         PSDMR_SDA10_PBI1_A9            |\
+                         PSDMR_RFRC_7_CLK               |\
+                         PSDMR_PRETOACT_2W              |\
+                         PSDMR_ACTTORW_2W               |\
+                         PSDMR_BL                       |\
+                         PSDMR_LDOTOPRE_1C              |\
+                         PSDMR_WRC_2C                   |\
+                         PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+                         ORxS_BPD_4                     |\
+                         ORxS_ROWST_PBI1_A6             |\
+                         ORxS_NUMR_13)
+
+#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
+                         PSDMR_SDAM_A16_IS_A5           |\
+                         PSDMR_BSMA_A13_A15             |\
+                         PSDMR_SDA10_PBI1_A8            |\
+                         PSDMR_RFRC_7_CLK               |\
+                         PSDMR_PRETOACT_2W              |\
+                         PSDMR_ACTTORW_2W               |\
+                         PSDMR_BL                       |\
+                         PSDMR_LDOTOPRE_1C              |\
+                         PSDMR_WRC_2C                   |\
+                         PSDMR_CL_2)
+
+#endif /* CFG_INIT_LOCAL_SDRAM */
+
+#endif /* CFG_RAMBOOT */
+
+#define CFG_CAN0_BASE		0xc0000000
+#define CFG_CAN1_BASE		0xc0008000
+#define CFG_FIOX_BASE		0xc0010000
+#define CFG_FDOHM_BASE		0xc0018000
+#define CFG_EXTPROM_BASE	0xc2000000
+
+#define CFG_CAN_SIZE		0x00000100
+#define CFG_FIOX_SIZE		0x00000020
+#define CFG_FDOHM_SIZE		0x00002000
+#define CFG_EXTPROM_BANK_SIZE	0x01000000
+
+#define EXT_EEPROM_MAX_FLASH_BANKS	0x02
+
+/* CS3 - CAN 0
+ */
+#define CFG_CAN0_BR3  ((CFG_CAN0_BASE & BRx_BA_MSK) |\
+                       BRx_PS_8                     |\
+                       BRx_MS_GPCM_P                |\
+                       BRx_V)
+
+#define CFG_CAN0_OR3  (P2SZ_TO_AM(CFG_CAN_SIZE)     |\
+                       ORxG_CSNT                    |\
+                       ORxG_ACS_DIV4                |\
+                       ORxG_SETA	            |	/* Ext. access termination */\
+                       ORxG_TRLX)
+/* CS4 - CAN 1
+ */
+#define CFG_CAN1_BR4  ((CFG_CAN1_BASE & BRx_BA_MSK) |\
+                       BRx_PS_8                     |\
+                       BRx_MS_GPCM_P                |\
+                       BRx_V)
+
+#define CFG_CAN1_OR4  (P2SZ_TO_AM(CFG_CAN_SIZE)     |\
+                       ORxG_CSNT                    |\
+                       ORxG_ACS_DIV4                |\
+                       ORxG_SETA	            |	/* Ext. access termination */\
+                       ORxG_TRLX)
+
+/* CS5 - Extended PROM (16MB optional)
+ */
+#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
+                          BRx_PS_32                 |\
+                          BRx_MS_GPCM_P             |\
+                          BRx_V)
+
+#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
+                         ORxG_CSNT                  |\
+                         ORxG_ACS_DIV4              |\
+                         ORxG_SCY_5_CLK             |	/* Wait time: 2*SCY */\
+                         ORxG_TRLX)
+
+/* CS6 - Extended PROM (16MB optional)
+ */
+#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE +        \
+                           CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
+                          BRx_PS_32                 |\
+                          BRx_MS_GPCM_P             |\
+                          BRx_V)
+
+#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
+                         ORxG_CSNT                  |\
+                         ORxG_ACS_DIV4              |\
+                         ORxG_SCY_5_CLK             |	/* Wait time: 2*SCY */\
+                         ORxG_TRLX)
+
+/* CS7 - FIOX: Glue Logic
+ */
+#define CFG_FIOX_BR7  ((CFG_FIOX_BASE & BRx_BA_MSK) |\
+                       BRx_PS_32                    |\
+                       BRx_MS_GPCM_P                |\
+                       BRx_V)
+
+#define CFG_FIOX_OR7  (P2SZ_TO_AM(CFG_FIOX_SIZE)    |\
+                       ORxG_CSNT                    |\
+                       ORxG_ACS_DIV4                |\
+                       ORxG_SCY_5_CLK               |	/* Wait time: 2*SCY */\
+                       ORxG_TRLX)
+
+/* CS8 - DOH Master
+ */
+#define CFG_DOH_BR8   ((CFG_FDOHM_BASE & BRx_BA_MSK)|\
+                       BRx_PS_16                    |\
+                       BRx_MS_GPCM_P                |\
+                       BRx_V)
+
+#define CFG_DOH_OR8   (P2SZ_TO_AM(CFG_FDOHM_SIZE)   |\
+                       ORxG_CSNT                    |\
+                       ORxG_ACS_DIV4                |\
+                       ORxG_SCY_5_CLK               |	/* Wait time: 2*SCY */\
+                       ORxG_TRLX)
+
+
+/* FPGA configuration */
+#define CFG_PC_FIOX_PROG	(1 << (31- 5))	/* PD  5        */
+#define CFG_PC_FIOX_DONE	(1 << (31-28))	/* PD 28	*/
+#define CFG_PC_FIOX_INIT	(1 << (31-29))	/* PD 29	*/
+
+#define CFG_PC_FDOHM_PROG	(1 << (31- 4))	/* PD  4        */
+#define CFG_PC_FDOHM_DONE	(1 << (31-26))	/* PD 26	*/
+#define CFG_PC_FDOHM_INIT	(1 << (31-27))	/* PD 27	*/
+
+
+#endif	/* __CONFIG_H */