From: mariusgroeger Date: Mon, 15 Jul 2002 06:49:56 +0000 (+0000) Subject: Added support for SMDK2410 eval board (David Müller ) X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f2662c76955f750a7f4290a5b6448af3ab3629e0;p=users%2Frw%2Farmboot.git Added support for SMDK2410 eval board (David Müller ) --- diff --git a/CHANGELOG b/CHANGELOG index 0376f7d..fb10bd0 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Recent changes ====================================================================== +* Added support for SMDK2410 eval board (David Müller ) + * Fix write_p15_c1() for ARM720,ARM920 * Fix to support multilib toolchains (David Müller ) diff --git a/CREDITS b/CREDITS index 0aef45c..8229c90 100644 --- a/CREDITS +++ b/CREDITS @@ -31,3 +31,7 @@ W: http://www.denx.de N: Gary Jennejohn E: garyj@jennejohn.org, gj@denx.de D: Support for Samsung ARM920T S3C2400X + +N: David Müller +E: d.mueller@elsoft.ch +D: Support for Samsung ARM920T SMDK2410 eval board diff --git a/MAKEALL b/MAKEALL index 16abc24..868cd8f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -26,7 +26,7 @@ LIST_ARM7="impa7 ep7312" ## ARM9 Systems ######################################################################### -LIST_ARM9="samsung" +LIST_ARM9="samsung smdk2410" LIST_all="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9}" diff --git a/Makefile b/Makefile index b6bc5e9..9b51771 100644 --- a/Makefile +++ b/Makefile @@ -176,12 +176,20 @@ samsung_config : unconfig echo "CPU = arm920t" >>config.mk ; \ echo "#include " >config.h +smdk2410_config : unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = arm" > config.mk ; \ + echo "BOARD = smdk2410" >>config.mk ; \ + echo "CPU = arm920t" >>config.mk ; \ + echo "#include " >config.h + ######################################################################### clean: find . -type f \ \( -name 'core' -o -name '*.bak' -o -name '*~' \ - -o -name '*.o' -o -name '*.a' \) -print \ + -o -name '*.o' -o -name '*.a' -o -name '.depend' \) -print \ | xargs rm -f rm -f examples/hello_world examples/timer rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr diff --git a/README b/README index 869fae2..1e13bef 100644 --- a/README +++ b/README @@ -104,3 +104,4 @@ Shannon shannon_config Tuxscreen (no support for implementa impA7 impa7_config EP7211 based CLEP7312 ep7312_config Cirrus Logic EP7312 Dev. Board S3C2400X samsung_config Samsung S3C2400X +SMDK2410X smdk2410_config Samsung SMDK2410X Eval Board diff --git a/board/samsung/samsung.c b/board/samsung/samsung.c index 0a93b25..d6e4983 100644 --- a/board/samsung/samsung.c +++ b/board/samsung/samsung.c @@ -26,6 +26,7 @@ */ #include "armboot.h" +#include "s3c2400.h" /* ------------------------------------------------------------------------- */ @@ -37,7 +38,22 @@ int board_init(bd_t *bd) { /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ + /* change the clock to be 50 MHz 1:1:1 */ + rMPLLCON = 0x5c042; + rCLKDIVN = 0; + /* set up the I/O ports */ + rPACON = 0x3ffff; + rPBCON=0xaaaaaaaa; + rPBUP=0xffff; + rPECON=0x0; + rPEUP=0x0; + /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ + /* 00, 00, 00, 00, 10, 00, 10 */ + rPFCON=0x22; + rPFUP=0x5; + rPGCON=0x0; + rPGUP=0x0; + rOPENCR=0x0; /* arch number of SAMSUNG-Board */ /* I have no idea what this means, so I just picked an unused value */ diff --git a/board/smdk2410/Makefile b/board/smdk2410/Makefile new file mode 100644 index 0000000..3c510f3 --- /dev/null +++ b/board/smdk2410/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := smdk2410.o flash.o env.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/smdk2410/armboot.lds b/board/smdk2410/armboot.lds new file mode 100644 index 0000000..e25d261 --- /dev/null +++ b/board/smdk2410/armboot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + .bss : { *(.bss) } + + armboot_end = .; +} diff --git a/board/smdk2410/config.mk b/board/smdk2410/config.mk new file mode 100644 index 0000000..aba735d --- /dev/null +++ b/board/smdk2410/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +# +# SMDK2410 has 1 bank of 32 MB DRAM +# +# 3000'0000 to 3200'0000 +# +# Linux-Kernel is expected to be at 3000'0000, entry 3000'0000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 31F0'0000 +# +# download areas is 3100'0000 +# + + +TEXT_BASE = 0x31F00000 diff --git a/board/smdk2410/env.c b/board/smdk2410/env.c new file mode 100644 index 0000000..f839739 --- /dev/null +++ b/board/smdk2410/env.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "armboot.h" + +static int check_crc(bd_t *bd) +{ + /* need to calculate crc? */ + if (bd->bi_ext.env_crc_valid == 0) + { + env_t *env = (env_t *)CFG_ENV_ADDR; + + if (crc32(0, env->data, sizeof(env->data)) == env->crc) + bd->bi_ext.env_crc_valid = 1; + else + bd->bi_ext.env_crc_valid = -1; + } + return bd->bi_ext.env_crc_valid > 0; +} + + +/* + * save environment buffer back to flash + * returns -1 on error, 0 if ok + */ +int board_env_save(bd_t *bd, env_t *env, int size) +{ + int rc; + ulong start_addr, end_addr; + +#if CFG_ENV_SIZE <= CFG_ENV_SECT_SIZE +#error Make sure that CFG_ENV_SIZE <= CFG_ENV_SECT_SIZE +#endif + + start_addr = CFG_ENV_ADDR; + end_addr = start_addr + CFG_ENV_SIZE - 1; + + rc = flash_sect_protect(0, CFG_ENV_ADDR, end_addr); + if (rc < 0) + return rc; + + rc = flash_sect_erase(start_addr, end_addr); + if (rc < 0) + { + flash_sect_protect(1, start_addr, end_addr); + flash_perror(rc); + return rc; + } + + printf("Saving Environment to Flash..."); + rc = flash_write((uchar*)env, start_addr, size); + if (rc < 0) + flash_perror(rc); + else + printf("done.\n"); + + (void)flash_sect_protect(1, start_addr, end_addr); + + return 0; +} + +/* + * copy environment to memory + * returns -1 on error, 0 if ok + */ +int board_env_copy(bd_t *bd, env_t *data, int size) +{ + env_t *env = (env_t *)CFG_ENV_ADDR; + + if (check_crc(bd)) + { + memcpy(data, env, sizeof(env_t)); + return 0; + } + + return -1; +} + +/* + * try to read env character at offset #index + * + * called before the environment is copied to ram + * returns -1 on error, 0 if ok + */ +int board_env_getchar(bd_t * bd, int index, uchar *c) +{ + env_t *env = (env_t *)CFG_ENV_ADDR; + + /* check environment crc */ + if (index < sizeof(env->data) && check_crc(bd)) + { + *c = env->data[index]; + return 0; + } + + return -1; +} + +/* + * try to read env character at offset #index + * + * called before the environment is copied to ram + * returns -1 on error, 0 if ok + */ +uchar *board_env_getaddr(bd_t * bd, int index) +{ + env_t *env = (env_t *)CFG_ENV_ADDR; + + /* check environment crc */ + if (index < sizeof(env->data) && check_crc(bd)) + return &env->data[index]; + + return 0; +} diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c new file mode 100644 index 0000000..3074301 --- /dev/null +++ b/board/smdk2410/flash.c @@ -0,0 +1,440 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "armboot.h" + +ulong myflush(void); + + +#define FLASH_BANK_SIZE PHYS_FLASH_SIZE +#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x000000F0 +#define CMD_UNLOCK1 0x000000AA +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000A0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(bd_t *bd) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + ulong flashbase = 0; + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV400B & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic("configured to many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) + { + + if (j <= 3) + { + /* 1st one is 16 KB */ + if (j == 0) + { + flash_info[i].start[j] = flashbase + 0; + } + + /* 2nd and 3rd are both 8 KB */ + if ((j == 1) || (j == 2)) + { + flash_info[i].start[j] = flashbase + 0x4000 + (j-1)*0x2000; + } + + /* 4th 32 KB */ + if (j == 3) + { + flash_info[i].start[j] = flashbase + 0x8000; + } + } + else + { + flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _armboot_end - _armboot_start, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) + { + case (AMD_ID_LV400B & FLASH_TYPEMASK): + printf("1x Amd29LV400BB (4Mbit)\n"); + break; + case (AMD_ID_LV800B & FLASH_TYPEMASK): + printf("1x Amd29LV800BB (8Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto Done; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) + { + if ((i % 5) == 0) + { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + ushort result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) + { + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + if (info->protect[sect] == 0) + { /* not protected */ + vushort *addr = (vushort *)(info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip = 0; + + do + { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip = TMO; + break; + } + + if (!chip && (result & 0xFFFF) & BIT_ERASE_DONE) + chip = READY; + + if (!chip && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip = ERR; + + } while (!chip); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip == ERR) + { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip == TMO) + { + rc = ERR_TIMOUT; + goto outahere; + } + + printf("ok.\n"); + } + else /* it was protected */ + { + printf("protected!\n"); + } + } + + if (ctrlc()) + printf("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_hword (flash_info_t *info, ulong dest, ushort data) +{ + vushort *addr = (vushort *)dest; + ushort result; + int rc = ERR_OK; + int cflag, iflag; + int chip; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait until flash is ready */ + chip = 0; + do + { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + { + chip = ERR | TMO; + break; + } + if (!chip && ((result & 0x80) == (data & 0x80))) + chip = READY; + + if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) + { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip = READY; + else + chip = ERR; + } + + } while (!chip); + + *addr = CMD_READ_ARRAY; + + if (chip == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 8); + } + for (; i<2 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt==0 && i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); + } + + if ((rc = write_hword(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vushort*)src); + if ((rc = write_hword(info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); + } + + return write_hword(info, wp, data); +} diff --git a/board/smdk2410/memsetup.S b/board/smdk2410/memsetup.S new file mode 100644 index 0000000..c6ed06f --- /dev/null +++ b/board/smdk2410/memsetup.S @@ -0,0 +1,168 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + + +#include "config.h" +#include "version.h" + + +/* some parameters for the board */ + +/* + * + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE + * + */ + +#define BWSCON 0x48000000 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* BANK0CON */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* BANK1CON */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x0 /* 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 /* 0clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x0 /* 0clk */ +#define B3_Tacp 0x3 /* 6clk */ +#define B3_PMC 0x0 /* normal */ + +#define B4_Tacs 0x0 /* 0clk */ +#define B4_Tcos 0x0 /* 0clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x0 /* 0clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x0 /* 0clk */ +#define B5_Tacc 0x7 /* 14clk */ +#define B5_Tcoh 0x0 /* 0clk */ +#define B5_Tah 0x0 /* 0clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 +#define B6_SCAN 0x1 /* 9bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl memsetup +memsetup: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + .word 0x30 + .word 0x30 diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c new file mode 100644 index 0000000..acffc8a --- /dev/null +++ b/board/smdk2410/smdk2410.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "armboot.h" +#include "s3c2410.h" + +/* ------------------------------------------------------------------------- */ + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ + #define M_MDIV 0xC3 + #define M_PDIV 0x4 + #define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ + #define M_MDIV 0xA1 + #define M_PDIV 0x3 + #define M_SDIV 0x1 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 + #define U_M_MDIV 0xA1 + #define U_M_PDIV 0x3 + #define U_M_SDIV 0x1 +#elif USB_CLOCK==1 + #define U_M_MDIV 0x48 + #define U_M_PDIV 0x3 + #define U_M_SDIV 0x2 +#endif + +static inline +void delay(unsigned long loops) +{ + __asm__ volatile ( + "1:\n" + "subs %0, %1, #1\n" + "bne 1b" + : "=r" (loops) : "0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(bd_t *bd) +{ + /* to reduce PLL lock time, adjust the LOCKTIME register */ + rLOCKTIME = 0xFFFFFF; + + /* configure MPLL */ + rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + delay(4000); + + /* configure UPLL */ + rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + + /* some delay between MPLL and UPLL */ + delay(8000); + + /* set up the I/O ports */ + rGPACON = 0x007FFFFF; + rGPBCON = 0x00044555; + rGPBUP = 0x000007FF; + rGPCCON = 0xAAAAAAAA; + rGPCUP = 0x0000FFFF; + rGPDCON = 0xAAAAAAAA; + rGPDUP = 0x0000FFFF; + rGPECON = 0xAAAAAAAA; + rGPEUP = 0x0000FFFF; + rGPFCON = 0x000055AA; + rGPFUP = 0x000000FF; + rGPGCON = 0xFF95FFBA; + rGPGUP = 0x0000FFFF; + rGPHCON = 0x002AFAAA; + rGPHUP = 0x000007FF; + + /* arch number of SMDK2410-Board */ + bd->bi_arch_number = 193; + + /* adress of boot parameters */ + bd->bi_boot_params = 0x30000100; + + return 1; +} + +int dram_init(bd_t *bd) +{ + bd->bi_dram[0].start = PHYS_SDRAM_1; + bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return PHYS_SDRAM_1_SIZE; +} + diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 9a38739..6eeadc1 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -45,14 +45,18 @@ static unsigned long read_p15_c1(void) : "=r" (value) : : "memory"); +#ifdef MMU_DEBUG printf("p15/c1 is = %08lx\n", value); +#endif return value; } /* write to co-processor 15, register #1 (control register) */ static void write_p15_c1(unsigned long value) { +#ifdef MMU_DEBUG printf("write %08lx to p15/c1\n", value); +#endif __asm__ __volatile__( "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" : @@ -94,22 +98,6 @@ void cpu_init(bd_t *bd) #else _armboot_real_end = _armboot_end + CONFIG_STACKSIZE; #endif - /* change the clock to be 50 MHz 1:1:1 */ - rMPLLCON = 0x5c042; - rCLKDIVN = 0; - /* set up the I/O ports */ - rPACON = 0x3ffff; - rPBCON=0xaaaaaaaa; - rPBUP=0xffff; - rPECON=0x0; - rPEUP=0x0; - //INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] - // 00, 00, 00, 00, 10, 00, 10 - rPFCON=0x22; - rPFUP=0x5; - rPGCON=0x0; - rPGUP=0x0; - rOPENCR=0x0; } void cleanup_before_linux(bd_t *bd) diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index 2267186..ff36652 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -31,6 +31,12 @@ #include "armboot.h" #include "arm920t.h" +#if defined(CONFIG_S3C2400) +#include "s3c2400.h" +#elif defined(CONFIG_S3C2410) +#include "s3c2410.h" +#endif + #include "ptregs.h" extern void reset_cpu(ulong addr); diff --git a/cpu/arm920t/serial.c b/cpu/arm920t/serial.c index fb8dc66..fcff3a3 100644 --- a/cpu/arm920t/serial.c +++ b/cpu/arm920t/serial.c @@ -20,6 +20,11 @@ #include "armboot.h" #include "arm920t.h" +#if defined(CONFIG_S3C2400) +#include "s3c2400.h" +#elif defined(CONFIG_S3C2410) +#include "s3c2410.h" +#endif unsigned int br[] = {1562, 780, 390, 194, 32, 15}; void serial_setbrg(bd_t *bd, int baudrate) @@ -27,6 +32,7 @@ void serial_setbrg(bd_t *bd, int baudrate) int i; unsigned int reg = 0; +#if defined(CONFIG_SMDK2400) /* this assumes a PCLK of 50 MHz */ /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ if (baudrate == 1200) reg = 2603; @@ -36,30 +42,45 @@ void serial_setbrg(bd_t *bd, int baudrate) else if (baudrate == 57600) reg = 53; else if (baudrate == 115200) reg = 26; else hang(); +#elif defined(CONFIG_SMDK2410) + /* this assumes a PCLK of 50.7 MHz */ + /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ + if (baudrate == 1200) reg = 2639; + else if (baudrate == 9600) reg = 329; + else if (baudrate == 19200) reg = 164; + else if (baudrate == 38400) reg = 82; + else if (baudrate == 57600) reg = 54; + else if (baudrate == 115200) reg = 27; + else hang(); +#else +# error Bord config missing +#endif #ifdef CONFIG_SERIAL1 - rUFCON0=0x0; - rUMCON0=0x0; + /* FIFO enable, Tx/Rx FIFO clear */ + rUFCON0 = 0x06; + rUMCON0 = 0x0; /* Normal,No parity,1 stop,8 bit */ - rULCON0=0x3; + rULCON0 = 0x3; /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - rUCON0=0x245; + rUCON0 = 0x245; rUBRDIV0 = reg; for(i=0;i<100;i++); #elif CONFIG_SERIAL2 - rUFCON1=0x0; - rUMCON1=0x0; + /* FIFO enable, Tx/Rx FIFO clear */ + rUFCON1 = 0x06; + rUMCON1 = 0x0; /* Normal,No parity,1 stop,8 bit */ - rULCON1=0x3; + rULCON1 = 0x3; /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - rUCON1=0x245; + rUCON1 = 0x245; rUBRDIV1 = reg; for(i=0;i<100;i++); diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index f0b306b..3a07ef6 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -125,11 +125,20 @@ reset: msr cpsr,r0 /* turn off the watchdog */ -#define pWTCON 0x15300000 +#if defined(CONFIG_S3C2400) +#define pWTCON 0x15300000 /* Interupt-Controller base addresses */ -#define INTMR 0x14400008 +#define INTMSK 0x14400008 /* clock divisor register */ -#define CLKDIVN 0x14800014 +#define CLKDIVN 0x14800014 +#elif defined(CONFIG_S3C2410) +#define pWTCON 0x53000000 +/* Interupt-Controller base addresses */ +#define INTMSK 0x4A000008 +#define INTSUBMSK 0x4A00001C +/* clock divisor register */ +#define CLKDIVN 0x4C000014 +#endif ldr r0, =pWTCON mov r1, #0x0 @@ -139,8 +148,13 @@ reset: * mask all IRQs by setting all bits in the INTMR - default */ mov r1, #0xffffffff - ldr r0, =INTMR + ldr r0, =INTMSK + str r1, [r0] +#if defined(CONFIG_S3C2410) + ldr r1, =0x3ff + ldr r0, =INTSUBMSK str r1, [r0] +#endif /* FCLK:HCLK:PCLK = 1:2:4 */ /* default FCLK is 120 MHz ! */ diff --git a/include/arm920t.h b/include/arm920t.h index ebf1749..4592665 100644 --- a/include/arm920t.h +++ b/include/arm920t.h @@ -2,429 +2,12 @@ * NAME : arm920t.h * Version : 30 April 2002 * * - * Based on 24x.h for the Samsung Development Board + * empty for now ************************************************/ #ifndef __ARM920T_H__ #define __ARM920T_H__ -/* Memory control */ -#define rBWSCON (*(volatile unsigned *)0x14000000) -#define rBANKCON0 (*(volatile unsigned *)0x14000004) -#define rBANKCON1 (*(volatile unsigned *)0x14000008) -#define rBANKCON2 (*(volatile unsigned *)0x1400000c) -#define rBANKCON3 (*(volatile unsigned *)0x14000010) -#define rBANKCON4 (*(volatile unsigned *)0x14000014) -#define rBANKCON5 (*(volatile unsigned *)0x14000018) -#define rBANKCON6 (*(volatile unsigned *)0x1400001c) -#define rBANKCON7 (*(volatile unsigned *)0x14000020) -#define rREFRESH (*(volatile unsigned *)0x14000024) -#define rBANKSIZE (*(volatile unsigned *)0x14000028) -#define rMRSRB6 (*(volatile unsigned *)0x1400002c) -#define rMRSRB7 (*(volatile unsigned *)0x14000030) - -/* INTERRUPT */ -#define rSRCPND (*(volatile unsigned *)0x14400000) -#define rINTMOD (*(volatile unsigned *)0x14400004) -#define rINTMSK (*(volatile unsigned *)0x14400008) -#define rPRIORITY (*(volatile unsigned *)0x1440000c) -#define rINTPND (*(volatile unsigned *)0x14400010) -#define rINTOFFSET (*(volatile unsigned *)0x14400014) - - -/* DMA */ -#define rDISRC0 (*(volatile unsigned *)0x14600000) -#define rDIDST0 (*(volatile unsigned *)0x14600004) -#define rDCON0 (*(volatile unsigned *)0x14600008) -#define rDSTAT0 (*(volatile unsigned *)0x1460000c) -#define rDCSRC0 (*(volatile unsigned *)0x14600010) -#define rDCDST0 (*(volatile unsigned *)0x14600014) -#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018) -#define rDISRC1 (*(volatile unsigned *)0x14600020) -#define rDIDST1 (*(volatile unsigned *)0x14600024) -#define rDCON1 (*(volatile unsigned *)0x14600028) -#define rDSTAT1 (*(volatile unsigned *)0x1460002c) -#define rDCSRC1 (*(volatile unsigned *)0x14600030) -#define rDCDST1 (*(volatile unsigned *)0x14600034) -#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038) -#define rDISRC2 (*(volatile unsigned *)0x14600040) -#define rDIDST2 (*(volatile unsigned *)0x14600044) -#define rDCON2 (*(volatile unsigned *)0x14600048) -#define rDSTAT2 (*(volatile unsigned *)0x1460004c) -#define rDCSRC2 (*(volatile unsigned *)0x14600050) -#define rDCDST2 (*(volatile unsigned *)0x14600054) -#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058) -#define rDISRC3 (*(volatile unsigned *)0x14600060) -#define rDIDST3 (*(volatile unsigned *)0x14600064) -#define rDCON3 (*(volatile unsigned *)0x14600068) -#define rDSTAT3 (*(volatile unsigned *)0x1460006c) -#define rDCSRC3 (*(volatile unsigned *)0x14600070) -#define rDCDST3 (*(volatile unsigned *)0x14600074) -#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078) - - -/* CLOCK & POWER MANAGEMENT */ -#define rLOCKTIME (*(volatile unsigned *)0x14800000) -#define rMPLLCON (*(volatile unsigned *)0x14800004) -#define rUPLLCON (*(volatile unsigned *)0x14800008) -#define rCLKCON (*(volatile unsigned *)0x1480000c) -#define rCLKSLOW (*(volatile unsigned *)0x14800010) -#define rCLKDIVN (*(volatile unsigned *)0x14800014) - - -/* LCD CONTROLLER */ -#define rLCDCON1 (*(volatile unsigned *)0x14a00000) -#define rLCDCON2 (*(volatile unsigned *)0x14a00004) -#define rLCDCON3 (*(volatile unsigned *)0x14a00008) -#define rLCDCON4 (*(volatile unsigned *)0x14a0000c) -#define rLCDCON5 (*(volatile unsigned *)0x14a00010) -#define rLCDSADDR1 (*(volatile unsigned *)0x14a00014) -#define rLCDSADDR2 (*(volatile unsigned *)0x14a00018) -#define rLCDSADDR3 (*(volatile unsigned *)0x14a0001c) -#define rREDLUT (*(volatile unsigned *)0x14a00020) -#define rGREENLUT (*(volatile unsigned *)0x14a00024) -#define rBLUELUT (*(volatile unsigned *)0x14a00028) -#define rDP1_2 (*(volatile unsigned *)0x14a0002c) -#define rDP4_7 (*(volatile unsigned *)0x14a00030) -#define rDP3_5 (*(volatile unsigned *)0x14a00034) -#define rDP2_3 (*(volatile unsigned *)0x14a00038) -#define rDP5_7 (*(volatile unsigned *)0x14a0003c) -#define rDP3_4 (*(volatile unsigned *)0x14a00040) -#define rDP4_5 (*(volatile unsigned *)0x14a00044) -#define rDP6_7 (*(volatile unsigned *)0x14a00048) -#define rDITHMODE (*(volatile unsigned *)0x14a0004c) -#define rTPAL (*(volatile unsigned *)0x14a00050) -#define PALETTE (0x14a00400)//SJS - - -/* UART */ -#define rULCON0 (*(volatile unsigned char *)0x15000000) -#define rUCON0 (*(volatile unsigned short *)0x15000004) -#define rUFCON0 (*(volatile unsigned char *)0x15000008) -#define rUMCON0 (*(volatile unsigned char *)0x1500000c) -#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010) -#define rUERSTAT0 (*(volatile unsigned char *)0x15000014) -#define rUFSTAT0 (*(volatile unsigned short *)0x15000018) -#define rUMSTAT0 (*(volatile unsigned char *)0x1500001c) -#define rUBRDIV0 (*(volatile unsigned short *)0x15000028) - -#define rULCON1 (*(volatile unsigned char *)0x15004000) -#define rUCON1 (*(volatile unsigned short *)0x15004004) -#define rUFCON1 (*(volatile unsigned char *)0x15004008) -#define rUMCON1 (*(volatile unsigned char *)0x1500400c) -#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010) -#define rUERSTAT1 (*(volatile unsigned char *)0x15004014) -#define rUFSTAT1 (*(volatile unsigned short *)0x15004018) -#define rUMSTAT1 (*(volatile unsigned char *)0x1500401c) -#define rUBRDIV1 (*(volatile unsigned short *)0x15004028) - -#ifdef __BIG_ENDIAN -#define rUTXH0 (*(volatile unsigned char *)0x15000023) -#define rURXH0 (*(volatile unsigned char *)0x15000027) -#define rUTXH1 (*(volatile unsigned char *)0x15004023) -#define rURXH1 (*(volatile unsigned char *)0x15004027) - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x15000027) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x15004027) - -#define UTXH0 (0x15000020+3) //byte_access address by DMA -#define URXH0 (0x15000024+3) -#define UTXH1 (0x15004020+3) -#define URXH1 (0x15004024+3) - -#else //Little Endian -#define rUTXH0 (*(volatile unsigned char *)0x15000020) -#define rURXH0 (*(volatile unsigned char *)0x15000024) -#define rUTXH1 (*(volatile unsigned char *)0x15004020) -#define rURXH1 (*(volatile unsigned char *)0x15004024) - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x15000024) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x15004024) - -#define UTXH0 (0x15000020) //byte_access address by DMA -#define URXH0 (0x15000024) -#define UTXH1 (0x15004020) -#define URXH1 (0x15004024) -#endif - - -/* PWM TIMER */ -#define rTCFG0 (*(volatile unsigned *)0x15100000) -#define rTCFG1 (*(volatile unsigned *)0x15100004) -#define rTCON (*(volatile unsigned *)0x15100008) -#define rTCNTB0 (*(volatile unsigned *)0x1510000c) -#define rTCMPB0 (*(volatile unsigned *)0x15100010) -#define rTCNTO0 (*(volatile unsigned *)0x15100014) -#define rTCNTB1 (*(volatile unsigned *)0x15100018) -#define rTCMPB1 (*(volatile unsigned *)0x1510001c) -#define rTCNTO1 (*(volatile unsigned *)0x15100020) -#define rTCNTB2 (*(volatile unsigned *)0x15100024) -#define rTCMPB2 (*(volatile unsigned *)0x15100028) -#define rTCNTO2 (*(volatile unsigned *)0x1510002c) -#define rTCNTB3 (*(volatile unsigned *)0x15100030) -#define rTCMPB3 (*(volatile unsigned *)0x15100034) -#define rTCNTO3 (*(volatile unsigned *)0x15100038) -#define rTCNTB4 (*(volatile unsigned *)0x1510003c) -#define rTCNTO4 (*(volatile unsigned *)0x15100040) - - -/* USB DEVICE */ -#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140) -#define rPWR_REG (*(volatile unsigned *)0x15200144) -#define rINT_REG (*(volatile unsigned *)0x15200148) -#define rINT_MASK_REG (*(volatile unsigned *)0x1520014c) -#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150) -#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154) -#define rEP0_CSR (*(volatile unsigned *)0x15200160) -#define rEP0_MAXP (*(volatile unsigned *)0x15200164) -#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168) -#define rEP0_FIFO (*(volatile unsigned *)0x1520016c) -#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180) -#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184) -#define rEP1_FIFO (*(volatile unsigned *)0x15200188) -#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190) -#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194) -#define rEP2_FIFO (*(volatile unsigned *)0x15200198) -#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001a0) -#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001a4) -#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001a8) -#define rEP3_FIFO (*(volatile unsigned *)0x152001ac) -#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001b0) -#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001b4) -#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001b8) -#define rEP4_FIFO (*(volatile unsigned *)0x152001bc) -#define rDMA_CON (*(volatile unsigned *)0x152001c0) -#define rDMA_UNIT (*(volatile unsigned *)0x152001c4) -#define rDMA_FIFO (*(volatile unsigned *)0x152001c8) -#define rDMA_TX (*(volatile unsigned *)0x152001cc) -#define rTEST_MODE (*(volatile unsigned *)0x152001f4) -#define rIN_CON_REG (*(volatile unsigned *)0x152001f8) - - -/* WATCH DOG TIMER */ -#define rWTCON (*(volatile unsigned *)0x15300000) -#define rWTDAT (*(volatile unsigned *)0x15300004) -#define rWTCNT (*(volatile unsigned *)0x15300008) - - -/* IIC */ -#define rIICCON (*(volatile unsigned *)0x15400000) -#define rIICSTAT (*(volatile unsigned *)0x15400004) -#define rIICADD (*(volatile unsigned *)0x15400008) -#define rIICDS (*(volatile unsigned *)0x1540000c) - - -/* IIS */ -#define rIISCON (*(volatile unsigned *)0x15508000) -#define rIISMOD (*(volatile unsigned *)0x15508004) -#define rIISPSR (*(volatile unsigned *)0x15508008) -#define rIISFIFCON (*(volatile unsigned *)0x1550800c) - -#ifdef __BIG_ENDIAN -#define IISFIF ((volatile unsigned short *)0x15508012) - -#else //Little Endian -#define IISFIF ((volatile unsigned short *)0x15508010) -#endif - - -/* I/O PORT */ -#define rPACON (*(volatile unsigned *)0x15600000) -#define rPADAT (*(volatile unsigned *)0x15600004) - -#define rPBCON (*(volatile unsigned *)0x15600008) -#define rPBDAT (*(volatile unsigned *)0x1560000c) -#define rPBUP (*(volatile unsigned *)0x15600010) - -#define rPCCON (*(volatile unsigned *)0x15600014) -#define rPCDAT (*(volatile unsigned *)0x15600018) -#define rPCUP (*(volatile unsigned *)0x1560001c) - -#define rPDCON (*(volatile unsigned *)0x15600020) -#define rPDDAT (*(volatile unsigned *)0x15600024) -#define rPDUP (*(volatile unsigned *)0x15600028) - -#define rPECON (*(volatile unsigned *)0x1560002c) -#define rPEDAT (*(volatile unsigned *)0x15600030) -#define rPEUP (*(volatile unsigned *)0x15600034) - -#define rPFCON (*(volatile unsigned *)0x15600038) -#define rPFDAT (*(volatile unsigned *)0x1560003c) -#define rPFUP (*(volatile unsigned *)0x15600040) - -#define rPGCON (*(volatile unsigned *)0x15600044) -#define rPGDAT (*(volatile unsigned *)0x15600048) -#define rPGUP (*(volatile unsigned *)0x1560004c) - -#define rOPENCR (*(volatile unsigned *)0x15600050) -#define rMISCCR (*(volatile unsigned *)0x15600054) -#define rEXTINT (*(volatile unsigned *)0x15600058) - - -/* RTC */ -#ifdef __BIG_ENDIAN -#define rRTCCON (*(volatile unsigned char *)0x15700043) -#define rRTCALM (*(volatile unsigned char *)0x15700053) -#define rALMSEC (*(volatile unsigned char *)0x15700057) -#define rALMMIN (*(volatile unsigned char *)0x1570005b) -#define rALMHOUR (*(volatile unsigned char *)0x1570005f) -#define rALMDAY (*(volatile unsigned char *)0x15700063) -#define rALMMON (*(volatile unsigned char *)0x15700067) -#define rALMYEAR (*(volatile unsigned char *)0x1570006b) -#define rRTCRST (*(volatile unsigned char *)0x1570006f) -#define rBCDSEC (*(volatile unsigned char *)0x15700073) -#define rBCDMIN (*(volatile unsigned char *)0x15700077) -#define rBCDHOUR (*(volatile unsigned char *)0x1570007b) -#define rBCDDAY (*(volatile unsigned char *)0x1570007f) -#define rBCDDATE (*(volatile unsigned char *)0x15700083) -#define rBCDMON (*(volatile unsigned char *)0x15700087) -#define rBCDYEAR (*(volatile unsigned char *)0x1570008b) -#define rTICINT (*(volatile unsigned char *)0x15700047) - -#else //Little Endian -#define rRTCCON (*(volatile unsigned char *)0x15700040) -#define rRTCALM (*(volatile unsigned char *)0x15700050) -#define rALMSEC (*(volatile unsigned char *)0x15700054) -#define rALMMIN (*(volatile unsigned char *)0x15700058) -#define rALMHOUR (*(volatile unsigned char *)0x1570005c) -#define rALMDAY (*(volatile unsigned char *)0x15700060) -#define rALMMON (*(volatile unsigned char *)0x15700064) -#define rALMYEAR (*(volatile unsigned char *)0x15700068) -#define rRTCRST (*(volatile unsigned char *)0x1570006c) -#define rBCDSEC (*(volatile unsigned char *)0x15700070) -#define rBCDMIN (*(volatile unsigned char *)0x15700074) -#define rBCDHOUR (*(volatile unsigned char *)0x15700078) -#define rBCDDAY (*(volatile unsigned char *)0x1570007c) -#define rBCDDATE (*(volatile unsigned char *)0x15700080) -#define rBCDMON (*(volatile unsigned char *)0x15700084) -#define rBCDYEAR (*(volatile unsigned char *)0x15700088) -#define rTICINT (*(volatile unsigned char *)0x15700044) -#endif - - -/* ADC */ -#define rADCCON (*(volatile unsigned *)0x15800000) -#define rADCDAT (*(volatile unsigned *)0x15800004) - - -/* SPI */ -#define rSPCON (*(volatile unsigned *)0x15900000) -#define rSPSTA (*(volatile unsigned *)0x15900004) -#define rSPPIN (*(volatile unsigned *)0x15900008) -#define rSPPRE (*(volatile unsigned *)0x1590000c) -#define rSPTDAT (*(volatile unsigned *)0x15900010) -#define rSPRDAT (*(volatile unsigned *)0x15900014) - - -/* MMC INTERFACE */ -#define rMMCON (*(volatile unsigned *)0x15a00000) -#define rMMCRR (*(volatile unsigned *)0x15a00004) -#define rMMFCON (*(volatile unsigned *)0x15a00008) -#define rMMSTA (*(volatile unsigned *)0x15a0000c) -#define rMMFSTA (*(volatile unsigned *)0x15a00010) -#define rMMPRE (*(volatile unsigned *)0x15a00014) -#define rMMLEN (*(volatile unsigned *)0x15a00018) -#define rMMCR7 (*(volatile unsigned *)0x15a0001c) -#define rMMRSP0 (*(volatile unsigned *)0x15a00020) -#define rMMRSP1 (*(volatile unsigned *)0x15a00024) -#define rMMRSP2 (*(volatile unsigned *)0x15a00028) -#define rMMRSP3 (*(volatile unsigned *)0x15a0002c) -#define rMMCMD0 (*(volatile unsigned *)0x15a00030) -#define rMMCMD1 (*(volatile unsigned *)0x15a00034) -#define rMMCR16 (*(volatile unsigned *)0x15a00038) -#define rMMDAT (*(volatile unsigned *)0x15a0003c) - - - -/* ISR */ -#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) -#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) -#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) -#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc)) -#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) -#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) -#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) -#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c)) - -#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) -#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) -#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) -#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c)) -#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) -#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) -#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38)) -#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3c)) -#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) -#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) -#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) -#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c)) -#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) -#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) -#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) -#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5c)) -#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) -#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) -#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) -#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c)) -#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) -#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74)) -#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78)) -#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7c)) -#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80)) -#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) -#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) -#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c)) -#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) -#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) -#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) -#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xa0)) - - -/* PENDING BIT */ -#define BIT_EINT0 (0x1) -#define BIT_EINT1 (0x1<<1) -#define BIT_EINT2 (0x1<<2) -#define BIT_EINT3 (0x1<<3) -#define BIT_EINT4 (0x1<<4) -#define BIT_EINT5 (0x1<<5) -#define BIT_EINT6 (0x1<<6) -#define BIT_EINT7 (0x1<<7) -#define BIT_TICK (0x1<<8) -#define BIT_WDT (0x1<<9) -#define BIT_TIMER0 (0x1<<10) -#define BIT_TIMER1 (0x1<<11) -#define BIT_TIMER2 (0x1<<12) -#define BIT_TIMER3 (0x1<<13) -#define BIT_TIMER4 (0x1<<14) -#define BIT_UERR01 (0x1<<15) -#define BIT_NOTUSED (0x1<<16) -#define BIT_DMA0 (0x1<<17) -#define BIT_DMA1 (0x1<<18) -#define BIT_DMA2 (0x1<<19) -#define BIT_DMA3 (0x1<<20) -#define BIT_MMC (0x1<<21) -#define BIT_SPI (0x1<<22) -#define BIT_URXD0 (0x1<<23) -#define BIT_URXD1 (0x1<<24) -#define BIT_USBD (0x1<<25) -#define BIT_USBH (0x1<<26) -#define BIT_IIC (0x1<<27) -#define BIT_UTXD0 (0x1<<28) -#define BIT_UTXD1 (0x1<<29) -#define BIT_RTC (0x1<<30) -#define BIT_ADC (0x1<<31) -#define BIT_ALLMSK (0xffffffff) - -#define ClearPending(bit) {\ - rSRCPND = bit;\ - rINTPND = bit;\ - rINTPND;\ - } -//Wait until rINTPND is changed for the case that the ISR is very short. #endif /*__ARM920T_H__*/ diff --git a/include/configs/config_samsung.h b/include/configs/config_samsung.h index 1085983..addd011 100644 --- a/include/configs/config_samsung.h +++ b/include/configs/config_samsung.h @@ -38,8 +38,9 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ -#define CONFIG_SAMSUNG 1 /* on an SAMSUNG Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core */ +#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ +#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ diff --git a/include/configs/config_smdk2410.h b/include/configs/config_smdk2410.h new file mode 100644 index 0000000..61c75dd --- /dev/null +++ b/include/configs/config_smdk2410.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Gary Jennejohn + * David Mueller + * + * Configuation settings for the SAMSUNG SMDK2410 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ +#define CONFIG_SMDK2410 1 /* on an SAMSUNG SMDK2410 Board */ + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x19000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#ifndef USE_920T_MMU +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +//#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" +//#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1 +//#define CONFIG_BOOTFILE "elinos-lart" +//#define CONFIG_BOOTCOMMAND "tftp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x31F00000 /* 31 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x31000000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CFG_HZ 1562500 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext +{ + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00100000 /* 1 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/s3c2400.h b/include/s3c2400.h new file mode 100644 index 0000000..08eb3bc --- /dev/null +++ b/include/s3c2400.h @@ -0,0 +1,429 @@ +/************************************************ + * NAME : s3c2400.h + * Version : 3.7.2002 + * + * Based on 24x.h for the Samsung Development Board + ************************************************/ + +#ifndef __S3C2400_H__ +#define __S3C2400_H__ + +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x14000000) +#define rBANKCON0 (*(volatile unsigned *)0x14000004) +#define rBANKCON1 (*(volatile unsigned *)0x14000008) +#define rBANKCON2 (*(volatile unsigned *)0x1400000C) +#define rBANKCON3 (*(volatile unsigned *)0x14000010) +#define rBANKCON4 (*(volatile unsigned *)0x14000014) +#define rBANKCON5 (*(volatile unsigned *)0x14000018) +#define rBANKCON6 (*(volatile unsigned *)0x1400001C) +#define rBANKCON7 (*(volatile unsigned *)0x14000020) +#define rREFRESH (*(volatile unsigned *)0x14000024) +#define rBANKSIZE (*(volatile unsigned *)0x14000028) +#define rMRSRB6 (*(volatile unsigned *)0x1400002C) +#define rMRSRB7 (*(volatile unsigned *)0x14000030) + + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x14400000) +#define rINTMOD (*(volatile unsigned *)0x14400004) +#define rINTMSK (*(volatile unsigned *)0x14400008) +#define rPRIORITY (*(volatile unsigned *)0x1440000C) +#define rINTPND (*(volatile unsigned *)0x14400010) +#define rINTOFFSET (*(volatile unsigned *)0x14400014) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x14600000) +#define rDIDST0 (*(volatile unsigned *)0x14600004) +#define rDCON0 (*(volatile unsigned *)0x14600008) +#define rDSTAT0 (*(volatile unsigned *)0x1460000C) +#define rDCSRC0 (*(volatile unsigned *)0x14600010) +#define rDCDST0 (*(volatile unsigned *)0x14600014) +#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018) +#define rDISRC1 (*(volatile unsigned *)0x14600020) +#define rDIDST1 (*(volatile unsigned *)0x14600024) +#define rDCON1 (*(volatile unsigned *)0x14600028) +#define rDSTAT1 (*(volatile unsigned *)0x1460002C) +#define rDCSRC1 (*(volatile unsigned *)0x14600030) +#define rDCDST1 (*(volatile unsigned *)0x14600034) +#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038) +#define rDISRC2 (*(volatile unsigned *)0x14600040) +#define rDIDST2 (*(volatile unsigned *)0x14600044) +#define rDCON2 (*(volatile unsigned *)0x14600048) +#define rDSTAT2 (*(volatile unsigned *)0x1460004C) +#define rDCSRC2 (*(volatile unsigned *)0x14600050) +#define rDCDST2 (*(volatile unsigned *)0x14600054) +#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058) +#define rDISRC3 (*(volatile unsigned *)0x14600060) +#define rDIDST3 (*(volatile unsigned *)0x14600064) +#define rDCON3 (*(volatile unsigned *)0x14600068) +#define rDSTAT3 (*(volatile unsigned *)0x1460006C) +#define rDCSRC3 (*(volatile unsigned *)0x14600070) +#define rDCDST3 (*(volatile unsigned *)0x14600074) +#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x14800000) +#define rMPLLCON (*(volatile unsigned *)0x14800004) +#define rUPLLCON (*(volatile unsigned *)0x14800008) +#define rCLKCON (*(volatile unsigned *)0x1480000C) +#define rCLKSLOW (*(volatile unsigned *)0x14800010) +#define rCLKDIVN (*(volatile unsigned *)0x14800014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x14A00000) +#define rLCDCON2 (*(volatile unsigned *)0x14A00004) +#define rLCDCON3 (*(volatile unsigned *)0x14A00008) +#define rLCDCON4 (*(volatile unsigned *)0x14A0000C) +#define rLCDCON5 (*(volatile unsigned *)0x14A00010) +#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014) +#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018) +#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C) +#define rREDLUT (*(volatile unsigned *)0x14A00020) +#define rGREENLUT (*(volatile unsigned *)0x14A00024) +#define rBLUELUT (*(volatile unsigned *)0x14A00028) +#define rDP1_2 (*(volatile unsigned *)0x14A0002C) +#define rDP4_7 (*(volatile unsigned *)0x14A00030) +#define rDP3_5 (*(volatile unsigned *)0x14A00034) +#define rDP2_3 (*(volatile unsigned *)0x14A00038) +#define rDP5_7 (*(volatile unsigned *)0x14A0003c) +#define rDP3_4 (*(volatile unsigned *)0x14A00040) +#define rDP4_5 (*(volatile unsigned *)0x14A00044) +#define rDP6_7 (*(volatile unsigned *)0x14A00048) +#define rDITHMODE (*(volatile unsigned *)0x14A0004C) +#define rTPAL (*(volatile unsigned *)0x14A00050) +#define PALETTE (0x14A00400) /* SJS */ + + +/* UART */ +#define rULCON0 (*(volatile unsigned char *)0x15000000) +#define rUCON0 (*(volatile unsigned short *)0x15000004) +#define rUFCON0 (*(volatile unsigned char *)0x15000008) +#define rUMCON0 (*(volatile unsigned char *)0x1500000C) +#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010) +#define rUERSTAT0 (*(volatile unsigned char *)0x15000014) +#define rUFSTAT0 (*(volatile unsigned short *)0x15000018) +#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C) +#define rUBRDIV0 (*(volatile unsigned short *)0x15000028) + +#define rULCON1 (*(volatile unsigned char *)0x15004000) +#define rUCON1 (*(volatile unsigned short *)0x15004004) +#define rUFCON1 (*(volatile unsigned char *)0x15004008) +#define rUMCON1 (*(volatile unsigned char *)0x1500400C) +#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010) +#define rUERSTAT1 (*(volatile unsigned char *)0x15004014) +#define rUFSTAT1 (*(volatile unsigned short *)0x15004018) +#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C) +#define rUBRDIV1 (*(volatile unsigned short *)0x15004028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x15000023) +#define rURXH0 (*(volatile unsigned char *)0x15000027) +#define rUTXH1 (*(volatile unsigned char *)0x15004023) +#define rURXH1 (*(volatile unsigned char *)0x15004027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004027) + +#define UTXH0 (0x15000020+3) /* byte_access address by DMA */ +#define URXH0 (0x15000024+3) +#define UTXH1 (0x15004020+3) +#define URXH1 (0x15004024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x15000020) +#define rURXH0 (*(volatile unsigned char *)0x15000024) +#define rUTXH1 (*(volatile unsigned char *)0x15004020) +#define rURXH1 (*(volatile unsigned char *)0x15004024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004024) + +#define UTXH0 (0x15000020) /* byte_access address by DMA */ +#define URXH0 (0x15000024) +#define UTXH1 (0x15004020) +#define URXH1 (0x15004024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x15100000) +#define rTCFG1 (*(volatile unsigned *)0x15100004) +#define rTCON (*(volatile unsigned *)0x15100008) +#define rTCNTB0 (*(volatile unsigned *)0x1510000C) +#define rTCMPB0 (*(volatile unsigned *)0x15100010) +#define rTCNTO0 (*(volatile unsigned *)0x15100014) +#define rTCNTB1 (*(volatile unsigned *)0x15100018) +#define rTCMPB1 (*(volatile unsigned *)0x1510001C) +#define rTCNTO1 (*(volatile unsigned *)0x15100020) +#define rTCNTB2 (*(volatile unsigned *)0x15100024) +#define rTCMPB2 (*(volatile unsigned *)0x15100028) +#define rTCNTO2 (*(volatile unsigned *)0x1510002C) +#define rTCNTB3 (*(volatile unsigned *)0x15100030) +#define rTCMPB3 (*(volatile unsigned *)0x15100034) +#define rTCNTO3 (*(volatile unsigned *)0x15100038) +#define rTCNTB4 (*(volatile unsigned *)0x1510003C) +#define rTCNTO4 (*(volatile unsigned *)0x15100040) + + +/* USB DEVICE */ +#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140) +#define rPWR_REG (*(volatile unsigned *)0x15200144) +#define rINT_REG (*(volatile unsigned *)0x15200148) +#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C) +#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150) +#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154) +#define rEP0_CSR (*(volatile unsigned *)0x15200160) +#define rEP0_MAXP (*(volatile unsigned *)0x15200164) +#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168) +#define rEP0_FIFO (*(volatile unsigned *)0x1520016C) +#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180) +#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184) +#define rEP1_FIFO (*(volatile unsigned *)0x15200188) +#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190) +#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194) +#define rEP2_FIFO (*(volatile unsigned *)0x15200198) +#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0) +#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4) +#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8) +#define rEP3_FIFO (*(volatile unsigned *)0x152001AC) +#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0) +#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4) +#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8) +#define rEP4_FIFO (*(volatile unsigned *)0x152001BC) +#define rDMA_CON (*(volatile unsigned *)0x152001C0) +#define rDMA_UNIT (*(volatile unsigned *)0x152001C4) +#define rDMA_FIFO (*(volatile unsigned *)0x152001C8) +#define rDMA_TX (*(volatile unsigned *)0x152001CC) +#define rTEST_MODE (*(volatile unsigned *)0x152001F4) +#define rIN_CON_REG (*(volatile unsigned *)0x152001F8) + + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x15300000) +#define rWTDAT (*(volatile unsigned *)0x15300004) +#define rWTCNT (*(volatile unsigned *)0x15300008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x15400000) +#define rIICSTAT (*(volatile unsigned *)0x15400004) +#define rIICADD (*(volatile unsigned *)0x15400008) +#define rIICDS (*(volatile unsigned *)0x1540000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x15508000) +#define rIISMOD (*(volatile unsigned *)0x15508004) +#define rIISPSR (*(volatile unsigned *)0x15508008) +#define rIISFIFCON (*(volatile unsigned *)0x1550800C) + +#ifdef __BIG_ENDIAN +#define IISFIF ((volatile unsigned short *)0x15508012) + +#else /* Little Endian */ +#define IISFIF ((volatile unsigned short *)0x15508010) +#endif + + +/* I/O PORT */ +#define rPACON (*(volatile unsigned *)0x15600000) +#define rPADAT (*(volatile unsigned *)0x15600004) + +#define rPBCON (*(volatile unsigned *)0x15600008) +#define rPBDAT (*(volatile unsigned *)0x1560000C) +#define rPBUP (*(volatile unsigned *)0x15600010) + +#define rPCCON (*(volatile unsigned *)0x15600014) +#define rPCDAT (*(volatile unsigned *)0x15600018) +#define rPCUP (*(volatile unsigned *)0x1560001C) + +#define rPDCON (*(volatile unsigned *)0x15600020) +#define rPDDAT (*(volatile unsigned *)0x15600024) +#define rPDUP (*(volatile unsigned *)0x15600028) + +#define rPECON (*(volatile unsigned *)0x1560002C) +#define rPEDAT (*(volatile unsigned *)0x15600030) +#define rPEUP (*(volatile unsigned *)0x15600034) + +#define rPFCON (*(volatile unsigned *)0x15600038) +#define rPFDAT (*(volatile unsigned *)0x1560003C) +#define rPFUP (*(volatile unsigned *)0x15600040) + +#define rPGCON (*(volatile unsigned *)0x15600044) +#define rPGDAT (*(volatile unsigned *)0x15600048) +#define rPGUP (*(volatile unsigned *)0x1560004C) + +#define rOPENCR (*(volatile unsigned *)0x15600050) +#define rMISCCR (*(volatile unsigned *)0x15600054) +#define rEXTINT (*(volatile unsigned *)0x15600058) + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x15700043) +#define rRTCALM (*(volatile unsigned char *)0x15700053) +#define rALMSEC (*(volatile unsigned char *)0x15700057) +#define rALMMIN (*(volatile unsigned char *)0x1570005B) +#define rALMHOUR (*(volatile unsigned char *)0x1570005F) +#define rALMDAY (*(volatile unsigned char *)0x15700063) +#define rALMMON (*(volatile unsigned char *)0x15700067) +#define rALMYEAR (*(volatile unsigned char *)0x1570006B) +#define rRTCRST (*(volatile unsigned char *)0x1570006F) +#define rBCDSEC (*(volatile unsigned char *)0x15700073) +#define rBCDMIN (*(volatile unsigned char *)0x15700077) +#define rBCDHOUR (*(volatile unsigned char *)0x1570007B) +#define rBCDDAY (*(volatile unsigned char *)0x1570007F) +#define rBCDDATE (*(volatile unsigned char *)0x15700083) +#define rBCDMON (*(volatile unsigned char *)0x15700087) +#define rBCDYEAR (*(volatile unsigned char *)0x1570008B) +#define rTICINT (*(volatile unsigned char *)0x15700047) + +#else /* Little Endian */ +#define rRTCCON (*(volatile unsigned char *)0x15700040) +#define rRTCALM (*(volatile unsigned char *)0x15700050) +#define rALMSEC (*(volatile unsigned char *)0x15700054) +#define rALMMIN (*(volatile unsigned char *)0x15700058) +#define rALMHOUR (*(volatile unsigned char *)0x1570005C) +#define rALMDAY (*(volatile unsigned char *)0x15700060) +#define rALMMON (*(volatile unsigned char *)0x15700064) +#define rALMYEAR (*(volatile unsigned char *)0x15700068) +#define rRTCRST (*(volatile unsigned char *)0x1570006C) +#define rBCDSEC (*(volatile unsigned char *)0x15700070) +#define rBCDMIN (*(volatile unsigned char *)0x15700074) +#define rBCDHOUR (*(volatile unsigned char *)0x15700078) +#define rBCDDAY (*(volatile unsigned char *)0x1570007C) +#define rBCDDATE (*(volatile unsigned char *)0x15700080) +#define rBCDMON (*(volatile unsigned char *)0x15700084) +#define rBCDYEAR (*(volatile unsigned char *)0x15700088) +#define rTICINT (*(volatile unsigned char *)0x15700044) +#endif + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x15800000) +#define rADCDAT (*(volatile unsigned *)0x15800004) + + +/* SPI */ +#define rSPCON (*(volatile unsigned *)0x15900000) +#define rSPSTA (*(volatile unsigned *)0x15900004) +#define rSPPIN (*(volatile unsigned *)0x15900008) +#define rSPPRE (*(volatile unsigned *)0x1590000C) +#define rSPTDAT (*(volatile unsigned *)0x15900010) +#define rSPRDAT (*(volatile unsigned *)0x15900014) + + +/* MMC INTERFACE */ +#define rMMCON (*(volatile unsigned *)0x15a00000) +#define rMMCRR (*(volatile unsigned *)0x15a00004) +#define rMMFCON (*(volatile unsigned *)0x15a00008) +#define rMMSTA (*(volatile unsigned *)0x15a0000C) +#define rMMFSTA (*(volatile unsigned *)0x15a00010) +#define rMMPRE (*(volatile unsigned *)0x15a00014) +#define rMMLEN (*(volatile unsigned *)0x15a00018) +#define rMMCR7 (*(volatile unsigned *)0x15a0001C) +#define rMMRSP0 (*(volatile unsigned *)0x15a00020) +#define rMMRSP1 (*(volatile unsigned *)0x15a00024) +#define rMMRSP2 (*(volatile unsigned *)0x15a00028) +#define rMMRSP3 (*(volatile unsigned *)0x15a0002C) +#define rMMCMD0 (*(volatile unsigned *)0x15a00030) +#define rMMCMD1 (*(volatile unsigned *)0x15a00034) +#define rMMCR16 (*(volatile unsigned *)0x15a00038) +#define rMMDAT (*(volatile unsigned *)0x15a0003C) + + + +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38)) +#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4 (0x1<<4) +#define BIT_EINT5 (0x1<<5) +#define BIT_EINT6 (0x1<<6) +#define BIT_EINT7 (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UERR01 (0x1<<15) +#define BIT_NOTUSED (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_MMC (0x1<<21) +#define BIT_SPI (0x1<<22) +#define BIT_URXD0 (0x1<<23) +#define BIT_URXD1 (0x1<<24) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UTXD0 (0x1<<28) +#define BIT_UTXD1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__S3C2400_H__*/ diff --git a/include/s3c2410.h b/include/s3c2410.h new file mode 100644 index 0000000..18a76cc --- /dev/null +++ b/include/s3c2410.h @@ -0,0 +1,573 @@ +/************************************************ + * NAME : s3c2410.h + * Version : 3.7.2002 + * + * Based on S3C2410X User's manual Rev 0.1 + ************************************************/ + +#ifndef __S3C2410_H__ +#define __S3C2410_H__ + + +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x48000000) +#define rBANKCON0 (*(volatile unsigned *)0x48000004) +#define rBANKCON1 (*(volatile unsigned *)0x48000008) +#define rBANKCON2 (*(volatile unsigned *)0x4800000C) +#define rBANKCON3 (*(volatile unsigned *)0x48000010) +#define rBANKCON4 (*(volatile unsigned *)0x48000014) +#define rBANKCON5 (*(volatile unsigned *)0x48000018) +#define rBANKCON6 (*(volatile unsigned *)0x4800001C) +#define rBANKCON7 (*(volatile unsigned *)0x48000020) +#define rREFRESH (*(volatile unsigned *)0x48000024) +#define rBANKSIZE (*(volatile unsigned *)0x48000028) +#define rMRSRB6 (*(volatile unsigned *)0x4800002C) +#define rMRSRB7 (*(volatile unsigned *)0x48000030) + + +/* USB HOST */ +#define rHcRevision (*(volatile unsigned *)0x49000000) +#define rHcControl (*(volatile unsigned *)0x49000004) +#define rHcCommonStatus (*(volatile unsigned *)0x49000008) +#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C) +#define rHcInterruptEnable (*(volatile unsigned *)0x49000010) +#define rHcInterruptDisable (*(volatile unsigned *)0x49000014) +#define rHcHCCA (*(volatile unsigned *)0x49000018) +#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C) +#define rHcControlHeadED (*(volatile unsigned *)0x49000020) +#define rHcControlCurrentED (*(volatile unsigned *)0x49000024) +#define rHcBulkHeadED (*(volatile unsigned *)0x49000028) +#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C) +#define rHcDoneHead (*(volatile unsigned *)0x49000030) +#define rHcRmInterval (*(volatile unsigned *)0x49000034) +#define rHcFmRemaining (*(volatile unsigned *)0x49000038) +#define rHcFmNumber (*(volatile unsigned *)0x4900003C) +#define rHcPeriodicStart (*(volatile unsigned *)0x49000040) +#define rHcLSThreshold (*(volatile unsigned *)0x49000044) +#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048) +#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C) +#define rHcRhStatus (*(volatile unsigned *)0x49000050) +#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054) +#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058) + + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x4A000000) +#define rINTMOD (*(volatile unsigned *)0x4A000004) +#define rINTMSK (*(volatile unsigned *)0x4A000008) +#define rPRIORITY (*(volatile unsigned *)0x4A00000C) +#define rINTPND (*(volatile unsigned *)0x4A000010) +#define rINTOFFSET (*(volatile unsigned *)0x4A000014) +#define rSUBSRCPND (*(volatile unsigned *)0x4A000018) +#define rINTSUBMSK (*(volatile unsigned *)0x4A00001C) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x4B000000) +#define rDISRCC0 (*(volatile unsigned *)0x4B000004) +#define rDIDST0 (*(volatile unsigned *)0x4B000008) +#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C) +#define rDCON0 (*(volatile unsigned *)0x4B000010) +#define rDSTAT0 (*(volatile unsigned *)0x4B000014) +#define rDCSRC0 (*(volatile unsigned *)0x4B000018) +#define rDCDST0 (*(volatile unsigned *)0x4B00001C) +#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020) +#define rDISRC1 (*(volatile unsigned *)0x4B000040) +#define rDISRCC1 (*(volatile unsigned *)0x4B000044) +#define rDIDST1 (*(volatile unsigned *)0x4B000048) +#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C) +#define rDCON1 (*(volatile unsigned *)0x4B000050) +#define rDSTAT1 (*(volatile unsigned *)0x4B000054) +#define rDCSRC1 (*(volatile unsigned *)0x4B000058) +#define rDCDST1 (*(volatile unsigned *)0x4B00005C) +#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060) +#define rDISRC2 (*(volatile unsigned *)0x4B000080) +#define rDISRCC2 (*(volatile unsigned *)0x4B000084) +#define rDIDST2 (*(volatile unsigned *)0x4B000088) +#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C) +#define rDCON2 (*(volatile unsigned *)0x4B000090) +#define rDSTAT2 (*(volatile unsigned *)0x4B000094) +#define rDCSRC2 (*(volatile unsigned *)0x4B000098) +#define rDCDST2 (*(volatile unsigned *)0x4B00009C) +#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0) +#define rDISRC3 (*(volatile unsigned *)0x4B0000C0) +#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4) +#define rDIDST3 (*(volatile unsigned *)0x4B0000C8) +#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC) +#define rDCON3 (*(volatile unsigned *)0x4B0000D0) +#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4) +#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8) +#define rDCDST3 (*(volatile unsigned *)0x4B0000DC) +#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x4C000000) +#define rMPLLCON (*(volatile unsigned *)0x4C000004) +#define rUPLLCON (*(volatile unsigned *)0x4C000008) +#define rCLKCON (*(volatile unsigned *)0x4C00000C) +#define rCLKSLOW (*(volatile unsigned *)0x4C000010) +#define rCLKDIVN (*(volatile unsigned *)0x4C000014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x4D000000) +#define rLCDCON2 (*(volatile unsigned *)0x4D000004) +#define rLCDCON3 (*(volatile unsigned *)0x4D000008) +#define rLCDCON4 (*(volatile unsigned *)0x4D00000C) +#define rLCDCON5 (*(volatile unsigned *)0x4D000010) +#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014) +#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018) +#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C) +#define rREDLUT (*(volatile unsigned *)0x4D000020) +#define rGREENLUT (*(volatile unsigned *)0x4D000024) +#define rBLUELUT (*(volatile unsigned *)0x4D000028) +#define rDITHMODE (*(volatile unsigned *)0x4D00004C) +#define rTPAL (*(volatile unsigned *)0x4D000050) +#define rLCDINTPND (*(volatile unsigend *)0x4D000054) +#define rLCDSRCPND (*(volatile unsigend *)0x4D000058) +#define rLCDINTMSK (*(volatile unsigend *)0x4D00005C) + + +/* NAND FLASH */ +#define rNFCONF (*(volatile unsigend *)0x4E000000) +#define rNFCMD (*(volatile unsigend *)0x4E000004) +#define rNFADDR (*(volatile unsigend *)0x4E000008) +#define rNFDATA (*(volatile unsigend *)0x4E00000C) +#define rNFSTAT (*(volatile unsigend *)0x4E000010) +#define rNFECC (*(volatile unsigend *)0x4E000014) + + +/* UART */ +#define rULCON0 (*(volatile unsigned *)0x50000000) +#define rUCON0 (*(volatile unsigned *)0x50000004) +#define rUFCON0 (*(volatile unsigned *)0x50000008) +#define rUMCON0 (*(volatile unsigned *)0x5000000C) +#define rUTRSTAT0 (*(volatile unsigned *)0x50000010) +#define rUERSTAT0 (*(volatile unsigned *)0x50000014) +#define rUFSTAT0 (*(volatile unsigned *)0x50000018) +#define rUMSTAT0 (*(volatile unsigned *)0x5000001C) +#define rUBRDIV0 (*(volatile unsigned *)0x50000028) + +#define rULCON1 (*(volatile unsigned *)0x50004000) +#define rUCON1 (*(volatile unsigned *)0x50004004) +#define rUFCON1 (*(volatile unsigned *)0x50004008) +#define rUMCON1 (*(volatile unsigned *)0x5000400C) +#define rUTRSTAT1 (*(volatile unsigned *)0x50004010) +#define rUERSTAT1 (*(volatile unsigned *)0x50004014) +#define rUFSTAT1 (*(volatile unsigned *)0x50004018) +#define rUMSTAT1 (*(volatile unsigned *)0x5000401C) +#define rUBRDIV1 (*(volatile unsigned *)0x50004028) + +#define rULCON2 (*(volatile unsigned *)0x50008000) +#define rUCON2 (*(volatile unsigned *)0x50008004) +#define rUFCON2 (*(volatile unsigned *)0x50008008) +#define rUTRSTAT2 (*(volatile unsigned *)0x50008010) +#define rUERSTAT2 (*(volatile unsigned *)0x50008014) +#define rUFSTAT2 (*(volatile unsigned *)0x50008018) +#define rUBRDIV2 (*(volatile unsigned *)0x50008028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x50000023) +#define rURXH0 (*(volatile unsigned char *)0x50000027) +#define rUTXH1 (*(volatile unsigned char *)0x50004023) +#define rURXH1 (*(volatile unsigned char *)0x50004027) +#define rUTXH2 (*(volatile unsigned char *)0x50008023) +#define rURXH2 (*(volatile unsigned char *)0x50008027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004027) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008027) + +#define UTXH0 (0x50000020+3) /* byte_access address by DMA */ +#define URXH0 (0x50000024+3) +#define UTXH1 (0x50004020+3) +#define URXH1 (0x50004024+3) +#define UTXH2 (0x50008020+3) +#define URXH2 (0x50008024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x50000020) +#define rURXH0 (*(volatile unsigned char *)0x50000024) +#define rUTXH1 (*(volatile unsigned char *)0x50004020) +#define rURXH1 (*(volatile unsigned char *)0x50004024) +#define rUTXH2 (*(volatile unsigned char *)0x50008020) +#define rURXH2 (*(volatile unsigned char *)0x50008024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004024) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008024) + +#define UTXH0 (0x50000020) /* byte_access address by DMA */ +#define URXH0 (0x50000024) +#define UTXH1 (0x50004020) +#define URXH1 (0x50004024) +#define UTXH2 (0x50008020) +#define URXH2 (0x50008024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x51000000) +#define rTCFG1 (*(volatile unsigned *)0x51000004) +#define rTCON (*(volatile unsigned *)0x51000008) +#define rTCNTB0 (*(volatile unsigned *)0x5100000C) +#define rTCMPB0 (*(volatile unsigned *)0x51000010) +#define rTCNTO0 (*(volatile unsigned *)0x51000014) +#define rTCNTB1 (*(volatile unsigned *)0x51000018) +#define rTCMPB1 (*(volatile unsigned *)0x5100001C) +#define rTCNTO1 (*(volatile unsigned *)0x51000020) +#define rTCNTB2 (*(volatile unsigned *)0x51000024) +#define rTCMPB2 (*(volatile unsigned *)0x51000028) +#define rTCNTO2 (*(volatile unsigned *)0x5100002C) +#define rTCNTB3 (*(volatile unsigned *)0x51000030) +#define rTCMPB3 (*(volatile unsigned *)0x51000034) +#define rTCNTO3 (*(volatile unsigned *)0x51000038) +#define rTCNTB4 (*(volatile unsigned *)0x5100003C) +#define rTCNTO4 (*(volatile unsigned *)0x51000040) + + +/* USB DEVICE */ +#ifdef __BIG_ENDIAN +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) +#define rPWR_REG (*(volatile unsigned char *)0x52000147) +#define rEP_INT_REG (*(volatile unsigned char *)0x5200014B) +#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B) +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F) +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) +#define rINDEX_REG (*(volatile unsigned char *)0x5200017B) +#define rMAXP_REG (*(volatile unsigned char *)0x52000183) +#define rEP0_CSR (*(volatile unsigned char *)0x52000187) +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) +#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B) +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001C3) +#define rEP1_FIFO (*(volatile unsigned char *)0x520001C7) +#define rEP2_FIFO (*(volatile unsigned char *)0x520001CB) +#define rEP3_FIFO (*(volatile unsigned char *)0x520001CF) +#define rEP4_FIFO (*(volatile unsigned char *)0x520001D3) +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B) +#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F) +#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213) +#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B) +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F) +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) +#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227) +#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B) +#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B) +#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F) +#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253) +#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B) +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F) +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) +#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267) +#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B) +#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F) +#else /* little endian */ +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) +#define rPWR_REG (*(volatile unsigned char *)0x52000144) +#define rEP_INT_REG (*(volatile unsigned char *)0x52000148) +#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C) +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) +#define rINDEX_REG (*(volatile unsigned char *)0x52000178) +#define rMAXP_REG (*(volatile unsigned char *)0x52000180) +#define rEP0_CSR (*(volatile unsigned char *)0x52000184) +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) +#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001C0) +#define rEP1_FIFO (*(volatile unsigned char *)0x520001C4) +#define rEP2_FIFO (*(volatile unsigned char *)0x520001C8) +#define rEP3_FIFO (*(volatile unsigned char *)0x520001CC) +#define rEP4_FIFO (*(volatile unsigned char *)0x520001D0) +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) +#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C) +#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210) +#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C) +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) +#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224) +#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228) +#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) +#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C) +#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250) +#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C) +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) +#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264) +#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268) +#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C) +#endif /* __BIG_ENDIAN */ + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x53000000) +#define rWTDAT (*(volatile unsigned *)0x53000004) +#define rWTCNT (*(volatile unsigned *)0x53000008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x54000000) +#define rIICSTAT (*(volatile unsigned *)0x54000004) +#define rIICADD (*(volatile unsigned *)0x54000008) +#define rIICDS (*(volatile unsigned *)0x5400000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x55000000) +#define rIISMOD (*(volatile unsigned *)0x55000004) +#define rIISPSR (*(volatile unsigned *)0x55000008) +#define rIISFCON (*(volatile unsigned *)0x5500000C) + +#ifdef __BIG_ENDIAN +#define IISFIF ((volatile unsigned short *)0x55000012) +#else /* little endian */ +#define IISFIF ((volatile unsigned short *)0x55000010) +#endif + + +/* I/O PORT */ +#define rGPACON (*(volatile unsigned *)0x56000000) +#define rGPADAT (*(volatile unsigned *)0x56000004) + +#define rGPBCON (*(volatile unsigned *)0x56000010) +#define rGPBDAT (*(volatile unsigned *)0x56000014) +#define rGPBUP (*(volatile unsigned *)0x56000018) + +#define rGPCCON (*(volatile unsigned *)0x56000020) +#define rGPCDAT (*(volatile unsigned *)0x56000024) +#define rGPCUP (*(volatile unsigned *)0x56000028) + +#define rGPDCON (*(volatile unsigned *)0x56000030) +#define rGPDDAT (*(volatile unsigned *)0x56000034) +#define rGPDUP (*(volatile unsigned *)0x56000038) + +#define rGPECON (*(volatile unsigned *)0x56000040) +#define rGPEDAT (*(volatile unsigned *)0x56000044) +#define rGPEUP (*(volatile unsigned *)0x56000048) + +#define rGPFCON (*(volatile unsigned *)0x56000050) +#define rGPFDAT (*(volatile unsigned *)0x56000054) +#define rGPFUP (*(volatile unsigned *)0x56000058) + +#define rGPGCON (*(volatile unsigned *)0x56000060) +#define rGPGDAT (*(volatile unsigned *)0x56000064) +#define rGPGUP (*(volatile unsigned *)0x56000068) + +#define rGPHCON (*(volatile unsigned *)0x56000070) +#define rGPHDAT (*(volatile unsigned *)0x56000074) +#define rGPHUP (*(volatile unsigned *)0x56000078) + +#define rMISCCR (*(volatile unsigned *)0x56000080) +#define rDCLKCON (*(volatile unsigned *)0x56000084) +#define rEXTINT0 (*(volatile unsigned *)0x56000088) +#define rEXTINT1 (*(volatile unsigned *)0x5600008C) +#define rEXTINT2 (*(volatile unsigned *)0x56000090) +#define rEINTFLT0 (*(volatile unsigned *)0x56000094) +#define rEINTFLT1 (*(volatile unsigned *)0x56000098) +#define rEINTFLT2 (*(volatile unsigned *)0x5600009C) +#define rEINTFLT3 (*(volatile unsigned *)0x560000A0) +#define rEINTMASK (*(volatile unsigned *)0x560000A4) +#define rEINTPEND (*(volatile unsigned *)0x560000A8) +#define rGSTATUS0 (*(volatile unsigned *)0x560000AC) +#define rGSTATUS1 (*(volatile unsigned *)0x560000B0) + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x57000043) +#define rTICNT (*(volatile unsigned char *)0x57000047) +#define rRTCALM (*(volatile unsigned char *)0x57000053) +#define rALMSEC (*(volatile unsigned char *)0x57000057) +#define rALMMIN (*(volatile unsigned char *)0x5700005B) +#define rALMHOUR (*(volatile unsigned char *)0x5700005F) +#define rALMDATE (*(volatile unsigned char *)0x57000063) +#define rALMMON (*(volatile unsigned char *)0x57000067) +#define rALMYEAR (*(volatile unsigned char *)0x5700006B) +#define rRTCRST (*(volatile unsigned char *)0x5700006F) +#define rBCDSEC (*(volatile unsigned char *)0x57000073) +#define rBCDMIN (*(volatile unsigned char *)0x57000077) +#define rBCDHOUR (*(volatile unsigned char *)0x5700007B) +#define rBCDDATE (*(volatile unsigned char *)0x5700007F) +#define rBCDDAY (*(volatile unsigned char *)0x57000083) +#define rBCDMON (*(volatile unsigned char *)0x57000087) +#define rBCDYEAR (*(volatile unsigned char *)0x5700008B) +#else /* little endian */ +#define rRTCCON (*(volatile unsigned char *)0x57000040) +#define rTICNT (*(volatile unsigned char *)0x57000044) +#define rRTCALM (*(volatile unsigned char *)0x57000050) +#define rALMSEC (*(volatile unsigned char *)0x57000054) +#define rALMMIN (*(volatile unsigned char *)0x57000058) +#define rALMHOUR (*(volatile unsigned char *)0x5700005C) +#define rALMDATE (*(volatile unsigned char *)0x57000060) +#define rALMMON (*(volatile unsigned char *)0x57000064) +#define rALMYEAR (*(volatile unsigned char *)0x57000068) +#define rRTCRST (*(volatile unsigned char *)0x5700006C) +#define rBCDSEC (*(volatile unsigned char *)0x57000070) +#define rBCDMIN (*(volatile unsigned char *)0x57000074) +#define rBCDHOUR (*(volatile unsigned char *)0x57000078) +#define rBCDDATE (*(volatile unsigned char *)0x5700007C) +#define rBCDDAY (*(volatile unsigned char *)0x57000080) +#define rBCDMON (*(volatile unsigned char *)0x57000084) +#define rBCDYEAR (*(volatile unsigned char *)0x57000088) +#endif + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x58000000) +#define rADCTSC (*(volatile unsigned *)0x58000004) +#define rADCDLY (*(volatile unsigned *)0x58000008) +#define rADCDAT0 (*(volatile unsigned *)0x5800000C) +#define rADCDAT1 (*(volatile unsigned *)0x58000010) + + +/* SPI */ +#define rSPCON0 (*(volatile unsigned *)0x59000000) +#define rSPSTA0 (*(volatile unsigned *)0x59000004) +#define rSPPIN0 (*(volatile unsigned *)0x59000008) +#define rSPPRE0 (*(volatile unsigned *)0x5900000C) +#define rSPTDAT0 (*(volatile unsigned *)0x59000010) +#define rSPRDAT0 (*(volatile unsigned *)0x59000014) +#define rSPCON1 (*(volatile unsigned *)0x59000020) +#define rSPSTA1 (*(volatile unsigned *)0x59000024) +#define rSPPIN1 (*(volatile unsigned *)0x59000028) +#define rSPPRE1 (*(volatile unsigned *)0x5900002C) +#define rSPTDAT1 (*(volatile unsigned *)0x59000030) +#define rSPRDAT1 (*(volatile unsigned *)0x59000034) + + +/* SD INTERFACE */ +#define rSDICON (*(volatile unsigned *)0x5A000000) +#define rSDIPRE (*(volatile unsigned *)0x5A000004) +#define rSDICmdArg (*(volatile unsigned *)0x5A000008) +#define rSDICmdCon (*(volatile unsigned *)0x5A00000C) +#define rSDICmdSta (*(volatile unsigned *)0x5A000010) +#define rSDIRSP0 (*(volatile unsigned *)0x5A000014) +#define rSDIRSP1 (*(volatile unsigned *)0x5A000018) +#define rSDIRSP2 (*(volatile unsigned *)0x5A00001C) +#define rSDIRSP3 (*(volatile unsigned *)0x5A000020) +#define rSDIDTimer (*(volatile unsigned *)0x5A000024) +#define rSDIBSize (*(volatile unsigned *)0x5A000028) +#define rSDIDatCon (*(volatile unsigned *)0x5A00002C) +#define rSDIDatCnt (*(volatile unsigned *)0x5A000030) +#define rSDIDatSta (*(volatile unsigned *)0x5A000034) +#define rSDIFSTA (*(volatile unsigned *)0x5A000038) +#ifdef __BIG_ENDIAN +#define rSDIDAT (*(volatile unsigned char *)0x5A00003F) +#else +#define rSDIDAT (*(volatile unsigned char *)0x5A00003C) +#endif +#define rSDIIntMsk (*(volatile unsigned *)0x5A000040) + +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__S3C2410_H__*/