From: Duncan Ma <duncan.ma@amd.com>
Date: Tue, 1 Aug 2023 21:59:05 +0000 (-0400)
Subject: drm/amd/display: Fix dig register undefined
X-Git-Tag: v6.7-rc1~145^2~10^2~309
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f1eb045639a38ae9ee80c466f81f2e18204f6d25;p=users%2Fdwmw2%2Flinux.git

drm/amd/display: Fix dig register undefined

[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.

[How]
Fix stream encoder register define list.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 957f39e1381b8..aa0c27e76e4e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -308,7 +308,7 @@ static const struct dcn31_apg_mask apg_mask = {
 };
 
 #define stream_enc_regs_init(id)\
-	SE_DCN32_REG_LIST_RI(id)
+	SE_DCN35_REG_LIST_RI(id)
 
 static struct dcn10_stream_enc_registers stream_enc_regs[5];