From: Akihiko Odaki Date: Tue, 23 May 2023 02:43:36 +0000 (+0900) Subject: igb: Clear-on-read ICR when ICR.INTA is set X-Git-Tag: nvme-fixes-pull-request~144^2~4 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=efb1fd7a73aac29b02514c8aa46b752a7c7caa73;p=qemu-nvme.git igb: Clear-on-read ICR when ICR.INTA is set For GPIE.NSICR, Section 7.3.2.1.2 says: > ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the > clear on read occurs only if no bit is set in the IMS or at least one > bit is set in the IMS and there is a true interrupt as reflected in > ICR.INTA. e1000e does similar though it checks for CTRL_EXT.IAME, which does not exist on igb. Suggested-by: Sriram Yagnaraman Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 823dde8f28..d00b1caa6a 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -2598,6 +2598,8 @@ igb_mac_icr_read(IGBCore *core, int index) } else if (core->mac[IMS] == 0) { trace_e1000e_irq_icr_clear_zero_ims(); igb_lower_interrupts(core, ICR, 0xffffffff); + } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) { + igb_lower_interrupts(core, ICR, 0xffffffff); } else if (!msix_enabled(core->owner)) { trace_e1000e_irq_icr_clear_nonmsix_icr_read(); igb_lower_interrupts(core, ICR, 0xffffffff);