From: wdenk Date: Sun, 7 Oct 2001 12:15:54 +0000 (+0000) Subject: * Patch by Stefan Roese, 19 Sep 2001: X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=ee83e75f6a351ffe8d39ccab01662a0bc8543058;p=users%2Frw%2Fppcboot.git * Patch by Stefan Roese, 19 Sep 2001: - Watchdog support for ppc4xx added. - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup (ppc405gp). - Added OCRTC Board Support - SDRAM size autodetect added on some esd boards (ppc405) - Rework of some esd config files - Changed cpu defines for ppc4xx for Linux compatibility CONFIG_PPC405 -> CONFIG_4xx CONFIG_PPC405GP -> CONFIG_405GP CONFIG_PPC405CR -> CONFIG_405CR --- diff --git a/CHANGELOG b/CHANGELOG index 7e7182c..5f0a23b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,18 @@ To do: Modifications for 1.0.6: ====================================================================== +* Patch by Stefan Roese, 19 Sep 2001: +- Watchdog support for ppc4xx added. +- CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup + (ppc405gp). +- Added OCRTC Board Support +- SDRAM size autodetect added on some esd boards (ppc405) +- Rework of some esd config files +- Changed cpu defines for ppc4xx for Linux compatibility + CONFIG_PPC405 -> CONFIG_4xx + CONFIG_PPC405GP -> CONFIG_405GP + CONFIG_PPC405CR -> CONFIG_405CR + * Remove references to obsolete CFG_HWINFO_LEN stuff * Work around problem with transmit of 1st eth packet on AMX diff --git a/Makefile b/Makefile index 669cb6f..cc076b4 100644 --- a/Makefile +++ b/Makefile @@ -389,6 +389,15 @@ CPCIISER4_config: unconfig echo "VENDOR = esd" >>config.mk ; \ echo "#include " >config.h +OCRTC_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = ocrtc">>config.mk ; \ + echo "CPU = ppc4xx" >>config.mk ; \ + echo "VENDOR = esd" >>config.mk ; \ + echo "#include " >config.h + DASA_SIM_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd include ; \ diff --git a/README b/README index a076d72..65cddfb 100644 --- a/README +++ b/README @@ -206,7 +206,7 @@ The following options need to be configured: CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860 or CONFIG_MPC8240, CONFIG_MPC8260 or CONFIG_IOP480 - or CONFIG_PPC405GP + or CONFIG_405GP or CONFIG_MPC74xx - Board Type: Define exactly one of diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index b4f167e..eb6181e 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -144,7 +144,7 @@ int checkboard (void) } } - printf("\n FPGA: "); + printf("\nFPGA: "); /* display infos on fpgaimage */ index = 15; diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 697dc97..8ddee5b 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -157,7 +157,7 @@ int checkboard (void) } } - printf("\n FPGA: "); + printf("\nFPGA: "); /* display infos on fpgaimage */ index = 15; diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 1942509..4c76a50 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -210,7 +210,7 @@ int checkboard (void) else printf(" (PCI Adapter Version)"); - printf("\n FPGA: "); + printf("\nFPGA: "); /* display infos on fpgaimage */ index = 15; @@ -230,7 +230,17 @@ int checkboard (void) long int initdram (int board_type) { - return (16 * 1024*1024); + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ diff --git a/board/esd/cpci405/init.S b/board/esd/cpci405/init.S index fcd2688..2e6d0b7 100644 --- a/board/esd/cpci405/init.S +++ b/board/esd/cpci405/init.S @@ -42,6 +42,19 @@ #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ +#define MAGIC0 0x00000000 +#define MAGIC1 0x11111111 +#define MAGIC2 0x22222222 +#define MAGIC3 0x33333333 +#define MAGIC4 0x44444444 + +#define ADDR_ZERO 0x00000000 +#define ADDR_400 0x00000400 +#define ADDR_08MB 0x00800000 +#define ADDR_16MB 0x01000000 +#define ADDR_32MB 0x02000000 +#define ADDR_64MB 0x04000000 + #include #include @@ -184,12 +197,12 @@ sdram_init: mflr r31 //------------------------------------------------------------------- - // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) + // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) //------------------------------------------------------------------- addi r4,0,mem_mb0cf mtdcr memcfga,r4 - addis r4,0,0x0004 - ori r4,r4,0x6001 + addis r4,0,0x0008 + ori r4,r4,0x4001 mtdcr memcfgd,r4 //------------------------------------------------------------------- @@ -278,5 +291,176 @@ sdram_init: ..spinlp3: bdnz ..spinlp3 // spin loop + //------------------------------------------------------------------- + // Test if 64MByte is ok. + //------------------------------------------------------------------- + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + stw r3,0x00(r4) // store magic at 0 + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + stw r3,0x00(r4) // store magic at 8MB + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + stw r3,0x00(r4) // store magic at 16MB + addis r3,0,MAGIC3@h + ori r3,r3,MAGIC3@l + addis r4,0,ADDR_32MB@h + ori r4,r4,ADDR_32MB@l + stw r3,0x00(r4) // store magic at 32MB + + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + lwz r5,0x00(r4) // load from 0 + cmplw 0,r3,r5 + bne ..chk_32mb + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + lwz r5,0x00(r4) // load from 8mb + cmplw 0,r3,r5 + bne ..chk_32mb + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + lwz r5,0x00(r4) // load from 8mb + beq ..sdram_done + +..chk_32mb: + //------------------------------------------------------------------- + // Disable memory controller. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x0000 // set DC_EN=0 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0006 + ori r4,r4,0x2001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Wait some time + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp4: + bdnz ..spinlp4 // spin loop + + //------------------------------------------------------------------- + // Test if 32MByte is ok. + //------------------------------------------------------------------- + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + stw r3,0x00(r4) // store magic at 0 + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_400@h + ori r4,r4,ADDR_400@l + stw r3,0x00(r4) // store magic at 0x400 + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + stw r3,0x00(r4) // store magic at 8MB + addis r3,0,MAGIC3@h + ori r3,r3,MAGIC3@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + stw r3,0x00(r4) // store magic at 16MB + + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + lwz r5,0x00(r4) // load from 0 + cmplw 0,r3,r5 + bne ..chk_16mb + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_400@h + ori r4,r4,ADDR_400@l + lwz r5,0x00(r4) // load from 0x400 + cmplw 0,r3,r5 + bne ..chk_16mb + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + lwz r5,0x00(r4) // load from 8mb + cmplw 0,r3,r5 + beq ..sdram_done + +..chk_16mb: + //------------------------------------------------------------------- + // Disable memory controller. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x0000 // set DC_EN=0 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // 16 MB is left. + // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0004 + ori r4,r4,0x6001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Wait some time + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp5: + bdnz ..spinlp5 // spin loop + +..sdram_done: mtlr r31 // restore lr blr diff --git a/board/esd/cpciiser4/config.mk b/board/esd/cpciiser4/config.mk index 83f07fe..58574cb 100644 --- a/board/esd/cpciiser4/config.mk +++ b/board/esd/cpciiser4/config.mk @@ -22,8 +22,9 @@ # # -# esd ADCIOP boards +# esd CPCIISER4 boards # #TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFFD0000 +#TEXT_BASE = 0xFFFD0000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index c69a0c2..24ae559 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -34,6 +34,10 @@ #define FPGA_DEBUG #endif +#if 0 +#define FPGA_DEBUG2 +#endif + /* fpga configuration data - generated by bin2cc */ const unsigned char fpgadata[] = { @@ -149,7 +153,7 @@ int checkboard (void) } } - printf("\n FPGA: "); + printf("\nFPGA: "); /* display infos on fpgaimage */ index = 15; diff --git a/board/esd/cpciiser4/fpgadata.c b/board/esd/cpciiser4/fpgadata.c index 5588fba..e363bb0 100644 --- a/board/esd/cpciiser4/fpgadata.c +++ b/board/esd/cpciiser4/fpgadata.c @@ -2013,7 +2013,7 @@ 0x02,0x01,0x04,0x02,0xe8,0x01,0x02,0x01,0xe5,0x02,0x02,0x01,0x02,0xe5,0x02,0x01, 0x04,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01, 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, - 0x08,0x01,0xe6,0xe5,0x3c,0x35,0x01,0x09,0x0e,0x9f,0x01,0xe7,0x36,0xe2,0x12,0xe5, + 0x08,0x01,0xe6,0xe5,0x3c,0x35,0x01,0x09,0x0e,0x9f,0x01,0xe7,0x36,0xe3,0x12,0xe5, 0xe7,0x46,0x13,0x17,0x25,0x8a,0x0a,0xe5,0xe5,0x1c,0x48,0x0c,0x09,0x07,0xe5,0x07, 0xa0,0xe6,0x47,0x1b,0x12,0x0c,0x0d,0x06,0x3c,0x5b,0x5c,0x03,0x0f,0xe5,0x08,0x0a, 0xe5,0x10,0x16,0xe5,0x05,0x6d,0x07,0xe5,0x01,0x63,0x21,0x13,0x15,0x7e,0x02,0xe5, @@ -2053,7 +2053,7 @@ 0x09,0x13,0x42,0xe5,0x8e,0x04,0xe7,0x3f,0x13,0x44,0x90,0x03,0xe6,0xe5,0x8f,0x9d, 0x03,0x13,0x09,0x09,0x09,0x1d,0x09,0x0c,0x06,0x09,0x09,0x36,0x06,0x09,0x09,0x09, 0x09,0x09,0x09,0x09,0x09,0x09,0x15,0x01,0xe5,0x35,0x05,0x03,0x05,0x0d,0x0f,0x2a, - 0x97,0x06,0x02,0xe5,0x98,0x8e,0x05,0x03,0xe2,0x50,0x14,0x09,0x09,0x09,0x09,0x09, + 0x97,0x06,0x02,0xe5,0x98,0x8e,0x05,0x03,0xe3,0x50,0x14,0x09,0x09,0x09,0x09,0x09, 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x04,0xe6,0x01,0xe5,0x04,0x09,0xe8, 0x04,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x0f, 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x08,0xe5,0x06,0xe6, diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c index a34022d..d2bab51 100644 --- a/board/esd/dasa_sim/dasa_sim.c +++ b/board/esd/dasa_sim/dasa_sim.c @@ -190,7 +190,7 @@ int checkboard (void) printf(" (Id=%d Version=%d Revision=%d)", (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1); - printf("\n FPGA: "); + printf("\nFPGA: "); /* display infos on fpgaimage */ index = 15; @@ -203,7 +203,7 @@ int checkboard (void) } else { - printf("\n FPGA: Booting failed!"); + printf("\nFPGA: Booting failed!"); } putc ('\n'); diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile new file mode 100644 index 0000000..7a9d25a --- /dev/null +++ b/board/esd/ocrtc/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/ocrtc/config.mk b/board/esd/ocrtc/config.mk new file mode 100644 index 0000000..f123319 --- /dev/null +++ b/board/esd/ocrtc/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c new file mode 100644 index 0000000..c05f0ce --- /dev/null +++ b/board/esd/ocrtc/flash.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i=0; i +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#define MAGIC0 0x00000000 +#define MAGIC1 0x11111111 +#define MAGIC2 0x22222222 +#define MAGIC3 0x33333333 +#define MAGIC4 0x44444444 + +#define ADDR_ZERO 0x00000000 +#define ADDR_400 0x00000400 +#define ADDR_08MB 0x00800000 +#define ADDR_16MB 0x01000000 +#define ADDR_32MB 0x02000000 +#define ADDR_64MB 0x04000000 + +#include +#include + +#include +#include + + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 // save link register + bl ..getAddr +..getAddr: + mflr r3 // get address of ..getAddr + mtlr r4 // restore link register + addi r4,0,18 // set ctr to 10; used to prefetch + mtctr r4 // 10 cache lines to fit this function + // in cache (gives us 8x10=80 instrctns) +..ebcloop: + icbt r0,r3 // prefetch cache line for addr in r3 + addi r3,r3,32 // move to next cache line + bdnz ..ebcloop // continue for 10 cache lines + + //------------------------------------------------------------------- + // Delay to ensure all accesses to ROM are complete before changing + // bank 0 timings. 200usec should be enough. + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp: + bdnz ..spinlp // spin loop + + //----------------------------------------------------------------------- + // Memory Bank 0 (Flash Bank 0) initialization + //----------------------------------------------------------------------- + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W), + ori r4,r4,0xA000 // BW=0x1(16 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 1 (Flash Bank 1) initialization + //----------------------------------------------------------------------- + addi r4,0,pb1ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0xFF85 // BAS=0xFF8,BS=0x2(4MB),BU=0x3(R/W), + ori r4,r4,0xA000 // BW=0x1(16 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 2 (PLD - FPGA-boot) initialization + //----------------------------------------------------------------------- + addi r4,0,pb2ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb2cr + mtdcr ebccfga,r4 + addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0x8000 // BW=0x0(8 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 3 (PLD - OSL) initialization + //----------------------------------------------------------------------- + addi r4,0,pb3ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb3cr + mtdcr ebccfga,r4 + addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0x8000 // BW=0x0(8 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 4 (Spartan2 1) initialization + //----------------------------------------------------------------------- + addi r4,0,pb4ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb4cr + mtdcr ebccfga,r4 + addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xc000 // BW=0x10(32 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 5 (Spartan2 2) initialization + //----------------------------------------------------------------------- + addi r4,0,pb5ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb5cr + mtdcr ebccfga,r4 + addis r4,0,0xF031 // BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xc000 // BW=0x10(32 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 6 (Virtex 1) initialization + //----------------------------------------------------------------------- + addi r4,0,pb6ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb6cr + mtdcr ebccfga,r4 + addis r4,0,0xF041 // BAS=0xF04,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xc000 // BW=0x10(32 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 7 (Virtex 2) initialization + //----------------------------------------------------------------------- + addi r4,0,pb7ap + mtdcr ebccfga,r4 + addis r4,0,0x9201 + ori r4,r4,0x5480 // disable Ready + mtdcr ebccfgd,r4 + + addi r4,0,pb7cr + mtdcr ebccfga,r4 + addis r4,0,0xF051 // BAS=0xF05,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xc000 // BW=0x10(32 bits) + mtdcr ebccfgd,r4 + + nop // pass2 DCR errata #8 + blr + +//----------------------------------------------------------------------------- +// Function: sdram_init +// Description: Configures SDRAM memory banks. +// Auto Memory Configuration option reads the SDRAM EEPROM +// via the IIC bus and then configures the SDRAM memory +// banks appropriately. If Auto Memory Configuration is +// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is +// plugged, ie. the DIMM that shipped wih the Eval board. +//----------------------------------------------------------------------------- + .globl sdram_init + +sdram_init: + + mflr r31 + + //------------------------------------------------------------------- + // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0008 + ori r4,r4,0x4001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. + // To set the appropriate timings, we need to know the SDRAM speed. + // We can use the PLB speed since the SDRAM speed is the same as + // the PLB speed. The PLB speed is the FBK divider times the + // 405GP reference clock, which on the Walnut board is 33Mhz. + // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is + // 100Mhz; if FBK is 3, SDRAM is 133Mhz. + // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and + // maybe 133Mhz. + //------------------------------------------------------------------- + mfdcr r5,strap // determine FBK divider + // via STRAP reg to calc PLB speed. + // SDRAM speed is the same as the PLB + // speed. + rlwinm r4,r5,4,0x3 // get FBK divide bits + +..chk_66: + cmpi %cr0,0,r4,0x1 + bne ..chk_100 + addis r6,0,0x0085 // SDTR1 value for 66Mhz + ori r6,r6,0x4005 + addis r7,0,0x03F8 // RTR value for 66Mhz + b ..sdram_ok +..chk_100: + cmpi %cr0,0,r4,0x2 + bne ..chk_133 + addis r6,0,0x0086 // SDTR1 value for 100Mhz + ori r6,r6,0x400D + addis r7,0,0x05F0 // RTR value for 100Mhz + b ..sdram_ok +..chk_133: + addis r6,0,0x0107 // SDTR1 value for 133Mhz + ori r6,r6,0x4015 + addis r7,0,0x07F0 // RTR value for 133Mhz + +..sdram_ok: + //------------------------------------------------------------------- + // Set SDTR1 + //------------------------------------------------------------------- + addi r4,0,mem_sdtr1 + mtdcr memcfga,r4 + mtdcr memcfgd,r6 + + //------------------------------------------------------------------- + // Set RTR + //------------------------------------------------------------------- + addi r4,0,mem_rtr + mtdcr memcfga,r4 + mtdcr memcfgd,r7 + + //------------------------------------------------------------------- + // Delay to ensure 200usec have elapsed since reset. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0000 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp2: + bdnz ..spinlp2 // spin loop + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Delay to ensure 10msec have elapsed since reset. This is + // required for the MPC952 to stabalize. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles + // This delay should occur before accessing SDRAM. + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp3: + bdnz ..spinlp3 // spin loop + + //------------------------------------------------------------------- + // Test if 64MByte is ok. + //------------------------------------------------------------------- + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + stw r3,0x00(r4) // store magic at 0 + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + stw r3,0x00(r4) // store magic at 8MB + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + stw r3,0x00(r4) // store magic at 16MB + addis r3,0,MAGIC3@h + ori r3,r3,MAGIC3@l + addis r4,0,ADDR_32MB@h + ori r4,r4,ADDR_32MB@l + stw r3,0x00(r4) // store magic at 32MB + + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + lwz r5,0x00(r4) // load from 0 + cmplw 0,r3,r5 + bne ..chk_32mb + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + lwz r5,0x00(r4) // load from 8mb + cmplw 0,r3,r5 + bne ..chk_32mb + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + lwz r5,0x00(r4) // load from 8mb + beq ..sdram_done + +..chk_32mb: + //------------------------------------------------------------------- + // Disable memory controller. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x0000 // set DC_EN=0 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0006 + ori r4,r4,0x2001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Wait some time + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp4: + bdnz ..spinlp4 // spin loop + + //------------------------------------------------------------------- + // Test if 32MByte is ok. + //------------------------------------------------------------------- + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + stw r3,0x00(r4) // store magic at 0 + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_400@h + ori r4,r4,ADDR_400@l + stw r3,0x00(r4) // store magic at 0x400 + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + stw r3,0x00(r4) // store magic at 8MB + addis r3,0,MAGIC3@h + ori r3,r3,MAGIC3@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + stw r3,0x00(r4) // store magic at 16MB + + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + lwz r5,0x00(r4) // load from 0 + cmplw 0,r3,r5 + bne ..chk_16mb + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_400@h + ori r4,r4,ADDR_400@l + lwz r5,0x00(r4) // load from 0x400 + cmplw 0,r3,r5 + bne ..chk_16mb + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + lwz r5,0x00(r4) // load from 8mb + cmplw 0,r3,r5 + beq ..sdram_done + +..chk_16mb: + //------------------------------------------------------------------- + // Disable memory controller. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x0000 // set DC_EN=0 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // 16 MB is left. + // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0004 + ori r4,r4,0x6001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Wait some time + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp5: + bdnz ..spinlp5 // spin loop + +..sdram_done: + mtlr r31 // restore lr + blr diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c new file mode 100644 index 0000000..39adc68 --- /dev/null +++ b/board/esd/ocrtc/ocrtc.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "ocrtc.h" +#include +#include <405gp_i2c.h> +#include +#include + +/* ------------------------------------------------------------------------- */ + +int board_pre_init (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f(void) +{ + return 0; /* dummy implementation */ +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + unsigned char *s = getenv("serial#"); + unsigned char *e; + + if (!s) + { + printf ("### No HW ID - assuming OCRTC"); + } + else + { + for (e=s; *e; ++e) { + if (*e == ' ') + break; + } + + for ( ; s> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h new file mode 100644 index 0000000..b50d521 --- /dev/null +++ b/board/esd/ocrtc/ocrtc.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/ocrtc/ppcboot.lds b/board/esd/ocrtc/ppcboot.lds new file mode 100644 index 0000000..eb0fe75 --- /dev/null +++ b/board/esd/ocrtc/ppcboot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/esd/ocrtc/init.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/405gp_enet.o (.text) + common/dlmalloc.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + ppc/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/ocrtc/ppcboot.lds.debug b/board/esd/ocrtc/ppcboot.lds.debug new file mode 100644 index 0000000..9e9ff00 --- /dev/null +++ b/board/esd/ocrtc/ppcboot.lds.debug @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/pip405/pci_pip405.c b/board/pip405/pci_pip405.c index 008f969..243bdd8 100644 --- a/board/pip405/pci_pip405.c +++ b/board/pip405/pci_pip405.c @@ -38,7 +38,7 @@ void pciinfo(int bus_no); -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP #ifdef CONFIG_PCI @@ -1502,4 +1502,4 @@ void pciScanForDevices(int BusNum) #endif /* CONFIG_PCI */ -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ diff --git a/board/pip405/video.c b/board/pip405/video.c index 199e235..617db25 100644 --- a/board/pip405/video.c +++ b/board/pip405/video.c @@ -33,7 +33,7 @@ #include #include #include "video.h" -#ifdef CONFIG_PPC405 +#ifdef CONFIG_4xx #include <405gp_pci.h> #endif #include "vga_table.h" diff --git a/common/board.c b/common/board.c index 9c0f069..3ddf665 100644 --- a/common/board.c +++ b/common/board.c @@ -158,6 +158,7 @@ board_init_f (ulong bootflag) defined(CONFIG_WALNUT405) || \ defined(CONFIG_PIP405) || \ defined(CONFIG_CPCIISER4) || \ + defined(CONFIG_OCRTC) || \ defined(CONFIG_ADCIOP) || \ defined(CONFIG_DASA_SIM) || \ defined(CONFIG_LWMON) || \ @@ -428,10 +429,8 @@ board_init_f (ulong bootflag) bd->bi_procfreq = idata->cpu_clk; /* Processor Speed, In Hz */ bd->bi_plb_busfreq = bd->bi_busfreq; -#ifdef CONFIG_PPC405 +#ifdef CONFIG_405GP bd->bi_pci_busfreq = get_PCI_freq(); -#else - bd->bi_pci_busfreq = bd->bi_busfreq; #endif #endif diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index a7ac61b..90136ce 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -53,7 +53,7 @@ void bedbug_init( void ) { /* -------------------------------------------------- */ -#if defined(CONFIG_PPC405) +#if defined(CONFIG_4xx) void bedbug405_init( void ); bedbug405_init(); #elif defined(CONFIG_MPC860) @@ -456,7 +456,7 @@ void do_bootvx( cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[] ) unsigned long bootaddr; /* Address to put the bootline */ char * bootline; /* Text of the bootline */ char * tmp; /* Temporary char pointer */ -#if defined(CONFIG_PPC405) || defined(CONFIG_IOP480) +#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) char build_buf[ 80 ]; /* Buffer for building the bootline */ #endif /* -------------------------------------------------- */ @@ -494,6 +494,9 @@ void do_bootvx( cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[] ) #elif defined(CONFIG_CPCI405) tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS; memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 ); +#elif defined(CONFIG_OCRTC) + tmp = (char *)CFG_ETHERNET_MAC_ADDR; + memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 ); #else printf( "## Ethernet MAC address not copied to NV RAM\n" ); #endif @@ -517,7 +520,7 @@ void do_bootvx( cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[] ) } else { -#if defined(CONFIG_PPC405) +#if defined(CONFIG_4xx) sprintf( build_buf, "ibmEmac(0,0)" ); if(( tmp = getenv( "hostname" )) != NULL ) diff --git a/common/cmd_boot.c b/common/cmd_boot.c index 61ae51d..6da6af2 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -60,14 +60,16 @@ void do_bdinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) print_num ("immr_base", bd->bi_immr_base ); #endif print_num ("bootflags", bd->bi_bootflags ); -#if defined(CONFIG_PPC405) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) print_str ("procfreq", strmhz(buf, bd->bi_procfreq)); print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq)); +#if defined(CONFIG_405GP) print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq)); +#endif #else print_str ("intfreq", strmhz(buf, bd->bi_intfreq)); print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); -#endif /* CONFIG_PPC405) */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ printf ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 53becad..05d545c 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -35,7 +35,7 @@ #include #include #include -#ifdef CONFIG_PPC405 +#ifdef CONFIG_4xx #include <405gp_pci.h> #endif diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c index 2ab13bf..5c35f47 100644 --- a/cpu/ppc4xx/405gp_enet.c +++ b/cpu/ppc4xx/405gp_enet.c @@ -67,7 +67,7 @@ #include #include -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP #define MAXPACKET 1518 @@ -763,4 +763,4 @@ int eth_rx(void) return length; } -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 97fe0f8..6727a7d 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -55,6 +55,8 @@ | - On CPCI-405 pci base address and size is generated from | SDRAM and FLASH size (CFG regs not used anymore) | - Some minor changes for CPCI-405-A (adapter version) +| 14-Sep-01 stefan.roese@esd-electronics.com +| - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup +----------------------------------------------------------------------------*/ #include @@ -67,7 +69,7 @@ void pciinfo(int bus_no); -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP #ifdef CONFIG_PCI @@ -213,7 +215,12 @@ void pci_init(bd_t *bd) # if (CONFIG_PCI_HOST == PCI_HOST_AUTO) if (mfdcr(strap) & PSR_PCI_ARBIT_EN) # endif - PCI_Scan(0); + { +# ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +# endif + PCI_Scan(0); + } #endif /* CONFIG_PCI_PNP */ } @@ -367,6 +374,21 @@ void PCI_Scan(int BusNum) default: PCI_Config_Device(BusDevFunc, 6); } +#ifdef CONFIG_PCI_SCAN_SHOW + /* + * Don't print own pci regs (ppc405gp located @ bus 0, device 0) + */ + if ((BusNum != 0) || (Device != 0)) + { + printf(" %02x %02x %04x %04x %04x %02x\n", + BusNum, + Device, + PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID, 2), + PCI_Read_CFG_Reg(BusDevFunc, PCIDEVICEID, 2), + PCI_Read_CFG_Reg(BusDevFunc, PCICLASSCODE, 2), + PCI_Read_CFG_Reg(BusDevFunc, PCIINTLINE, 1)); + } +#endif } else { @@ -917,6 +939,6 @@ pciBheaderPrint(PCI_HEADER_BRIDGE * pB) #endif /* CONFIG_PCI */ -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ #endif /* CONFIG_PIP405 */ diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c index ea4a4b6..f8d6903 100644 --- a/cpu/ppc4xx/bedbug_405.c +++ b/cpu/ppc4xx/bedbug_405.c @@ -11,7 +11,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_PPC405) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_4xx) #define MAX_BREAK_POINTS 4 diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 907e015..a6d7f3d 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -46,15 +46,15 @@ int checkcpu(long clock) uint pvr = get_pvr(); char buf[32]; -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) PPC405_SYS_INFO sys_info; get_sys_info(&sys_info); -#if CONFIG_PPC405GP +#if CONFIG_405GP printf("IBM PowerPC 405GP Rev. "); #endif -#if CONFIG_PPC405CR +#if CONFIG_405CR printf("IBM PowerPC 405CR Rev. "); #endif switch (pvr) @@ -63,7 +63,7 @@ int checkcpu(long clock) putc('B'); break; case PVR_405GP_RC: -#if CONFIG_PPC405CR +#if CONFIG_405CR case PVR_405CR_RC: #endif putc('C'); @@ -71,7 +71,7 @@ int checkcpu(long clock) case PVR_405GP_RD: putc('D'); break; -#if CONFIG_PPC405GP +#if CONFIG_405GP case PVR_405GP_RE: putc('E'); break; @@ -92,7 +92,7 @@ int checkcpu(long clock) sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); -#if CONFIG_PPC405GP +#if CONFIG_405GP if (mfdcr(strap) & PSR_PCI_ASYNC_EN) printf(" PCI async ext clock used, "); else @@ -115,7 +115,7 @@ int checkcpu(long clock) break; } -#endif /* CONFIG_PPC405 */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ #ifdef CONFIG_IOP480 printf("PLX IOP480 (PVR=%08x)", pvr); @@ -147,14 +147,34 @@ void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) PPC405_SYS_INFO sys_info; get_sys_info(&sys_info); return (sys_info.freqProcessor); -#endif /* CONFIG_PPC405 */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ #ifdef CONFIG_IOP480 return (66000000); #endif /* CONFIG_IOP480 */ } + + +#if defined(CONFIG_WATCHDOG) +void +watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + reset_4xx_watchdog(); + if (re_enable) enable_interrupts(); +} + +void +reset_4xx_watchdog(void) +{ + /* + * Clear TSR(WIS) bit + */ + mtspr(tsr, 0x40000000); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 0321379..5d0c5f1 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -23,6 +23,8 @@ #include #include <405gp_enet.h> +#include +#include /* @@ -33,6 +35,19 @@ void cpu_init_f (void) { +#if defined(CONFIG_WATCHDOG) + unsigned long val; + + val = mfspr(tcr); + val |= 0xf0000000; /* generate system reset after 2.684 seconds */ + mtspr(tcr, val); + + val = mfspr(tsr); + val |= 0x80000000; /* enable watchdog timer */ + mtspr(tsr, val); + + reset_4xx_watchdog(); +#endif /* CONFIG_WATCHDOG */ } /* @@ -41,7 +56,7 @@ cpu_init_f (void) void cpu_init_r (bd_t *bd) { -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP unsigned long reg; /* @@ -62,5 +77,5 @@ cpu_init_r (bd_t *bd) reg = reg << 8; reg |= bd->bi_enetaddr[5]; out32 (EMAC_IAL, reg); -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ } diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 5ffdabb..88bdd76 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -113,6 +113,7 @@ void interrupt_init (bd_t *bd) { int vec; + unsigned long val; /* * Mark all irqs as free @@ -124,12 +125,12 @@ interrupt_init (bd_t *bd) irq_vecs[vec].count = 0; } -#ifdef CONFIG_PPC405 +#ifdef CONFIG_4xx /* * Init PIT */ set_pit(bd->bi_intfreq / 1000); -#endif /* CONFIG_PPC405 */ +#endif /* CONFIG_4xx */ #ifdef CONFIG_ADCIOP /* @@ -141,7 +142,9 @@ interrupt_init (bd_t *bd) /* * Enable PIT */ - set_tcr(0x04400000); + val = mfspr(tcr); + val |= 0x04400000; + mtspr(tcr, val); /* * Set EVPR to 0 @@ -253,6 +256,11 @@ void timer_interrupt(struct pt_regs *regs) printf ("*** Timer Interrupt *** "); #endif timestamp++; + +#if defined(CONFIG_WATCHDOG) + if ((timestamp % 1000) == 0) + reset_4xx_watchdog(); +#endif /* CONFIG_WATCHDOG */ } /****************************************************************************/ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 6518121..ac17447 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -25,7 +25,7 @@ #include #include "version.h" -#define CONFIG_PPC405GP 1 /* needed for Linux kernel header files */ +#define CONFIG_405GP 1 /* needed for Linux kernel header files */ #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 2b22805..610c781 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -48,7 +48,7 @@ #include <405_mal.h> #include -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP /***********************************************************/ @@ -221,4 +221,4 @@ int miiphy_duplex() return (speed); } -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 9fd2384..6ef73fd 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -259,7 +259,7 @@ serial_tstc() /*****************************************************************************/ -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) #define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */ @@ -681,4 +681,4 @@ kgdb_interruptible (int yes) #endif #endif /* CFG_CMD_KGDB */ -#endif /* CONFIG_PPC405 */ +#endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index bb2874f..31c3eeb 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -32,7 +32,7 @@ #define ONE_BILLION 1000000000 -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) void get_sys_info (PPC405_SYS_INFO *sysInfo) { @@ -194,18 +194,18 @@ void get_sys_info (PPC405_SYS_INFO *sysInfo) } } -#endif /* CONFIG_PPC405 */ +#endif /* CONFIG_405GP || CONFIG_405CR */ ulong get_gclk_freq (void) { ulong val; -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) PPC405_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqProcessor; -#endif /* CONFIG_PPC405 */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ #ifdef CONFIG_IOP480 val = 66000000; @@ -222,12 +222,12 @@ ulong get_gclk_freq (void) ulong get_bus_freq (ulong gclk_freq) { ulong val; -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP PPC405_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqPLB; -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ #ifdef CONFIG_IOP480 val = 66; @@ -243,17 +243,17 @@ ulong get_bus_freq (ulong gclk_freq) ulong get_OPB_freq (void) { ulong val; -#ifdef CONFIG_PPC405GP +#ifdef CONFIG_405GP PPC405_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqPLB/sys_info.pllOpbDiv; -#endif /* CONFIG_PPC405GP */ +#endif /* CONFIG_405GP */ return val; } -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) /******************************************** * get_PCI_freq @@ -268,5 +268,5 @@ ulong get_PCI_freq (void) val = sys_info.freqPLB/sys_info.pllPciDiv; return val; } -#endif +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ /*---------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a325724..b0887f9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -240,7 +240,7 @@ boot_warm: #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#ifdef CONFIG_PPC405 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) //----------------------------------------------------------------------- // Clear and set up some registers. @@ -299,9 +299,11 @@ boot_warm: GET_GOT /* initialize GOT access */ + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + bl board_init_f /* run first part of init code (from Flash) */ -#endif /* CONFIG_PPC405 */ +#endif /* CONFIG_405GP || CONFIG_405CR */ .globl _start_of_vectors diff --git a/include/config_AR405.h b/include/config_AR405.h index aa234f2..ceff179 100644 --- a/include/config_AR405.h +++ b/include/config_AR405.h @@ -33,8 +33,8 @@ * (easy to change) */ -#define CONFIG_PPC405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_AR405 1 /* ...on a AR405 board */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ diff --git a/include/config_CANBT.h b/include/config_CANBT.h index 13ca168..9bb8e74 100644 --- a/include/config_CANBT.h +++ b/include/config_CANBT.h @@ -33,8 +33,8 @@ * (easy to change) */ -#define CONFIG_PPC405CR 1 /* This is a PPC405CR CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405CR 1 /* This is a PPC405CR CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CANBT 1 /* ...on a CANBT board */ #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h index 74be4b6..0b8e755 100644 --- a/include/config_CPCI405.h +++ b/include/config_CPCI405.h @@ -33,8 +33,8 @@ * (easy to change) */ -#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ @@ -42,11 +42,20 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#if 0 +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" +#endif + #undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ +#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ "bootm ffc00000 ffca0000" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "bootm ffc00000" +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -54,11 +63,9 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ CFG_CMD_IDE | \ - CFG_CMD_ASKENV | \ CFG_CMD_BEDBUG | \ CFG_CMD_EEPROM ) @@ -68,7 +75,7 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ /* * Miscellaneous configurable options @@ -114,6 +121,8 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ diff --git a/include/config_CPCIISER4.h b/include/config_CPCIISER4.h index 960ed70..8606dc3 100644 --- a/include/config_CPCIISER4.h +++ b/include/config_CPCIISER4.h @@ -33,8 +33,8 @@ * (easy to change) */ -#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ @@ -43,10 +43,7 @@ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm ffc00000 ffca0000" +#define CONFIG_BOOTCOMMAND "bootm fff00000" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -54,10 +51,8 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ - CFG_CMD_ASKENV | \ CFG_CMD_BEDBUG | \ CFG_CMD_EEPROM ) @@ -119,33 +114,15 @@ #define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_FLASH_BASE 0xFFFC0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ /* @@ -182,7 +159,7 @@ #undef CONFIG_I2C_X /* 8 bit access */ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x200 /* 512 bytes may be used for env vars */ +#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ diff --git a/include/config_ERIC.h b/include/config_ERIC.h index 3096de8..06bc61e 100644 --- a/include/config_ERIC.h +++ b/include/config_ERIC.h @@ -33,8 +33,8 @@ * (easy to change) */ -#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_ERIC 1 /* ...on a ERIC board */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ diff --git a/include/config_OCRTC.h b/include/config_OCRTC.h new file mode 100644 index 0000000..a322f81 --- /dev/null +++ b/include/config_OCRTC.h @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_OCRTC 1 /* ...on a OCRTC board */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "go fff00100" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ + +#else /* Use EEPROM for environment variables */ +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#undef CONFIG_I2C_X /* 8 bit access */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + + +/* On Chip Memory location */ +#define OCM_DATA_ADDR 0xF8000000 + +#define CFG_ETHERNET_MAC_ADDR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/config_PIP405.h b/include/config_PIP405.h index 41c4fee..b7b3ba4 100644 --- a/include/config_PIP405.h +++ b/include/config_PIP405.h @@ -32,8 +32,8 @@ * High Level Configuration Options * (easy to change) ***********************************************************/ -#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PIP405 1 /* ...on a PIP405 board */ /*********************************************************** * Clock diff --git a/include/config_WALNUT405.h b/include/config_WALNUT405.h index 0456f1c..4b4f062 100644 --- a/include/config_WALNUT405.h +++ b/include/config_WALNUT405.h @@ -33,8 +33,8 @@ * (easy to change) */ -#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ diff --git a/include/ppcboot.h b/include/ppcboot.h index b7bee0b..7546b7c 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -100,11 +100,13 @@ typedef struct bd_info { unsigned long bi_vco; /* VCO Out from PLL, in MHz */ #endif unsigned long bi_baudrate; /* Console Baudrate */ -#if defined(CONFIG_PPC405) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ +#endif +#if defined(CONFIG_405GP) unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif @@ -194,6 +196,7 @@ void inline setenv (char *, char *); defined (CONFIG_WALNUT405) || \ defined (CONFIG_PIP405) || \ defined (CONFIG_CPCIISER4) || \ + defined (CONFIG_OCRTC) || \ defined (CONFIG_DASA_SIM) || \ defined (CONFIG_ERIC) /* $(CPU)/405gp_pci.c */ @@ -234,6 +237,7 @@ void reset_phy (void); defined(CONFIG_WALNUT405) || \ defined(CONFIG_PIP405) || \ defined(CONFIG_CPCIISER4) || \ + defined(CONFIG_OCRTC) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_TQM8260) || \ defined(CONFIG_PM826) || \ @@ -291,6 +295,7 @@ void load_sernum_ethaddr(bd_t *bd); defined(CONFIG_WALNUT405) || \ defined(CONFIG_PIP405) || \ defined(CONFIG_CPCIISER4) || \ + defined(CONFIG_OCRTC) || \ defined(CONFIG_ADCIOP) || \ defined(CONFIG_DASA_SIM) || \ defined(CONFIG_LWMON) || \ @@ -373,18 +378,18 @@ void get_8260_clks (void); void prt_8260_clks (void); #elif defined(CONFIG_8xx) || \ defined(CONFIG_IOP480) || \ - defined(CONFIG_PPC405) || \ + defined(CONFIG_4xx) || \ defined(CONFIG_CU824) ulong get_gclk_freq (void); ulong get_OPB_freq (void); -#ifdef CONFIG_PPC405 +#ifdef CONFIG_4xx ulong get_PCI_freq (void); #endif #endif ulong get_bus_freq (ulong); -#if defined(CONFIG_PPC405) || defined(CONFIG_IOP480) +#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) void get_sys_info (PPC405_SYS_INFO *); #endif @@ -393,6 +398,11 @@ void get_sys_info (PPC405_SYS_INFO *); void reset_8xx_watchdog(volatile immap_t *immr); #endif +/* $(CPU)/cpu.c */ +#if defined(CONFIG_4xx) +void reset_4xx_watchdog(void); +#endif + /* $(CPU)/cpu_init.c */ #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr);