From: wdenk Date: Mon, 4 Dec 2000 20:28:34 +0000 (+0000) Subject: * Start RTC for some configs X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=ea712cb8608a7c418e0d271caa8ae13b928f2dcf;p=users%2Frw%2Fppcboot.git * Start RTC for some configs * Fixes for ethernet on MPC8260 FEC * Fixes for console on SCCx --- diff --git a/CHANGELOG b/CHANGELOG index a95708a..348f2a6 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -61,6 +61,10 @@ To do: Modifications since 0.6.4: ====================================================================== +* Fixes for ethernet on MPC8260 FEC + +* Fixes for console on SCCx + * Modify "initrd_high" feature to allow for specifying a memory limit * Fixes for (F)ADS configuration diff --git a/include/asm/immap_8260.h b/include/asm/immap_8260.h index c96bffb..4f9894c 100644 --- a/include/asm/immap_8260.h +++ b/include/asm/immap_8260.h @@ -427,9 +427,4 @@ typedef struct immap { char res11[4096]; } immap_t; -/* The 8260 relies heavily on the IMMR, so we keep it around as a - * kernel global symbol now. Should have done this for the 8xx...... - */ -immap_t *immr; - #endif /* __IMMAP_82XX__ */ diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 6b5ad88..2a659c7 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -41,18 +41,23 @@ #define CFG_CMD_NET 0x00000080 /* bootp, tftpboot, rarpboot */ #define CFG_CMD_ENV 0x00000100 /* saveenv */ #define CFG_CMD_KGDB 0x00000200 /* kgdb */ -#define CFG_CMD_IDE 0x00000400 /* IDE harddisk support */ -#define CFG_CMD_PCI 0x00000800 /* pciinfo */ -#define CFG_CMD_IRQ 0x00001000 /* irqinfo */ -#define CFG_CMD_BOOTD 0x00002000 /* bootd */ -#define CFG_CMD_CONSOLE 0x00004000 /* coninfo */ +#define CFG_CMD_PCMCIA 0x00000400 /* PCMCIA support */ +#define CFG_CMD_IDE 0x00000800 /* IDE harddisk support */ +#define CFG_CMD_PCI 0x00001000 /* pciinfo */ +#define CFG_CMD_IRQ 0x00002000 /* irqinfo */ +#define CFG_CMD_BOOTD 0x00004000 /* bootd */ +#define CFG_CMD_CONSOLE 0x00008000 /* coninfo */ #define CFG_CMD_ALL 0xFFFFFFFF /* ALL commands */ /* Commands that are considered "non-standard" for some reason * (memory hogs, requires special hardware, not fully tested, etc.) */ -#define CFG_CMD_NONSTD (CFG_CMD_KGDB | CFG_CMD_IDE | CFG_CMD_PCI | CFG_CMD_IRQ) +#define CFG_CMD_NONSTD (CFG_CMD_KGDB | \ + CFG_CMD_IDE | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ ) /* Default configuration */ diff --git a/include/cmd_pcmcia.h b/include/cmd_pcmcia.h index e8148e3..cf9d273 100644 --- a/include/cmd_pcmcia.h +++ b/include/cmd_pcmcia.h @@ -27,6 +27,7 @@ #ifndef _CMD_PCMCIA_H #define _CMD_PCMCIA_H +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CMD_TBL_PINIT MK_CMD_TBL_ENTRY( \ "pinit", 4, 2, 1, do_pinit, \ "pinit - initialize PCMCIA sub-system\n", \ @@ -34,6 +35,9 @@ ), void do_pinit (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); +#else +#define CMD_TBL_PINIT +#endif #endif /* _CMD_PCMCIA_H */ diff --git a/include/commproc.h b/include/commproc.h index 93ddb83..dcce21b 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -212,6 +212,17 @@ typedef struct smc_centronics { #define CPM_BRG_CD_MASK ((uint)0x00001ffe) #define CPM_BRG_DIV16 ((uint)0x00000001) +/* SI Clock Route Register +*/ +#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) +#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) +#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) +#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) +#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) +#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) + /* SCCs. */ #define SCC_GSMRH_IRP ((uint)0x00040000) diff --git a/include/config_ETX094.h b/include/config_ETX094.h index 2206b7b..cf83f0e 100644 --- a/include/config_ETX094.h +++ b/include/config_ETX094.h @@ -172,6 +172,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/include/config_FPS850L.h b/include/config_FPS850L.h index 8d385c8..03caf07 100644 --- a/include/config_FPS850L.h +++ b/include/config_FPS850L.h @@ -168,6 +168,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/include/config_IVMS8.h b/include/config_IVMS8.h index e40d754..21b1cc7 100644 --- a/include/config_IVMS8.h +++ b/include/config_IVMS8.h @@ -64,12 +64,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -/*----------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:d0:93:00:01:cb -#define CONFIG_IPADDR 10.0.0.98 -#define CONFIG_SERVERIP 10.0.0.1 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000" /*----------------------------------------------------------------------*/ /* @@ -233,8 +227,8 @@ * RTCSC - Real-Time Clock Status and Control Register 11-27 *----------------------------------------------------------------------- */ -/* 0x00C2 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF) +/* 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- diff --git a/include/config_SM850.h b/include/config_SM850.h index f4bc572..e494158 100644 --- a/include/config_SM850.h +++ b/include/config_SM850.h @@ -172,6 +172,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/include/config_SPD823TS.h b/include/config_SPD823TS.h index 3fb80e2..fefacf9 100644 --- a/include/config_SPD823TS.h +++ b/include/config_SPD823TS.h @@ -225,8 +225,8 @@ * RTCSC - Real-Time Clock Status and Control Register *----------------------------------------------------------------------- */ -/* 0xc2 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF) +/* 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- diff --git a/include/config_TQM823L.h b/include/config_TQM823L.h index 35847a9..d606ce0 100644 --- a/include/config_TQM823L.h +++ b/include/config_TQM823L.h @@ -174,6 +174,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/include/config_TQM850L.h b/include/config_TQM850L.h index fdf0048..ae031de 100644 --- a/include/config_TQM850L.h +++ b/include/config_TQM850L.h @@ -176,6 +176,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/include/config_TQM855L.h b/include/config_TQM855L.h index c2735de..1eab77f 100644 --- a/include/config_TQM855L.h +++ b/include/config_TQM855L.h @@ -174,6 +174,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/include/config_TQM860L.h b/include/config_TQM860L.h index d453d7c..a70fdb5 100644 --- a/include/config_TQM860L.h +++ b/include/config_TQM860L.h @@ -174,6 +174,12 @@ */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- diff --git a/mpc8260/ether_fcc.c b/mpc8260/ether_fcc.c index c6223f0..e6d1bd6 100644 --- a/mpc8260/ether_fcc.c +++ b/mpc8260/ether_fcc.c @@ -1,417 +1,353 @@ /* - * - * File: scc.c - * Description: - * Basic ET HW initialization and packet RX/TX routines - * - * NOTES <<>>: - * 1) Specifically Designed to run on TQM823L/STK8xxL board. - * 2) Do not cache Rx/Tx buffers. - * - * - * History - * 8/13/99 saw Ported driver from MPC821/MPC821ADS (SCC1) - * 8/16/00 bor Ported driver from MPC823FADS board - * - */ - -/* - * MPC8260 FCC Fast Ethernet MII <-> PHY + * MPC8260 FCC Fast Ethernet + * + * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. * - * Cogent CMA282 CPU module - * ------------------------ - * Uses FCC2 with an LTX970 10/100 PHY + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * - * PB-22 --------> TXD0 - * PB-23 --------> TXD1 - * PB-24 --------> TXD2 - * PB-25 --------> TXD3 - * PB-31 <-------- TX_ER - * PB-29 --------> TX_EN - * PC-16 --------> TX_CLK - * PB-21 <-------- RXD0 - * PB-20 <-------- RXD1 - * PB-19 <-------- RXD2 - * PB-18 <-------- RXD3 - *... + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8260 FCC Fast Ethernet + * Basic ET HW initialization and packet RX/TX routines + * + * This code will not perform the IO port configuration. This should be + * done in the iop_conf_t structure specific for the board. + * + * TODO: + * add a PHY driver to do the negotiation + * reflect negotiation results in FPSMR + * look for ways to configure the board specific stuff elsewhere, eg. + * config_xxx.h or the board directory */ #include #include +#include #include #include +/*#include "mii_phy.h"*/ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) -#define BD_OFFSET 0x860 /* offset to begin of DPRAM + allocation for serial IF*/ +#if (CONFIG_ETHER_INDEX == 1) + +#define PROFF_ENET PROFF_FCC1 +#define CPM_CR_ENET_SBLOCK CPM_CR_FCC1_SBLOCK +#define CPM_CR_ENET_SBLOCK CPM_CR_FCC1_SBLOCK +#define CPM_CR_ENET_PAGE CPM_CR_FCC1_PAGE + +#elif (CONFIG_ETHER_INDEX == 2) + +#define PROFF_ENET PROFF_FCC2 +#define CPM_CR_ENET_SBLOCK CPM_CR_FCC2_SBLOCK +#define CPM_CR_ENET_PAGE CPM_CR_FCC2_PAGE +#if defined(CONFIG_RSD_PROTO) +/* + * Attention: this is board-specific + * - Rx-CLK is CLK14 + * - Tx-CLK is CLK15 + * - RAM for BD/Buffers is on the Local Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +#define CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CMXFCR_VALUE (CMXFCR_RF2CS_CLK14 | CMXFCR_TF2CS_CLK15) +#define CPMFCR_RAMTYPE (CPMFCR_BDB | CPMFCR_DTB) +#define FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +#elif (CONFIG_ETHER_INDEX == 3) -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 +#define PROFF_ENET PROFF_FCC3 +#define CPM_CR_ENET_SBLOCK CPM_CR_FCC3_SBLOCK +#define CPM_CR_ENET_PAGE CPM_CR_FCC3_PAGE -#define TX_BUF_CNT 2 +#else +#error "FCC Ethernet not correctly defined" +#endif + +/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ +#define PKT_MAXDMA_SIZE 1520 + +/* The FCC stores dest/src/type, data, and checksum for receive packets. */ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 + +/* Maximum input buffer size. Must be a multiple of 32. */ +#define PKT_MAXBLR_SIZE 1536 #define TOUT_LOOP 1000000 -/* static char rxbuf[PKTBUFSRX][ DBUF_LENGTH ]; */ -static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; +#define TX_BUF_CNT 2 +#ifdef __GNUC__ +static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8))); +#else +#error "txbuf must be 64-bit aligned" +#endif static uint rxIdx; /* index of the current RX buffer */ static uint txIdx; /* index of the current TX buffer */ /* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; + * FCC Ethernet Tx and Rx buffer descriptors. + * Provide for Double Buffering + * Note: PKTBUFSRX is defined in net.h + */ -static RTXBD *rtx; +typedef volatile struct rtxbd { + cbd_t rxbd[PKTBUFSRX]; + cbd_t txbd[TX_BUF_CNT]; +} RTXBD; +/* Good news: the FCC supports external BDs! */ +#ifdef __GNUC__ +static RTXBD rtx __attribute__ ((aligned(8))); +#else +#error "rtx must be 64-bit aligned" +#endif int eth_send(volatile void *packet, int length) { - int i, j=0; -#if 0 - volatile char *in, *out; -#endif + int i; + int result = 0; - /* section 16.9.23.3 - * Wait for ready - */ -#if 0 - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); - out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); - in = packet; - for(i = 0; i < length; i++) { - *out++ = *in++; + if (length <= 0) { + printf("fec: bad packet size: %d\n", length); + goto out; + } + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + printf("fec: tx buffer not ready\n"); + goto out; } - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; + } -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; + rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx.txbd[txIdx].cbd_datlen = length; + rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | + BD_ENET_TX_WRAP); - /* wrap around buffer index when necessary */ - if (txIdx >= TX_BUF_CNT) txIdx = 0; -#endif + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + printf("fec: tx error\n"); + goto out; + } + } - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX timeout\n"); #ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); + printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc); #endif - i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - return i; + + /* return only status bits */ + result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; + +out: + return result; } int eth_rx(void) { - int length; - - for (;;) - { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } + int length; - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) - { -#ifdef ET_DEBUG - printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); -#endif + for (;;) + { + if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ } - else - { - /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); + length = rtx.rxbd[rxIdx].cbd_datlen; + + if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { + printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - + else { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the FCC. */ + rtx.rxbd[rxIdx].cbd_datlen = 0; + /* wrap around buffer index when necessary */ if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; + rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; + rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; } - } - return length; + } + return length; } -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ int eth_init(bd_t *bis) { - int i; - scc_enet_t *pram_ptr; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile cpm8260_t *cp = &(immr->im_cpm); + fcc_enet_t *pram_ptr; + unsigned long mem_addr; -#if defined(CONFIG_FADS) - *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP|BCSR4_MODEM_EN); - *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL|BCSR4_DATA_VOICE; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#if 0 + mii_discover_phy(); #endif - - pram_ptr = (scc_enet_t *)&(immr->im_cpm.cp_dparam[PROFF_ENET]); - + + /* 28.9 - (1-2): ioports have been set up already */ + + /* 28.9 - (3): connect FCC's tx and rx clocks */ + immr->im_cpmux.cmx_uar = 0; + immr->im_cpmux.cmx_fcr &= ~CMXFCR_MASK; + immr->im_cpmux.cmx_fcr |= CMXFCR_VALUE; + + /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr = + FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + + /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fpsmr = FCC_PSMR | FCC_PSMR_ENCRC; + + /* 28.9 - (6): FDSR: Ethernet Syn */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fdsr = 0xD555; + + /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ rxIdx = 0; txIdx = 0; - /* assign static pointer to BD area */ - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + BD_OFFSET); - - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - + /* Setup Receiver Buffer Descriptors */ for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx.rxbd[i].cbd_datlen = 0; + rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; } + rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - + /* Setup Ethernet Transmitter Buffer Descriptors */ for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; + rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); + rtx.txbd[i].cbd_datlen = 0; + rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; } + rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ + /* 28.9 - (7): initialise parameter ram */ + pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* clear whole structure to make sure all reserved fields are zero */ + memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) + /* + * common Parameter RAM area + * + * Allocate space in the reserved FCC area of DPRAM for the + * internal buffers. No one uses this space (yet), so we + * can do this. Later, we will add resource management for + * this area. */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - -#define ea bis->bi_enetaddr - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - + mem_addr = CPM_FCC_SPECIAL_BASE + ((CONFIG_ETHER_INDEX-1) * 64); + pram_ptr->fen_genfcc.fcc_riptr = mem_addr; + pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; /* - * Enter Command: Initialize Tx Params for SCC + * Set maximum bytes per receive buffer. + * It must be a multiple of 32. */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Clear Events in SCCE -- Clear bits by writing 1's + pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; + pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | + CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); + pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | + CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); + + /* protocol-specific area */ + pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ + pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ + pram_ptr->fen_retlim = 15; /* Retry limit threshold */ + pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ + /* + * Set Ethernet station address. + * + * This is supplied in the board information structure, so we + * copy that into the controller. + * So, far we have only been given one Ethernet address. We make + * it unique by setting a few bits in the upper byte of the + * non-static part of the address. */ +#define ea bis->bi_enetaddr + pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ + /* pad pointer. use tiptr since we don't need a specific padding char */ + pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; + pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */ + pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */ + pram_ptr->fen_rfthr = 1; + pram_ptr->fen_rfcnt = 1; +#if 0 + printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n", pram_ptr->fen_genfcc.fcc_rbase); + printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n", pram_ptr->fen_genfcc.fcc_tbase); +#endif + + /* 28.9 - (8): clear out events in FCCE */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fcce = ~0x0; - immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); - - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \ - SCC_GSMRL_TPL_48 | \ - SCC_GSMRL_TPP_10 | \ - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packetsregardless of dest. MAC adress - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22 - /* | SCC_PMSR_BRO | SCC_PMSR_PRO */); - - /* - * Configure Ethernet TENA Signal - */ + /* 28.9 - (9): FCCM: mask all events */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fccm = 0; -#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) - immr->im_ioport.iop_pcpar |= PC_ENET_TENA; - immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) - immr->im_cpm.cp_pbpar |= PB_ENET_TENA; - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; -#else -#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif + /* 28.9 - (10-12): we don't use ethernet interrupts */ - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive + /* 28.9 - (13) + * + * Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. */ + cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, + CPM_CR_ENET_SBLOCK, + 0x0c, + CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + /* 28.9 - (14): enable tx/rx in gfmr */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; return 1; } - - void eth_halt(void) { volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} -#if 0 -void restart(void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + /* write GFMR: disable tx/rx */ + immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr &= + ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } -#endif #endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET */ diff --git a/mpc8xx/serial.c b/mpc8xx/serial.c index 1f249d2..60bf26c 100644 --- a/mpc8xx/serial.c +++ b/mpc8xx/serial.c @@ -282,14 +282,6 @@ serial_putc(const char c) #endif } -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - int serial_getc(void) { @@ -340,7 +332,7 @@ serial_init (ulong cpu_clock, int baudrate) volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; + uint dpaddr, dpsize, size; volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); /* initialize pointers to SCC */ @@ -361,12 +353,10 @@ serial_init (ulong cpu_clock, int baudrate) ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data */ - dpaddr = 0x800; + dpaddr = CPM_DATAONLY_BASE; + dpsize = CPM_DATAONLY_SIZE; /* Set the physical address of the host memory buffers in * the buffer descriptors. @@ -386,21 +376,45 @@ serial_init (ulong cpu_clock, int baudrate) up->scc_genscc.scc_rfcr = SCC_EB; up->scc_genscc.scc_tfcr = SCC_EB; + /* Updating dpram address and size + */ + size = ((sizeof(cbd_t)*2 + 2) + 15) & ~15; + dpaddr += size; + dpsize -= size; + + /* Initialize CPM + */ + m8xx_cpm_init(dpaddr, dpsize); /* Set SCC(x) clock mode to 16x * Set up the baud rate generator. * See 8xx_io/commproc.c for details. * - * Wire BRG1 to SCC + * Wire BRGn to SCCn */ /* Set up the baud rate generator. */ sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - cp->cp_simode = SICR_UART_CLKRT; + +#if defined(CONFIG_8xx_CONS_SCC1) + cp->cp_sicr |= (SICR_RCLK_SCC1_BRG1 | SICR_TCLK_SCC1_BRG1); cp->cp_brgc1 = ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN; +#elif defined(CONFIG_8xx_CONS_SCC2) + cp->cp_sicr |= (SICR_RCLK_SCC2_BRG2 | SICR_TCLK_SCC2_BRG2); + cp->cp_brgc2 = + ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN; +#elif defined(CONFIG_8xx_CONS_SCC3) + cp->cp_sicr |= (SICR_RCLK_SCC3_BRG3 | SICR_TCLK_SCC3_BRG3); + cp->cp_brgc3 = + ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN; +#elif defined(CONFIG_8xx_CONS_SCC4) + cp->cp_sicr |= (SICR_RCLK_SCC4_BRG4 | SICR_TCLK_SCC4_BRG4); + cp->cp_brgc4 = + ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN; +#endif /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. @@ -476,14 +490,6 @@ serial_putc(const char c) #endif } -void -serial_putstr (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - int serial_getc(void) { @@ -527,19 +533,32 @@ serial_tstc() #endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */ +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init(void) { -#ifdef CONFIG_8xx_CONS_SMC1 +#if defined(CONFIG_8xx_CONS_SMC1) serial_printf("[on SMC1] "); -#endif -#ifdef CONFIG_8xx_CONS_SMC2 +#elif defined(CONFIG_8xx_CONS_SMC2) serial_printf("[on SMC2] "); -#endif -#ifdef CONFIG_8xx_CONS_SCC3 - printf("[on SCC3] "); +#elif defined(CONFIG_8xx_CONS_SCC1) + serial_printf("[on SCC1] "); +#elif defined(CONFIG_8xx_CONS_SCC2) + serial_printf("[on SCC2] "); +#elif defined(CONFIG_8xx_CONS_SCC3) + serial_printf("[on SCC3] "); +#elif defined(CONFIG_8xx_CONS_SCC4) + serial_printf("[on SCC4] "); #endif }