From: Fei Shao Date: Mon, 14 Oct 2024 11:09:26 +0000 (+0800) Subject: arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=e9e2a88663142d31977842568abf96a9c759f3b0;p=users%2Fjedix%2Flinux-maple.git arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao Link: https://lore.kernel.org/r/20241014111053.2294519-5-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 8c15002498e0..e1b984457cc0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2198,6 +2198,64 @@ #clock-cells = <1>; }; + video_decoder: video-decoder@18000000 { + compatible = "mediatek,mt8188-vcodec-dec"; + reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + mediatek,scp = <&scp>; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names = "sel", "vdec", "lat", "top"; + interrupts = ; + iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names = "sel", "vdec", "lat", "top"; + interrupts = ; + iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + larb23: smi@1800d000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1800d000 0 0x1000>; @@ -2249,6 +2307,31 @@ mediatek,smi = <&vdo_smi_common>; }; + video_encoder: video-encoder@1a020000 { + compatible = "mediatek,mt8188-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks = <&vencsys CLK_VENC1_VENC>; + clock-names = "venc_sel"; + interrupts = ; + iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,scp = <&scp>; + }; + disp_dsi0: dsi@1c008000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c008000 0 0x1000>;