From: Marc Zyngier Date: Fri, 21 Apr 2023 13:05:17 +0000 (+0100) Subject: Merge branch irq/riscv-ipi into irq/irqchip-next X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=e7b5771aa08746c13bb03ebe0a5053df1498c328;p=linux.git Merge branch irq/riscv-ipi into irq/irqchip-next * irq/riscv-ipi: : . : RISC-V IPI rework from Anup Patel: : : "This series aims to improve IPI support in Linux RISC-V in following ways: : 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V : specific hooks. This also makes Linux RISC-V IPI support aligned with : other architectures. : 2) Remote TLB flushes and icache flushes should prefer local IPIs instead : of SBI calls whenever we have specialized hardware (such as RISC-V AIA : IMSIC and RISC-V SWI) which allows S-mode software to directly inject : IPIs without any assistance from M-mode runtime firmware." : . irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers RISC-V: Use IPIs for remote icache flush when possible RISC-V: Use IPIs for remote TLB flush when possible RISC-V: Allow marking IPIs as suitable for remote FENCEs RISC-V: Treat IPIs as normal Linux IRQs irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode RISC-V: Clear SIP bit only when using SBI IPI operations Signed-off-by: Marc Zyngier --- e7b5771aa08746c13bb03ebe0a5053df1498c328