From: Bernard Zhao <bernard@vivo.com>
Date: Thu, 7 May 2020 11:45:14 +0000 (-0700)
Subject: memory: samsung: exynos5422-dmc: Fix tFAW timings alignment
X-Git-Tag: v5.7.5~51
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=e72001050c811d7f4a2ed51423c638c693d33bed;p=users%2Fdwmw2%2Flinux.git

memory: samsung: exynos5422-dmc: Fix tFAW timings alignment

commit 4bff7214d263b5235263136cb53147a759b3f3ab upstream.

Aligning of tFAW timing with standard was using wrong argument as
minimum acceptable value.  This could lead to wrong timing if provided
timings and clock period do not match the standard.

Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422")
Cc: <stable@vger.kernel.org>
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 81a1b1d016836..22a43d6628336 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -1091,7 +1091,7 @@ static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
 	/* power related timings */
 	val = dmc->timings->tFAW / clk_period_ps;
 	val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
-	val = max(val, dmc->min_tck->tXP);
+	val = max(val, dmc->min_tck->tFAW);
 	reg = &timing_power[0];
 	*reg_timing_power |= TIMING_VAL2REG(reg, val);