From: wdenk <wdenk>
Date: Fri, 16 Aug 2002 14:21:50 +0000 (+0000)
Subject: * Patch by Scott McNutt,, 14 Aug 2002:
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=e5aa5a30ce26780c3247dda29b71f8aac6faa243;p=users%2Frw%2Fppcboot.git

* Patch by Scott McNutt,, 14 Aug 2002:
  IBM 440GP Ethernet support

* Patch by Kenneth Johansson, 14 Aug 2002:
  use define in place of hard coded value in cpu/ppc4xx/spd_sdram.c

* Patch by Kenneth Johansson, 14 Aug 2002:
  remove broken RAM size test from cpu/ppc4xx/spd_sdram.c

* Patch by Jun Gu, 15 Aug 2002:
  support different DIP switch settings and large flash and SRAM
---

diff --git a/CHANGELOG b/CHANGELOG
index 3b4b681..0f9da78 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,18 @@
 Modifications for 1.2.0:
 ======================================================================
 
+* Patch by Scott McNutt,, 14 Aug 2002:
+  IBM 440GP Ethernet support
+
+* Patch by Kenneth Johansson, 14 Aug 2002:
+  use define in place of hard coded value in cpu/ppc4xx/spd_sdram.c
+
+* Patch by Kenneth Johansson, 14 Aug 2002:
+  remove broken RAM size test from cpu/ppc4xx/spd_sdram.c
+
+* Patch by Jun Gu, 15 Aug 2002:
+  support different DIP switch settings and large flash and SRAM
+
 * More changes for ARMBoot merge;
   include ARMBoot patch by Kyle Harris, 14 Aug 2002:
   - Add Xscale support, add support for lubbock and cradle boards
diff --git a/board/ebony/ebony.c b/board/ebony/ebony.c
index 674d7ed..9b6f2c0 100644
--- a/board/ebony/ebony.c
+++ b/board/ebony/ebony.c
@@ -25,47 +25,67 @@
 #include "ebony.h"
 #include <asm/processor.h>
 
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
 
-long int fixed_sdram( void );
+long int fixed_sdram (void);
 
 int board_pre_init (void)
 {
 	uint reg;
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char status;
+
 
 	/*--------------------------------------------------------------------
 	 * Setup the external bus controller/chip selects
 	 *-------------------------------------------------------------------*/
-	mtdcr( ebccfga, xbcfg );
-	reg = mfdcr( ebccfgd );
-	mtdcr( ebccfgd, reg | 0x04000000 );	/* Set ATC */
-
-	mtebc( pb0ap, 0x9b015480 );	/* FLASH/SRAM */
-	mtebc( pb0cr, 0xfff18000 ); /* BAS=0xfff 1MB R/W 8-bit */
-	mtebc( pb1ap, 0x02815480 );	/* NVRAM/RTC */
-	mtebc( pb1cr, 0x48018000 ); /* BA=0x480 1MB R/W 8-bit */
-	mtebc( pb2ap, 0x9b015480 );	/* 4MB FLASH */
-	mtebc( pb2cr, 0xff858000 ); /* BAS=0xff8 4MB R/W 8-bit */
-	mtebc( pb7ap, 0x01015280 );	/* FPGA registers */
-	mtebc( pb7cr, 0x48318000 ); /* BA=0x483 1MB R/W 8-bit */
+	mtdcr (ebccfga, xbcfg);
+	reg = mfdcr (ebccfgd);
+	mtdcr (ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	mtebc (pb1ap, 0x02815480);	/* NVRAM/RTC */
+	mtebc (pb1cr, 0x48018000);	/* BA=0x480 1MB R/W 8-bit */
+	mtebc (pb7ap, 0x01015280);	/* FPGA registers */
+	mtebc (pb7cr, 0x48318000);	/* BA=0x483 1MB R/W 8-bit */
+
+	/* read FPGA_REG0  and set the bus controller */
+	status = *fpga_base;
+	if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
+		mtebc (pb0ap, 0x9b015480);	/* FLASH/SRAM */
+		mtebc (pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+		mtebc (pb2ap, 0x9b015480);	/* 4MB FLASH */
+		mtebc (pb2cr, 0xff858000);	/* BAS=0xff8 4MB R/W 8-bit */
+	} else {
+		mtebc (pb0ap, 0x9b015480);	/* 4MB FLASH */
+		mtebc (pb0cr, 0xffc58000);	/* BAS=0xffc 4MB R/W 8-bit */
+
+		/* set CS2 if FLASH_ONBD_N == 0 */
+		if (!(status & FLASH_ONBD_N)) {
+			mtebc (pb2ap, 0x9b015480);	/* FLASH/SRAM */
+			mtebc (pb2cr, 0xff818000);	/* BAS=0xff8 4MB R/W 8-bit */
+		}
+	}
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr( uic0sr, 0xffffffff );    /* clear all */
-	mtdcr( uic0er, 0x00000000 );    /* disable all */
-	mtdcr( uic0cr, 0x00000009 );    /* SMI & UIC1 crit are critical */
-	mtdcr( uic0pr, 0xfffffe13 );    /* per ref-board manual */
-	mtdcr( uic0tr, 0x01c00008 );    /* per ref-board manual */
-	mtdcr( uic0vr, 0x00000001 );    /* int31 highest, base=0x000 */
-	mtdcr( uic0sr, 0xffffffff );    /* clear all */
-    
-	mtdcr( uic1sr, 0xffffffff );    /* clear all */
-	mtdcr( uic1er, 0x00000000 );    /* disable all */
-	mtdcr( uic1cr, 0x00000000 );    /* all non-critical */
-	mtdcr( uic1pr, 0xffffe0ff );    /* per ref-board manual */
-	mtdcr( uic1tr, 0x00ffc000 );    /* per ref-board manual */
-	mtdcr( uic1vr, 0x00000001 );    /* int31 highest, base=0x000 */
-	mtdcr( uic1sr, 0xffffffff );    /* clear all */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	return 0;
 }
@@ -75,57 +95,55 @@ int board_pre_init (void)
 int checkboard (void)
 {
 	sys_info_t sysinfo;
-	get_sys_info(&sysinfo);
-
-	printf("IBM 440GP Evaluation Board (Ebony)\n");
-	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
-	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
-	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
-	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
-	printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
+
+	get_sys_info (&sysinfo);
+
+	printf ("IBM 440GP Evaluation Board (Ebony)\n");
+	printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 	return (0);
 }
 
 
 long int initdram (int board_type)
 {
-	long    dram_size = 0;
+	long dram_size = 0;
+
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram();
+	dram_size = spd_sdram ();
 #else
-	dram_size = fixed_sdram();
+	dram_size = fixed_sdram ();
 #endif
 	return dram_size;
 }
 
 
 #if defined(CFG_DRAM_TEST)
-int testdram(void)
+int testdram (void)
 {
-	uint    *pstart = (uint *)0x00000000;
-	uint    *pend   = (uint *)0x08000000;
-	uint    *p;
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
 
-	for( p = pstart; p < pend; p++ )
+	for (p = pstart; p < pend; p++)
 		*p = 0xaaaaaaaa;
 
-	for( p = pstart; p < pend; p++ )
-	{
-		if( *p != 0xaaaaaaaa )
-		{
-			printf("SDRAM test fails at: %08x\n", (uint)p );
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
 			return 1;
 		}
 	}
 
-	for( p = pstart; p < pend; p++ )
+	for (p = pstart; p < pend; p++)
 		*p = 0x55555555;
 
-	for( p = pstart; p < pend; p++ )
-	{
-		if( *p != 0x55555555 )
-		{
-			printf("SDRAM test fails at: %08x\n", (uint)p );
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
 			return 1;
 		}
 	}
@@ -141,17 +159,18 @@ int testdram(void)
  *              PLB @ 133 MHz
  *
  ************************************************************************/
-long int fixed_sdram( void )
+long int fixed_sdram (void)
 {
-	uint    reg;
+	uint reg;
+
 	/*--------------------------------------------------------------------
 	 * Setup some default
 	 *------------------------------------------------------------------*/
-	mtsdram( mem_uabba, 0x00000000 );   /* ubba=0 (default)             */
-	mtsdram( mem_slio,  0x00000000 );   /* rdre=0 wrre=0 rarw=0         */
-	mtsdram( mem_devopt,0x00000000 );   /* dll=0 ds=0 (normal)          */
-	mtsdram( mem_wddctr,0x00000000 );   /* wrcp=0 dcd=0                 */
-	mtsdram( mem_clktr, 0x40000000 );   /* clkp=1 (90 deg wr) dcdt=0    */
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0                 */
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
 
 	/*--------------------------------------------------------------------
 	 * Setup for board-specific specific mem
@@ -159,25 +178,24 @@ long int fixed_sdram( void )
 	/*
 	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 	 */
-	mtsdram( mem_b0cr, 0x000a4001 );/* SDBA=0x000 128MB, Mode 3, enabled*/
-	mtsdram( mem_tr0,  0x410a4012 );/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	mtsdram (mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 	/* RA=10 RD=3                       */
-	mtsdram( mem_tr1,  0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
-	mtsdram( mem_rtr,  0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB     */
-	mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM    */
-	udelay( 400 );                  /* Delay 200 usecs (min)            */
-    
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram (mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)            */
+
 	/*--------------------------------------------------------------------
 	 * Enable the controller, then wait for DCEN to complete
 	 *------------------------------------------------------------------*/
-	mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit           */
-	for(;;)
-	{
-		mfsdram( mem_mcsts, reg );
-		if( reg & 0x80000000 )
+	mtsdram (mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
 			break;
 	}
-    
-	return( 128 * 1024 * 1024 );    /* 128 MB                           */
+
+	return (128 * 1024 * 1024);	/* 128 MB                           */
 }
-#endif /* !defined(CONFIG_SPD_EEPROM) */
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/ebony/init.S b/board/ebony/init.S
index 8c9d6be..d7b7515 100644
--- a/board/ebony/init.S
+++ b/board/ebony/init.S
@@ -90,7 +90,7 @@ tlbtab:
     tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)    
     tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
     tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
     tlbtab_end
     
 
diff --git a/common/Makefile b/common/Makefile
index a90403f..a29a891 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -38,6 +38,10 @@ COBJS	= main.o command.o environment.o bedbug.o \
 	  flash.o hush.o kgdb.o lists.o \
 	  miiphybb.o miiphyutil.o s_record.o \
 	  usb.o usb_kbd.o usb_storage.o soft_i2c.o
+# Temporary hack to get ARM working quickly
+ifeq ($(ARCH),ppc)
+COBJS  += cmd_nvedit.o
+endif
 
 OBJS	= $(AOBJS) $(COBJS)
 
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 38c49a8..0703b0c 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -29,7 +29,7 @@
 #include <ppcboot.h>
 #include <miiphy.h>
 
-#ifdef CONFIG_MII
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 
 /*****************************************************************************
  *
@@ -169,4 +169,4 @@ int miiphy_duplex (unsigned char addr)
 	}
 }
 
-#endif							/* CONFIG_MII */
+#endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index dd22679..54de5ff 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -427,7 +427,7 @@ void restart(void)
 }
 #endif
 
-#ifdef CFG_DISCOVER_PHY
+#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
 
 static	int	phyaddr = -1;	/* didn't find a PHY yet */
 static	uint	phytype;
@@ -488,7 +488,9 @@ mii_send(uint mii_cmd)
 #endif
 	return (mii_reply & 0xffff);		/* data read from phy */
 }
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
 
+#if defined(CFG_DISCOVER_PHY)
 static void
 mii_discover_phy(void)
 {
@@ -550,7 +552,7 @@ mii_discover_phy(void)
 		printf("No PHY device found.\n");
 	}
 }
-#endif
+#endif	/* CFG_DISCOVER_PHY */
 
 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
 
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index 3a38b70..dd0a04f 100644
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -251,6 +251,11 @@ int eth_init (bd_t * bis)
 	tx_i_index = 0;			/* Transmit Interrupt Queue Index */
 	tx_u_index = 0;			/* Transmit User Queue Index */
 
+#if defined(CONFIG_440) 
+        /* set RMII mode */
+        out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+#endif /* CONFIG_440 */
+
 	/* EMAC RESET */
 	out32 (EMAC_M0, EMAC_M0_SRST);
 
@@ -412,8 +417,15 @@ int eth_init (bd_t * bis)
 	/* set transmit request threshold register */
 	out32 (EMAC_TRTR, 0x18000000);	/* 256 byte threshold */
 
-	/* set recieve  low/high water mark register */
+	/* set receive  low/high water mark register */
+#if defined(CONFIG_440)
+	/* 440GP has a 64 byte burst length */
+        out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
+        out32 (EMAC_TXM1,           0xf8640000);
+#else /* CONFIG_440 */
+	/* 405s have a 16 byte burst length */
 	out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
+#endif /* CONFIG_440 */
 
 	/* Frame gap set */
 	out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
@@ -497,6 +509,7 @@ int eth_send (volatile void *ptr, int len)
 	tx[tx_slot].data_len = (short) len;
 	tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
 
+    __asm__ volatile ("eieio");
 	out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
 #ifdef INFO_405_ENET
 	packetSent++;
@@ -525,6 +538,83 @@ int eth_send (volatile void *ptr, int len)
 }
 
 
+#if defined(CONFIG_440)
+/*-----------------------------------------------------------------------------+
+| EnetInt.
+| EnetInt is the interrupt handler.  It will determine the
+| cause of the interrupt and call the apporpriate servive
+| routine.
++-----------------------------------------------------------------------------*/
+int enetInt ()
+{
+	int serviced;
+	int rc = -1;				/* default to not us */
+	unsigned long mal_isr;
+	unsigned long emac_isr = 0;
+	unsigned long mal_rx_eob;
+	unsigned long my_uic0msr, my_uic1msr;
+
+	/* enter loop that stays in interrupt code until nothing to service */
+	do {
+		serviced = 0;
+
+		my_uic0msr = mfdcr (uic0msr);
+		my_uic1msr = mfdcr (uic1msr);
+
+		if (!(my_uic0msr & UIC_MRE)
+                    && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+                        /* not for us */
+			return (rc);
+		}
+
+		/* get and clear controller status interrupts */
+		/* look at Mal and EMAC interrupts */
+		if ((my_uic0msr & UIC_MRE)
+                    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+                        /* we have a MAL interrupt */
+			mal_isr = mfdcr (malesr);
+			/* look for mal error */
+			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
+				mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
+				serviced = 1;
+				rc = 0;
+			}
+		}
+		if (UIC_ETH0 & my_uic1msr) {	/* look for EMAC errors */
+			emac_isr = in32 (EMAC_ISR);
+			if ((emac_ier & emac_isr) != 0) {
+				emac_err (emac_isr);
+				serviced = 1;
+				rc = 0;
+			}
+		}
+		if ((emac_ier & emac_isr)
+                    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+			mtdcr (uic0sr, UIC_MRE); /* Clear */
+			mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+			return (rc);		/* we had errors so get out */
+		}
+
+		/* handle MAL RX EOB  interupt from a receive */
+		/* check for EOB on valid channels            */
+		if (my_uic0msr & UIC_MRE) {
+			mal_rx_eob = mfdcr (malrxeobisr);
+			if ((mal_rx_eob & 0x80000000) != 0) {	/* call emac routine for channel 0 */
+				/* clear EOB
+				   mtdcr(malrxeobisr, mal_rx_eob); */
+				enet_rcv (emac_isr);
+				/* indicate that we serviced an interrupt */
+				serviced = 1;
+				rc = 0;
+			}
+		}
+                mtdcr (uic0sr, UIC_MRE); /* Clear */
+                mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+	} while (serviced);
+
+	return (rc);
+}
+#else /* CONFIG_440 */
 /*-----------------------------------------------------------------------------+
  * EnetInt.
  * EnetInt is the interrupt handler.  It will determine the
@@ -594,6 +684,7 @@ int enetInt ()
 
 	return (rc);
 }
+#endif /* CONFIG_440 */
 
 /*-----------------------------------------------------------------------------+
  *  MAL Error Routine
@@ -607,7 +698,7 @@ void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
 	mtdcr (maltxdeir, 0xC0000000);
 	mtdcr (malrxdeir, 0x80000000);
 
-#if 0	/*sr */
+#if 1	/*sr */
 	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx  MAL_DEF = %lx  MAL_ERR= %lx \n",
 		isr, uic, maldef, mal_errr);
 #else
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index c31991d..2a74e6e 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -285,7 +285,7 @@ long int spd_sdram(void)
    	}		
 			
 /*------------------------------------------------------------------
-	calculate total size and do sanity check
+	calculate total size 
   -------------------------------------------------------------------*/    
 	/* calculate total size and do sanity check */
 	tmp = spd_read(31);
@@ -297,13 +297,6 @@ long int spd_sdram(void)
 	    tmp = tmp>>1;
 	    }
 	total_size *= spd_read(5);	/* mult by module rows (dimm sides) */
-	/* now compute Total size based on address bits */
-	tmp = 1 << (row+col);		/* convert rows and cols to size */
-	tmp *= spd_read(6)/8;		/* mult by bus width in bytes */
-	tmp *= spd_read(17);		/* mult by internal banks */
-	/* see if the two methods of calculating size agree */
-	if ( tmp != total_size)
-	    SPD_ERR("SDRAM - conflicting module memory size\n");
 		
 /*------------------------------------------------------------------
 	map  rows * cols * banks to a mode 
@@ -438,7 +431,7 @@ int spd_read(uint addr)
 {
 	char data[2];
 
-	if (i2c_read(0x50, addr, 1, data, 1) == 0)
+	if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 		return (int)data[0];
 	else
 		return 0;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 2b96d2a..7e17770 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -191,9 +191,14 @@ _start_440:
 	* (see errata 1.12: 440_33)
 	*/
 	lis	r1,0x0030	/* store gathering & broadcast disable */
-	ori	r1,r1,0x6100	/* cache touch & force load/store align */
+	ori	r1,r1,0x6000	/* cache touch */
 	mtspr	ccr0,r1
 
+	/* set up interrupt vectors */
+	mtspr	ivpr,r0
+	li	r1,0x500
+	mtspr	ivor4,r1
+	
 	/*----------------------------------------------------------------*/
 	/* Configure cache regions  */
 	/*----------------------------------------------------------------*/
diff --git a/include/405gp_enet.h b/include/405gp_enet.h
index 5881aed..582caf2 100644
--- a/include/405gp_enet.h
+++ b/include/405gp_enet.h
@@ -65,6 +65,16 @@ struct arp_entry {
 
 
 			/*Register addresses */
+#if defined(CONFIG_440)
+#define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII_FER			(ZMII_BASE)
+#define ZMII_SSR			(ZMII_BASE + 4)
+#define ZMII_SMIISR			(ZMII_BASE + 8)
+
+#define ZMII_RMII			0x22000000
+#define ZMII_MDI0			0x80000000
+#endif /* CONFIG_440 */
+
 #if defined(CONFIG_440)
 #define EMAC_BASE 			(CFG_PERIPHERAL_BASE + 0x0800)
 #else
diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h
index 2a8ab16..b65a766 100644
--- a/include/asm-arm/string.h
+++ b/include/asm-arm/string.h
@@ -25,6 +25,7 @@ extern void * memchr(const void *, int, __kernel_size_t);
 #define __HAVE_ARCH_MEMSET
 extern void * memset(void *, int, __kernel_size_t);
 
+#if 0
 extern void __memzero(void *ptr, __kernel_size_t n);
 
 #define memset(p,v,n)							\
@@ -39,5 +40,8 @@ extern void __memzero(void *ptr, __kernel_size_t n);
 	})
 
 #define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
 
 #endif
diff --git a/include/configs/EBONY.h b/include/configs/EBONY.h
index ee6cbd6..a6ed5cc 100644
--- a/include/configs/EBONY.h
+++ b/include/configs/EBONY.h
@@ -115,7 +115,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define	CONFIG_PHY_ADDR		8	/* PHY address			*/
 
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index e6c74b0..b96c287 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -263,6 +263,11 @@
 					/* 16 byte page write mode using*/
 					/* last	4 bits of the address	*/
 #define CFG_I2C_MULTI_EEPROMS
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 9be8cdb..a2bda6e 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -264,7 +264,11 @@
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_I2C_MULTI_EEPROMS
-
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/ppcboot.h b/include/ppcboot.h
index bbb1010..9b62659 100644
--- a/include/ppcboot.h
+++ b/include/ppcboot.h
@@ -231,12 +231,12 @@ extern ulong load_addr;		/* Default Load Address	*/
 
 #ifdef CONFIG_PPC		/* ARM version in armboot.h - to be fixed! */
 /* common/cmd_nvedit.c */
-void	env_init (init_data_t *);
+void	env_init     (init_data_t *);
 void	env_relocate (ulong);
-char 	*getenv (uchar *);
-int      getenv_r (uchar *name, uchar *buf, unsigned len);
-int	saveenv(void);
-void inline  setenv (char *, char *);
+char 	*getenv      (uchar *);
+int	getenv_r     (uchar *name, uchar *buf, unsigned len);
+int	saveenv      (void);
+void inline setenv   (char *, char *);
 #endif /* CONFIG_PPC */
 
 #if defined(CONFIG_PCI)		|| \