From: David Woodhouse Date: Fri, 2 Feb 2018 18:59:51 +0000 (-0500) Subject: x86/cpufeatures: Clean up Spectre v2 related CPUID flags X-Git-Tag: v4.1.12-124.31.3~1150 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=e38ba7f028de689157b840a8e97bd560f9e9a2b3;p=users%2Fjedix%2Flinux-maple.git x86/cpufeatures: Clean up Spectre v2 related CPUID flags We want to expose the hardware features simply in /proc/cpuinfo as "ibrs", "ibpb" and "stibp". Since AMD has separate CPUID bits for those, use them as the user-visible bits. When the Intel SPEC_CTRL bit is set which indicates both IBRS and IBPB capability, set those (AMD) bits accordingly. Likewise if the Intel STIBP bit is set, set the AMD STIBP that's used for the generic hardware capability. Hide the rest from /proc/cpuinfo by putting "" in the comments. Including RETPOLINE and RETPOLINE_AMD which shouldn't be visible there. There are patches to make the sysfs vulnerabilities information non-readable by non-root, and the same should apply to all information about which mitigations are actually in use. Those *shouldn't* appear in /proc/cpuinfo. The feature bit for whether IBPB is actually used, which is needed for ALTERNATIVEs, is renamed to X86_FEATURE_USE_IBPB. Originally-by: Borislav Petkov Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner Cc: ak@linux.intel.com Cc: dave.hansen@intel.com Cc: karahmed@amazon.de Cc: arjan@linux.intel.com Cc: torvalds@linux-foundation.org Cc: peterz@infradead.org Cc: bp@alien8.de Cc: pbonzini@redhat.com Cc: tim.c.chen@linux.intel.com Cc: gregkh@linux-foundation.org Link: https://lkml.kernel.org/r/1517070274-12128-2-git-send-email-dwmw@amazon.co.uk (cherry picked from commit 2961298efe1ea1b6fc0d7ee8b76018fa6c0bcef2) Orabug: 27477743 CVE: CVE-2017-5715 Signed-off-by: Konrad Rzeszutek Wilk Conflicts: arch/x86/include/asm/cpufeatures.h arch/x86/kernel/cpu/bugs.c arch/x86/kernel/cpu/intel.c [Backport: The majority of the changes are to make 'retpoline' and friends not show up. Also fix so that instead of 'spec_ctrl' we have 'ibrs'. The rest we had already] Reviewed-by: Pavel Tatashin Reviewed-by: Darren Kenny --- diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 6016dbbd7be3..316b14fd0416 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -197,8 +197,8 @@ #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ -#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ -#define X86_FEATURE_SPEC_CTRL ( 7*32+20) /* Control Speculation Control */ +#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ +#define X86_FEATURE_IBRS ( 7*32+20) /* Control Speculation Control */ #define X86_FEATURE_STIPB ( 7*32+21) /* Single Thread Indirect Branch Predictors */ #define X86_FEATURE_IA32_ARCH_CAPS ( 7*32+22) /* Control Speculation Control */ #define X86_FEATURE_IBRS_ATT ( 7*32+23) /* IBRS all the time */ @@ -210,8 +210,8 @@ #define X86_FEATURE_VMEXIT_RSB_FULL (7*32+27) /* "" Whether to stuff the RSB on VMEXIT. */ #define X86_FEATURE_STUFF_RSB (7*32+28) /* "" Whether to stuff the RSB (usually dependent on !SMEP) */ -#define X86_FEATURE_RETPOLINE ( 7*32+29) /* Generic Retpoline mitigation for Spectre variant 2 */ -#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* AMD Retpoline mitigation for Spectre variant 2 */ +#define X86_FEATURE_RETPOLINE ( 7*32+29) /* "" Generic Retpoline mitigation for Spectre variant 2 */ +#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* "" AMD Retpoline mitigation for Spectre variant 2 */ /* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */ #define X86_FEATURE_PTI ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nopti */ diff --git a/arch/x86/include/asm/spec_ctrl.h b/arch/x86/include/asm/spec_ctrl.h index 582e116f9eb5..1d5af4745446 100644 --- a/arch/x86/include/asm/spec_ctrl.h +++ b/arch/x86/include/asm/spec_ctrl.h @@ -198,11 +198,11 @@ .endm .macro SET_IBPB -ALTERNATIVE "", __stringify(__ASM_SET_IBPB), X86_FEATURE_SPEC_CTRL +ALTERNATIVE "", __stringify(__ASM_SET_IBPB), X86_FEATURE_IBRS .endm .macro DISABLE_IBRS_CLOBBER -ALTERNATIVE "", __stringify(__ASM_DISABLE_IBRS_CLOBBER), X86_FEATURE_SPEC_CTRL +ALTERNATIVE "", __stringify(__ASM_DISABLE_IBRS_CLOBBER), X86_FEATURE_IBRS .endm .macro STUFF_RSB diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 39876a3c26ca..4dbac25c0aec 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -756,13 +756,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_virt_bits = (eax >> 8) & 0xff; c->x86_phys_bits = eax & 0xff; - /* Only look for X86_FEATURE_{IBPB, SPEC_CTRL, STIBP}. */ + /* Only look for X86_FEATURE_{IBPB, IBRS, STIBP}. */ if (ebx & BIT(12)) set_cpu_cap(c, X86_FEATURE_IBPB); if (ebx & BIT(14)) - set_cpu_cap(c, X86_FEATURE_SPEC_CTRL); + set_cpu_cap(c, X86_FEATURE_IBRS); if (ebx & BIT(15)) - set_cpu_cap(c, X86_FEATURE_STIPB); + set_cpu_cap(c, X86_FEATURE_STIBP); } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index c1dba23349c2..a506d475befc 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -105,11 +105,11 @@ static void early_init_intel(struct cpuinfo_x86 *c) rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode); } - if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || + if ((cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { if (&boot_cpu_data == c) - pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_CTRL\n"); - clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL); + pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_CTRL/IBRS\n"); + clear_cpu_cap(c, X86_FEATURE_IBRS); clear_cpu_cap(c, X86_FEATURE_IBPB); clear_cpu_cap(c, X86_FEATURE_STIBP); } diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 06e9143e3489..c1b207f5262f 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,7 +49,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, - { X86_FEATURE_SPEC_CTRL, CR_EDX,26, 0x00000007, 0 }, + { X86_FEATURE_IBRS, CR_EDX,26, 0x00000007, 0 }, { X86_FEATURE_STIPB, CR_EDX,27, 0x00000007, 0 }, { X86_FEATURE_IA32_ARCH_CAPS, CR_EDX,29, 0x00000007, 0 }, { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 }, @@ -96,7 +96,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) if (xen_pv_domain()) ignore = true; - if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) { + if (boot_cpu_has(X86_FEATURE_IBRS)) { printk(KERN_INFO "FEATURE SPEC_CTRL Present%s\n", ignore ? " but ignored (Xen)": ""); if (ignore) return; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b47511b91de0..0d9fa5311f9a 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -463,17 +463,17 @@ static __cpuidle void mwait_idle(void) smp_mb(); /* quirk */ } - if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) + if (boot_cpu_has(X86_FEATURE_IBRS)) native_wrmsrl(MSR_IA32_SPEC_CTRL, SPEC_CTRL_FEATURE_DISABLE_IBRS); __monitor((void *)¤t_thread_info()->flags, 0, 0); if (!need_resched()) { __sti_mwait(0, 0); - if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) + if (boot_cpu_has(X86_FEATURE_IBRS)) native_wrmsrl(MSR_IA32_SPEC_CTRL, SPEC_CTRL_FEATURE_ENABLE_IBRS); } else { - if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) + if (boot_cpu_has(X86_FEATURE_IBRS)) native_wrmsrl(MSR_IA32_SPEC_CTRL, SPEC_CTRL_FEATURE_ENABLE_IBRS); local_irq_enable(); } diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index d2392f8affba..aa49b40b1da8 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -59,7 +59,7 @@ u64 kvm_supported_xcr0(void) #define F(x) bit(X86_FEATURE_##x) /* These are scattered features in cpufeatures.h. */ -#define KVM_CPUID_BIT_SPEC_CTRL 26 +#define KVM_CPUID_BIT_IBRS 26 #define KVM_CPUID_BIT_STIBP 27 @@ -364,7 +364,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, const u32 kvm_supported_word10_x86_features = F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | f_xsaves; - const u32 kvm_cpuid_7_0_edx_x86_features = KF(SPEC_CTRL) | KF(STIBP); + const u32 kvm_cpuid_7_0_edx_x86_features = KF(IBRS) | KF(STIBP); /* cpuid 0x80000008.ebx */ const u32 kvm_cpuid_80000008_ebx_x86_features = @@ -443,8 +443,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, entry->ebx |= F(TSC_ADJUST); entry->edx &= kvm_cpuid_7_0_edx_x86_features; /* Aka !ibrs_supported and !ibpb_supported */ - if ( !boot_cpu_has(X86_FEATURE_SPEC_CTRL) ) - entry->edx &= !(1u << KVM_CPUID_BIT_SPEC_CTRL); + if ( !boot_cpu_has(X86_FEATURE_IBRS) ) + entry->edx &= !(1u << KVM_CPUID_BIT_IBRS); if ( !boot_cpu_has(X86_FEATURE_STIPB) ) entry->edx &= !(1u << KVM_CPUID_BIT_STIBP); } else {