From: Potin Lai <potin.lai.pt@gmail.com>
Date: Fri, 21 Mar 2025 07:26:09 +0000 (+0800)
Subject: ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=df89538262c5af1ee86619a4200533c238ffbd73;p=users%2Fjedix%2Flinux-maple.git

ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses

Update the device tree to enable `multi-master` mode on I2C buses shared
between the host BMC and the NV module with HMC. This ensures proper bus
arbitration and coordination in multi-master environments, preventing
communication conflicts and improving reliability.

Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Link: https://patch.msgid.link/20250321-potin-catalina-dts-update-20250102-v6-8-4bd85efeb9b4@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
---

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
index 6702be32918e..2dbb65db9250 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
@@ -815,6 +815,7 @@
 
 &i2c12 {
 	status = "okay";
+	multi-master;
 
 	// Module 1 FRU EEPROM
 	eeprom@50 {
@@ -825,6 +826,7 @@
 
 &i2c13 {
 	status = "okay";
+	multi-master;
 
 	// Module 0 FRU EEPROM
 	eeprom@50 {