From: Minda Chen Date: Wed, 2 Aug 2023 06:42:15 +0000 (+0800) Subject: riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause X-Git-Tag: v6.7-rc1~38^2~7 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=dd16ac404a685cce07e67261a94c6225d90ea7ba;p=users%2Fdwmw2%2Flinux.git riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause Actually it is a part of Conor's commit aae538cd03bc ("riscv: fix detection of toolchain Zihintpause support"). It is looks like a merge issue. Samuel's commit 0b1d60d6dd9e ("riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y") do not base on Conor's commit and revert to __riscv_zihintpause. So this patch can fix it. Signed-off-by: Minda Chen Fixes: 3c349eacc559 ("Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"") Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230802064215.31111-1-minda.chen@starfivetech.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h index 14f5d27783b85..96b65a5396dfc 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -14,7 +14,7 @@ static inline void cpu_relax(void) __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); #endif -#ifdef __riscv_zihintpause +#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE /* * Reduce instruction retirement. * This assumes the PC changes.