From: Gregory CLEMENT Date: Fri, 11 Jul 2025 09:54:21 +0000 (+0200) Subject: MIPS: CPS: Optimise delay CPU calibration for SMP X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=db6f8fcd56438a078ef61779ff68068a0886a79b;p=users%2Fjedix%2Flinux-maple.git MIPS: CPS: Optimise delay CPU calibration for SMP On MIPS architecture with CPS-based SMP support, all CPU cores in the same cluster run at the same frequency since they share the same L2 cache, requiring a fixed CPU/L2 cache ratio. This allows to implement calibrate_delay_is_known(), which will return 0 (triggering calibration) only for the primary CPU of each cluster. For other CPUs, we can simply reuse the value from their cluster's primary CPU core. With the introduction of this patch, a configuration running 32 cores spread across two clusters sees a significant reduction in boot time by approximately 600 milliseconds. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 6c5f15293a8e..22d4f9ff3ae2 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -281,6 +281,17 @@ static void __init cps_smp_setup(void) #endif /* CONFIG_MIPS_MT_FPAFF */ } +unsigned long calibrate_delay_is_known(void) +{ + int first_cpu_cluster = 0; + + /* The calibration has to be done on the primary CPU of the cluster */ + if (mips_cps_first_online_in_cluster(&first_cpu_cluster)) + return 0; + + return cpu_data[first_cpu_cluster].udelay_val; +} + static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned int nclusters, ncores, core_vpes, nvpe = 0, c, cl, cca;