From: Allen-KH Cheng Date: Thu, 21 Apr 2022 03:51:10 +0000 (+0800) Subject: arm64: dts: mediatek: mt8173: Add power domain to encoder nodes X-Git-Tag: howlett/maple/20220722_2~451^2^2~18 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=dab2782be22c359dd1a14a118e9b1592a7f91db3;p=users%2Fjedix%2Flinux-maple.git arm64: dts: mediatek: mt8173: Add power domain to encoder nodes The power of encoder is not control by mediatek,larb, so we add power domain to encoder nodes for mt8173 SoC. Signed-off-by: Irui Wang Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220421035111.7267-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 10291b2690abf..eebc2d0742543 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1470,6 +1470,7 @@ clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; }; jpegdec: jpegdec@18004000 { @@ -1520,6 +1521,7 @@ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; }; }; };