From: wdenk Date: Fri, 7 Jun 2002 13:51:35 +0000 (+0000) Subject: * Patch by Stefan Roese: X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=d8b0605825b4a18fc3bcff408ae4f363b4da695b;p=users%2Frw%2Fppcboot.git * Patch by Stefan Roese: - PCI405 board added. - CPCI4052 fpga image changed. - First step to add PPC405GPr support. - 405gp_pci.c: PCI class code init added (if defined). --- diff --git a/CHANGELOG b/CHANGELOG index 7625903..9e92b49 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,6 +14,12 @@ Modifications for 1.1.6: ====================================================================== +* Patch by Stefan Roese: + - PCI405 board added. + - CPCI4052 fpga image changed. + - First step to add PPC405GPr support. + - 405gp_pci.c: PCI class code init added (if defined). + * Fix initialization of funtion pointers for relocation; so far, the ethernet functions were still called from flash, causing PPCBoot to crash when you erased the flash and then tried to TFTP... diff --git a/MAKEALL b/MAKEALL index 9b6bdfe..6c9e4d4 100755 --- a/MAKEALL +++ b/MAKEALL @@ -36,8 +36,8 @@ LIST_4xx=" \ ADCIOP AR405 CANBT CPCI405 \ CPCI4052 CPCIISER4 CRAYL1 DASA_SIM \ DU405 ERIC MIP405 OCRTC \ - ORSG PIP405 W7OLMC W7OLMG \ - WALNUT405 \ + ORSG PCI405 PIP405 W7OLMC \ + W7OLMG WALNUT405 \ " ######################################################################### diff --git a/Makefile b/Makefile index 835d5a3..96c56d1 100644 --- a/Makefile +++ b/Makefile @@ -510,7 +510,7 @@ CANBT_config: unconfig CPCI405_config \ CPCI4052_config: unconfig - @echo "Configuring for $(call xtract,$@) Board..." ; \ + @echo "Configuring for $(@:_config=) Board..." ; \ cd ./include ; \ echo "ARCH = ppc" > config.mk ; \ echo "BOARD = cpci405" >>config.mk ; \ @@ -581,6 +581,15 @@ ORSG_config: unconfig echo "VENDOR = esd" >>config.mk ; \ echo "#include " >config.h +PCI405_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd ./include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = pci405" >>config.mk ; \ + echo "CPU = ppc4xx" >>config.mk ; \ + echo "VENDOR = esd" >>config.mk ; \ + echo "#include " >config.h + PIP405_config:unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd ./include ; \ diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 6674852..1a04b41 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -57,96 +57,91 @@ int gunzip(void *, int, unsigned char *, int *); int board_pre_init (void) { #ifndef CONFIG_CPCI405_VER2 - int index, len, i; - int status; + int index, len, i; + int status; #endif #ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - serial_init(get_gclk_freq(), CONFIG_BAUDRATE); - console_init_f(); + /* set up serial port with default baudrate */ + serial_init(get_gclk_freq(), CONFIG_BAUDRATE); + console_init_f(); #endif - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) - */ - out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(IBM405GP_GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(IBM405GP_GPIO0_OR, 0); /* pull prg low */ - - /* - * Boot onboard FPGA - */ + /* + * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + */ + out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(IBM405GP_GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(IBM405GP_GPIO0_OR, 0); /* pull prg low */ + + /* + * Boot onboard FPGA + */ #ifndef CONFIG_CPCI405_VER2 - if (!version2()) - { - status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); - if (status != 0) - { - /* booting FPGA failed */ + if (!version2()) { + status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); + if (status != 0) { + /* booting FPGA failed */ #ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - serial_init(get_gclk_freq(), CONFIG_BAUDRATE); - console_init_f(); + /* set up serial port with default baudrate */ + serial_init(get_gclk_freq(), CONFIG_BAUDRATE); + console_init_f(); #endif - printf("\nFPGA: Booting failed "); - switch (status) - { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) - { - len = fpgadata[index]; - printf("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) - { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, NULL, 0, 0, NULL); + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = fpgadata[index]; + printf("FPGA: %s\n", &(fpgadata[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, NULL, 0, 0, NULL); + } } - } #endif /* !CONFIG_CPCI405_VER2 */ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; } @@ -155,189 +150,178 @@ int board_pre_init (void) int ctermm2(void) { #ifdef CONFIG_CPCI405_VER2 - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ #else - if ((*(unsigned char *)0xf0000400 == 0x00) && - (*(unsigned char *)0xf0000401 == 0x01)) - return 0; /* no, board is cpci405 */ - else - return -1; /* yes, board is cterm-m2 */ + if ((*(unsigned char *)0xf0000400 == 0x00) && + (*(unsigned char *)0xf0000401 == 0x01)) + return 0; /* no, board is cpci405 */ + else + return -1; /* yes, board is cterm-m2 */ #endif } int cpci405_host(void) { - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ - else - return 0; /* no, board is cpci405 adapter */ + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + return -1; /* yes, board is cpci405 host */ + else + return 0; /* no, board is cpci405 adapter */ } int version2(void) { - unsigned long cntrl0Reg; - unsigned long value; - - /* - * Setup GPIO pins (CS2/GPIO11 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x02000000); - - value = in32(IBM405GP_GPIO0_IR) & 0x02000000; - - /* - * Setup GPIO pins (CS2/GPIO11 as CS again) - */ - mtdcr(cntrl0, cntrl0Reg); - - if (value) - return -1; /* yes, board is version 2.x */ - else - return 0; /* no, board is version 1.x */ + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Setup GPIO pins (CS2/GPIO11 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x02000000); + + value = in32(IBM405GP_GPIO0_IR) & 0x02000000; + + /* + * Setup GPIO pins (CS2/GPIO11 as CS again) + */ + mtdcr(cntrl0, cntrl0Reg); + + if (value) + return -1; /* yes, board is version 2.x */ + else + return 0; /* no, board is version 1.x */ } int misc_init_f(void) { - return 0; /* dummy implementation */ + return 0; /* dummy implementation */ } void misc_init_r(bd_t *bd) { - char * tmp; /* Temporary char pointer */ + char * tmp; /* Temporary char pointer */ #ifdef CONFIG_CPCI405_VER2 - unsigned char *dst; - ulong len; - int status; - int index; - int i; - unsigned long cntrl0Reg; - - /* - * On CPCI-405 version 2 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - - if (version2()) - { - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + unsigned long cntrl0Reg; + + /* + * On CPCI-405 version 2 the environment is saved in eeprom! + * FPGA can be gzip compressed (malloc) and booted this late. + */ + + if (version2()) { + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00300000); - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) - { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, NULL, 0, 0, NULL); + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, NULL, 0, 0, NULL); + } + + /* restore gpio/cs settings */ + mtdcr(cntrl0, cntrl0Reg); + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); } - - status = fpga_boot(dst, len); - if (status != 0) - { - printf("\nFPGA: Booting failed "); - switch (status) - { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) - { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) - { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, NULL, 0, 0, NULL); + else { + printf("\n*** PPCBoot Version does not match Board Version!\n"); + printf("*** CPCI-405 Version 2.x detected!\n"); + printf("*** Please use correct PPCBoot version (CPCI4052)!\n\n"); } - /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); - - puts("FPGA: "); +#else /* CONFIG_CPCI405_VER2 */ - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) - { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; + /* + * Generate last byte of ip-addr from code-plug @ 0xf0000400 + */ + if (ctermm2()) { + char str[32]; + unsigned char ipbyte = *(unsigned char *)0xf0000400; + + /* + * Only overwrite ip-addr with allowed values + */ + if ((ipbyte != 0x00) && (ipbyte != 0xff)) { + bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; + sprintf(str, "%ld.%ld.%ld.%ld", + (bd->bi_ip_addr & 0xff000000) >> 24, + (bd->bi_ip_addr & 0x00ff0000) >> 16, + (bd->bi_ip_addr & 0x0000ff00) >> 8, + (bd->bi_ip_addr & 0x000000ff)); + setenv("ipaddr", str); + } } - putc ('\n'); - free(dst); - } - else - { - printf("\n*** PPCBoot Version does not match Board Version!\n"); - printf("*** CPCI-405 Version 2.x detected!\n"); - printf("*** Please use correct PPCBoot version (CPCI4052)!\n\n"); - } - -#else /* CONFIG_CPCI405_VER2 */ - - /* - * Generate last byte of ip-addr from code-plug @ 0xf0000400 - */ - if (ctermm2()) - { - char str[32]; - unsigned char ipbyte = *(unsigned char *)0xf0000400; - - /* - * Only overwrite ip-addr with allowed values - */ - if ((ipbyte != 0x00) && (ipbyte != 0xff)) - { - bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; - sprintf(str, "%ld.%ld.%ld.%ld", - (bd->bi_ip_addr & 0xff000000) >> 24, - (bd->bi_ip_addr & 0x00ff0000) >> 16, - (bd->bi_ip_addr & 0x0000ff00) >> 8, - (bd->bi_ip_addr & 0x000000ff)); - setenv("ipaddr", str); - } - } - - if (version2()) - { - printf("\n*** PPCBoot Version does not match Board Version!\n"); - printf("*** CPCI-405 Board Version 1.x detected!\n"); - printf("*** Please use correct PPCBoot version (CPCI405)!\n\n"); - } + if (version2()) { + printf("\n*** PPCBoot Version does not match Board Version!\n"); + printf("*** CPCI-405 Board Version 1.x detected!\n"); + printf("*** Please use correct PPCBoot version (CPCI405)!\n\n"); + } #endif /* CONFIG_CPCI405_VER2 */ - /* - * Write ethernet addr in NVRAM for VxWorks - */ - tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS; - memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 ); + /* + * Write ethernet addr in NVRAM for VxWorks + */ + tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS; + memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 ); } @@ -348,82 +332,81 @@ void misc_init_r(bd_t *bd) int checkboard (void) { #ifndef CONFIG_CPCI405_VER2 - int index; - int len; + int index; + int len; #endif - unsigned char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + unsigned char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); - if (i == -1) { - printf ("### No HW ID - assuming CPCI405"); - } - else - puts(str); + if (i == -1) { + printf ("### No HW ID - assuming CPCI405"); + } + else + puts(str); - if (version2()) - printf(" (Ver 2.x, "); - else - printf(" (Ver 1.x, "); + if (version2()) + printf(" (Ver 2.x, "); + else + printf(" (Ver 1.x, "); #if 0 - if ((*(unsigned short *)((unsigned long)CFG_FPGA_BASE_ADDR) + CFG_FPGA_STATUS) - & CFG_FPGA_STATUS_FLASH) - printf("FLASH Bank A, "); - else - printf("FLASH Bank B, "); + if ((*(unsigned short *)((unsigned long)CFG_FPGA_BASE_ADDR) + CFG_FPGA_STATUS) + & CFG_FPGA_STATUS_FLASH) + printf("FLASH Bank A, "); + else + printf("FLASH Bank B, "); #endif - if (ctermm2()) - printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400); - else - if (cpci405_host()) - printf("PCI Host Version)"); - else - printf("PCI Adapter Version)"); + if (ctermm2()) + printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400); + else + if (cpci405_host()) + printf("PCI Host Version)"); + else + printf("PCI Adapter Version)"); #ifndef CONFIG_CPCI405_VER2 - puts("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) - { - len = fpgadata[index]; - printf("%s ", &(fpgadata[index+1])); - index += len+3; - } + puts("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = fpgadata[index]; + printf("%s ", &(fpgadata[index+1])); + index += len+3; + } #endif - putc ('\n'); + putc ('\n'); - return 1; + return 1; } /* ------------------------------------------------------------------------- */ long int initdram (int board_type) { - unsigned long val; + unsigned long val; - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); #if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ #endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ int testdram (void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); - return (0); + return (0); } /* ------------------------------------------------------------------------- */ diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c index 4a97e6b..8b8eda1 100644 --- a/board/esd/cpci405/fpgadata_cpci4052.c +++ b/board/esd/cpci405/fpgadata_cpci4052.c @@ -1,692 +1,738 @@ - 0x1f,0x8b,0x08,0x08,0xc5,0x7d,0xdf,0x3c,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30, - 0x35,0x5f,0x32,0x5f,0x30,0x31,0x2e,0x62,0x69,0x74,0x00,0xed,0x9c,0x7f,0x74,0x14, - 0xd7,0x95,0xe7,0x6f,0xbd,0xaa,0x96,0x4a,0xdd,0x2d,0x75,0xa9,0x25,0x91,0x8e,0x0d, - 0xb8,0xd4,0x12,0xb8,0xad,0x69,0x89,0xa6,0x65,0x63,0x8d,0xac,0xb4,0x9e,0x7e,0x40, - 0x3a,0x36,0x09,0x8a,0xe3,0x4c,0xd8,0xc4,0x49,0x9a,0x98,0xcc,0x68,0x66,0x89,0x07, - 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0x9b,0x2f,0x3f,0x82,0x85,0xe1,0x7f,0xcb,0xe6,0xed,0xf7,0xfd,0x56,0x9b,0x37,0x4d, + 0x5d,0xd5,0x8c,0x1f,0xfb,0xc7,0x8b,0xff,0xf6,0x7d,0xf0,0x5b,0xfa,0xf7,0xdb,0xc6, + 0x05,0x1c,0x2a,0xce,0x1e,0x61,0xe5,0xcb,0x3f,0xbb,0xec,0xba,0x62,0xf3,0xff,0x5a, + 0xdd,0xbf,0x7e,0xb1,0xbf,0xe5,0xc8,0x6b,0xff,0x36,0xbd,0xf2,0xbb,0xde,0x73,0xe5, + 0xba,0x72,0x5d,0xb9,0xae,0x5c,0x57,0xae,0x2b,0xd7,0xff,0x2f,0x97,0xb6,0x4f,0xf2, + 0xda,0x3e,0xa9,0xfe,0x47,0xb7,0xe5,0xca,0x75,0xe5,0xba,0x72,0x5d,0xb9,0xae,0x5c, + 0x57,0xae,0xff,0x88,0x2b,0xc2,0xfe,0x76,0x3f,0x44,0xbf,0x6e,0xfc,0xfd,0x7f,0x21, + 0x02,0x64,0xda,0x6f,0xff,0x7d,0xed,0xf7,0x5c,0x11,0xc8,0x72,0xf6,0xfd,0x3d,0x99, + 0xcb,0xdb,0xfa,0xbf,0x00,0x83,0xb4,0x63,0x44,0xd5,0x60,0x00,0x00, diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile new file mode 100644 index 0000000..12b2fa8 --- /dev/null +++ b/board/esd/pci405/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/pci405/config.mk b/board/esd/pci405/config.mk new file mode 100644 index 0000000..83f07fe --- /dev/null +++ b/board/esd/pci405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c new file mode 100644 index 0000000..32b2a56 --- /dev/null +++ b/board/esd/pci405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#define MAGIC0 0x00000000 +#define MAGIC1 0x11111111 +#define MAGIC2 0x22222222 +#define MAGIC3 0x33333333 +#define MAGIC4 0x44444444 + +#define ADDR_ZERO 0x00000000 +#define ADDR_400 0x00000400 +#define ADDR_08MB 0x00800000 +#define ADDR_16MB 0x01000000 +#define ADDR_32MB 0x02000000 +#define ADDR_64MB 0x04000000 + +#include +#include + +#include +#include + + +//----------------------------------------------------------------------------- +// Function: sdram_init +// Description: Configures SDRAM memory banks. +// Auto Memory Configuration option reads the SDRAM EEPROM +// via the IIC bus and then configures the SDRAM memory +// banks appropriately. If Auto Memory Configuration is +// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is +// plugged, ie. the DIMM that shipped wih the Eval board. +//----------------------------------------------------------------------------- + .globl sdram_init + +sdram_init: + + mflr r31 + + //------------------------------------------------------------------- + // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0008 + ori r4,r4,0x4001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. + // To set the appropriate timings, we need to know the SDRAM speed. + // We can use the PLB speed since the SDRAM speed is the same as + // the PLB speed. The PLB speed is the FBK divider times the + // 405GP reference clock, which on the Walnut board is 33Mhz. + // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is + // 100Mhz; if FBK is 3, SDRAM is 133Mhz. + // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and + // maybe 133Mhz. + //------------------------------------------------------------------- + mfdcr r5,strap // determine FBK divider + // via STRAP reg to calc PLB speed. + // SDRAM speed is the same as the PLB + // speed. + rlwinm r4,r5,4,0x3 // get FBK divide bits + +..chk_66: + cmpi %cr0,0,r4,0x1 + bne ..chk_100 + addis r6,0,0x0085 // SDTR1 value for 66Mhz + ori r6,r6,0x4005 + addis r7,0,0x03F8 // RTR value for 66Mhz + b ..sdram_ok +..chk_100: + cmpi %cr0,0,r4,0x2 + bne ..chk_133 + addis r6,0,0x0086 // SDTR1 value for 100Mhz + ori r6,r6,0x400D + addis r7,0,0x05F0 // RTR value for 100Mhz + b ..sdram_ok +..chk_133: + addis r6,0,0x0107 // SDTR1 value for 133Mhz + ori r6,r6,0x4015 + addis r7,0,0x07F0 // RTR value for 133Mhz + +..sdram_ok: + //------------------------------------------------------------------- + // Set SDTR1 + //------------------------------------------------------------------- + addi r4,0,mem_sdtr1 + mtdcr memcfga,r4 + mtdcr memcfgd,r6 + + //------------------------------------------------------------------- + // Set RTR + //------------------------------------------------------------------- + addi r4,0,mem_rtr + mtdcr memcfga,r4 + mtdcr memcfgd,r7 + + //------------------------------------------------------------------- + // Delay to ensure 200usec have elapsed since reset. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0000 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp2: + bdnz ..spinlp2 // spin loop + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Delay to ensure 10msec have elapsed since reset. This is + // required for the MPC952 to stabalize. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles + // This delay should occur before accessing SDRAM. + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp3: + bdnz ..spinlp3 // spin loop + + //------------------------------------------------------------------- + // Test if 64MByte is ok. + //------------------------------------------------------------------- + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + stw r3,0x00(r4) // store magic at 0 + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + stw r3,0x00(r4) // store magic at 8MB + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + stw r3,0x00(r4) // store magic at 16MB + addis r3,0,MAGIC3@h + ori r3,r3,MAGIC3@l + addis r4,0,ADDR_32MB@h + ori r4,r4,ADDR_32MB@l + stw r3,0x00(r4) // store magic at 32MB + + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + lwz r5,0x00(r4) // load from 0 + cmplw 0,r3,r5 + bne ..chk_32mb + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + lwz r5,0x00(r4) // load from 8mb + cmplw 0,r3,r5 + bne ..chk_32mb + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + lwz r5,0x00(r4) // load from 8mb + beq ..sdram_done + +..chk_32mb: + //------------------------------------------------------------------- + // Disable memory controller. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x0000 // set DC_EN=0 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0006 + ori r4,r4,0x2001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Wait some time + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp4: + bdnz ..spinlp4 // spin loop + + //------------------------------------------------------------------- + // Test if 32MByte is ok. + //------------------------------------------------------------------- + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + stw r3,0x00(r4) // store magic at 0 + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_400@h + ori r4,r4,ADDR_400@l + stw r3,0x00(r4) // store magic at 0x400 + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + stw r3,0x00(r4) // store magic at 8MB + addis r3,0,MAGIC3@h + ori r3,r3,MAGIC3@l + addis r4,0,ADDR_16MB@h + ori r4,r4,ADDR_16MB@l + stw r3,0x00(r4) // store magic at 16MB + + addis r3,0,MAGIC0@h + ori r3,r3,MAGIC0@l + addis r4,0,ADDR_ZERO@h + ori r4,r4,ADDR_ZERO@l + lwz r5,0x00(r4) // load from 0 + cmplw 0,r3,r5 + bne ..chk_16mb + addis r3,0,MAGIC1@h + ori r3,r3,MAGIC1@l + addis r4,0,ADDR_400@h + ori r4,r4,ADDR_400@l + lwz r5,0x00(r4) // load from 0x400 + cmplw 0,r3,r5 + bne ..chk_16mb + addis r3,0,MAGIC2@h + ori r3,r3,MAGIC2@l + addis r4,0,ADDR_08MB@h + ori r4,r4,ADDR_08MB@l + lwz r5,0x00(r4) // load from 8mb + cmplw 0,r3,r5 + beq ..sdram_done + +..chk_16mb: + //------------------------------------------------------------------- + // Disable memory controller. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x0000 // set DC_EN=0 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // 16 MB is left. + // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0004 + ori r4,r4,0x6001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Wait some time + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp5: + bdnz ..spinlp5 // spin loop + +..sdram_done: + mtlr r31 // restore lr + blr diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c new file mode 100644 index 0000000..9616d81 --- /dev/null +++ b/board/esd/pci405/pci405.c @@ -0,0 +1,252 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include <405gp_pci.h> + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +#define PCI_RECONFIG_MAGIC 0x07081967 + + +struct pci_config_regs { + unsigned short command; + unsigned char latency_timer; + unsigned char int_line; + unsigned long bar1; + unsigned long bar2; + unsigned long magic; +}; + + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, int *); + + +int board_pre_init (void) +{ + unsigned long cntrl0Reg; + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive + * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive + * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive + * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive + * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * Setup GPIO pins (IRQ4/GPIO21 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00008000); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f(void) +{ + return 0; /* dummy implementation */ +} + + +void misc_init_r(bd_t *bd) +{ + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + struct pci_config_regs *pci_regs; + + /* + * On PCI-405 the environment is saved in eeprom! + * FPGA can be gzip compressed (malloc) and booted this late. + */ + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + /* + * Rewrite pci config regs (only after soft-reset with magic set) + */ + pci_regs = (struct pci_config_regs *)0x10; + if (pci_regs->magic == PCI_RECONFIG_MAGIC) { + puts("PCI: Found magic, rewriting config regs...\n"); + pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, + pci_regs->command); + pci_write_config_byte(PCIDEVID_405GP, PCI_LATENCY_TIMER, + pci_regs->latency_timer); + pci_write_config_byte(PCIDEVID_405GP, PCI_INTERRUPT_LINE, + pci_regs->int_line); + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, + pci_regs->bar1); + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, + pci_regs->bar2); + } + pci_regs->magic = 0; /* clear magic again */ + +#if 0 /* test-only */ + pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &(pci_regs->command)); + pci_read_config_byte(PCIDEVID_405GP, PCI_LATENCY_TIMER, &(pci_regs->latency_timer)); + pci_read_config_byte(PCIDEVID_405GP, PCI_INTERRUPT_LINE, &(pci_regs->int_line)); + pci_read_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, &(pci_regs->bar1)); + pci_read_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, &(pci_regs->bar2)); + pci_regs->magic = PCI_RECONFIG_MAGIC; /* set magic */ +#endif + + free(dst); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + unsigned char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + if (i == -1) { + printf ("### No HW ID - assuming CPCI405"); + } + else + puts(str); + + putc ('\n'); + + return 1; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/pci405/ppcboot.lds b/board/esd/pci405/ppcboot.lds new file mode 100644 index 0000000..5a94fa1 --- /dev/null +++ b/board/esd/pci405/ppcboot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/esd/pci405/init.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/405gp_enet.o (.text) + common/dlmalloc.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + ppc/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/pci405/ppcboot.lds.debug b/board/esd/pci405/ppcboot.lds.debug new file mode 100644 index 0000000..35d9f7c --- /dev/null +++ b/board/esd/pci405/ppcboot.lds.debug @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 9331436..6878184 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -65,6 +65,8 @@ | - Removed pci class code init for CPCI405 board | 15-May-02 stefan.roese@esd-electronics.com | - New vga device handling +| 29-May-02 stefan.roese@esd-electronics.com +| - PCI class code init added (if defined) +----------------------------------------------------------------------------*/ #include @@ -228,6 +230,13 @@ void pci_405gp_init(bd_t *bd, struct pci_controller *hose) pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); #endif + /* + * Insert Class-code + */ +#ifdef CFG_PCI_CLASSCODE + pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); +#endif /* CFG_PCI_CLASSCODE */ + #if 0 /* test-only: no need yet! */ /*--------------------------------------------------------------------------+ | If PCI speed = 66Mhz, set 66Mhz capable bit. diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index ceaa93b..a368c47 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -44,90 +44,96 @@ int checkcpu(long clock) { - uint pvr = get_pvr(); - char buf[32]; + uint pvr = get_pvr(); + char buf[32]; #if defined(CONFIG_405GP) || defined(CONFIG_405CR) - PPC405_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; - get_sys_info(&sys_info); + get_sys_info(&sys_info); #if CONFIG_405GP - printf("IBM PowerPC 405GP Rev. "); + puts("IBM PowerPC 405GP"); + if (pvr == PVR_405GPR_RA) { + putc('r'); + } + puts(" Rev. "); #endif #if CONFIG_405CR - printf("IBM PowerPC 405CR Rev. "); + puts("IBM PowerPC 405CR Rev. "); #endif - switch (pvr) - { - case PVR_405GP_RB: - putc('B'); - break; - case PVR_405GP_RC: +#if CONFIG_440GP + puts("IBM PowerPC 440GP Rev. "); +#endif + switch (pvr) { + case PVR_405GP_RB: + putc('B'); + break; + case PVR_405GP_RC: #if CONFIG_405CR - case PVR_405CR_RC: + case PVR_405CR_RC: #endif - putc('C'); - break; - case PVR_405GP_RD: - putc('D'); - break; + putc('C'); + break; + case PVR_405GP_RD: + putc('D'); + break; #if CONFIG_405GP - case PVR_405GP_RE: - putc('E'); - break; + case PVR_405GP_RE: + putc('E'); + break; #endif - case PVR_405CR_RA: - putc('A'); - break; - case PVR_405CR_RB: - putc('B'); - break; - default: - printf("? (PVR=%08x)", pvr); - break; - } - - printf(" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); + case PVR_405CR_RA: + case PVR_405GPR_RA: + putc('A'); + break; + case PVR_405CR_RB: + putc('B'); + break; + default: + printf("? (PVR=%08x)", pvr); + break; + } + + printf(" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), + sys_info.freqPLB / 1000000, + sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, + sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); #if CONFIG_405GP - if (mfdcr(strap) & PSR_PCI_ASYNC_EN) - printf(" PCI async ext clock used, "); - else - printf(" PCI sync clock at %lu MHz, ", - sys_info.freqPLB / sys_info.pllPciDiv / 1000000); - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - printf("internal PCI arbiter enabled\n"); - else - printf("external PCI arbiter enabled\n"); + if (mfdcr(strap) & PSR_PCI_ASYNC_EN) + printf(" PCI async ext clock used, "); + else + printf(" PCI sync clock at %lu MHz, ", + sys_info.freqPLB / sys_info.pllPciDiv / 1000000); + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + printf("internal PCI arbiter enabled\n"); + else + printf("external PCI arbiter enabled\n"); #endif - switch (pvr) - { - case PVR_405GP_RB: - case PVR_405GP_RC: - case PVR_405GP_RD: - case PVR_405CR_RA: - case PVR_405CR_RB: - printf(" 16 kB I-Cache 8 kB D-Cache"); - break; - } + switch (pvr) { + case PVR_405GP_RB: + case PVR_405GP_RC: + case PVR_405GP_RD: + case PVR_405CR_RA: + case PVR_405CR_RB: + printf(" 16 kB I-Cache 8 kB D-Cache"); + break; + } #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ #ifdef CONFIG_IOP480 - printf("PLX IOP480 (PVR=%08x)", pvr); - printf(" at %s MHz:", strmhz(buf, clock)); - printf(" %u kB I-Cache", 4); - printf(" %u kB D-Cache", 2); + printf("PLX IOP480 (PVR=%08x)", pvr); + printf(" at %s MHz:", strmhz(buf, clock)); + printf(" %u kB I-Cache", 4); + printf(" %u kB D-Cache", 2); #endif - printf("\n"); + printf("\n"); - return 0; + return 0; } @@ -150,14 +156,14 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) unsigned long get_tbclk (void) { #if defined(CONFIG_405GP) || defined(CONFIG_405CR) - PPC405_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; - get_sys_info(&sys_info); - return (sys_info.freqProcessor); + get_sys_info(&sys_info); + return (sys_info.freqProcessor); #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ #ifdef CONFIG_IOP480 - return (66000000); + return (66000000); #endif /* CONFIG_IOP480 */ } @@ -166,17 +172,17 @@ unsigned long get_tbclk (void) void watchdog_reset(void) { - int re_enable = disable_interrupts(); - reset_4xx_watchdog(); - if (re_enable) enable_interrupts(); + int re_enable = disable_interrupts(); + reset_4xx_watchdog(); + if (re_enable) enable_interrupts(); } void reset_4xx_watchdog(void) { - /* - * Clear TSR(WIS) bit - */ - mtspr(tsr, 0x40000000); + /* + * Clear TSR(WIS) bit + */ + mtspr(tsr, 0x40000000); } #endif /* CONFIG_WATCHDOG */ diff --git a/include/asm/processor.h b/include/asm/processor.h index b950cfd..4747a8f 100644 --- a/include/asm/processor.h +++ b/include/asm/processor.h @@ -462,6 +462,8 @@ #define PVR_405CR_RA 0x40110041 #define PVR_405CR_RB 0x401100C5 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405GPR_RA 0x50910950 +#define PVR_440GP_RC 0x40120400 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/config_CPCI4052.h b/include/config_CPCI4052.h index 94b645a..e702d40 100644 --- a/include/config_CPCI4052.h +++ b/include/config_CPCI4052.h @@ -312,20 +312,27 @@ #define CFG_FPGA_STATUS 0x02 #define CFG_FPGA_TS 0x04 #define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x08 -#define CFG_FPGA_TS_CAP0_LOW 0x0a -#define CFG_FPGA_TS_CAP1 0x0c -#define CFG_FPGA_TS_CAP1_LOW 0x0e +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e /* FPGA Mode Reg */ #define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 /* FPGA Status Reg */ #define CFG_FPGA_STATUS_DIP0 0x0001 #define CFG_FPGA_STATUS_DIP1 0x0002 #define CFG_FPGA_STATUS_DIP2 0x0004 #define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ #define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ diff --git a/include/config_PCI405.h b/include/config_PCI405.h new file mode 100644 index 0000000..1886676 --- /dev/null +++ b/include/config_PCI405.h @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PCI405 1 /* ...on a PCI405 board */ + +#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ + +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 0 +#define CONFIG_PREBOOT \ + "crc32 f0207004 ffc 0;" \ + "if cmp 0 f0207000 1;" \ + "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ + "else;echo Old CRC is bad;fi" +#endif + +#undef CONFIG_BOOTARGS +#if 1 +#define CONFIG_BOOTCOMMAND \ + "bootm fffc0000" +#else +#define CONFIG_BOOTCOMMAND \ + "mw.l 0 ffffffff; mw.l 4 ffffffff;" \ + "while cmp 0 4 1; do echo Waiting for Host...;done;" \ + "bootm 400000" +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ +#undef CONFIG_PCI_PNP /* no pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ +#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ + +#if 0 /* test-only */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#else +#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */ +#define CFG_PCI_PTM2MS 0xef600001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NVRAM/RTC) initialization */ +#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ +#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (CAN0, 1) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (FPGA internal) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ +#define CFG_FPGA_BASE_ADDR 0xF0400000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#if 1 /* test-only */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#else +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#endif +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/ppcboot.h b/include/ppcboot.h index 627fd13..9bb3dbd 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -255,6 +255,7 @@ void reset_phy (void); defined(CONFIG_OCRTC) || \ defined(CONFIG_ORSG) || \ defined(CONFIG_PCU_E) || \ + defined(CONFIG_PCI405) || \ defined(CONFIG_PIP405) || \ defined(CONFIG_MIP405) || \ defined(CONFIG_PM826) || \