From: wdenk Date: Mon, 1 Apr 2002 16:29:53 +0000 (+0000) Subject: PPCBoot driver cleanup (PID#73 patch): X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=cf9c41f871aac8a5aed405bed9aa837ecaf2bc14;p=users%2Frw%2Fppcboot.git PPCBoot driver cleanup (PID#73 patch): moved lots of duplicated driver code from board directories into new driver directory --- diff --git a/CHANGELOG b/CHANGELOG index 3f2312e..4bcd893 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,6 +14,10 @@ Modifications for 1.1.6: ====================================================================== +* PPCBoot driver cleanup (PID#73 patch): + moved lots of duplicated driver code from board directories + into new driver directory + * Patch by Erik Theisen, 29 Mar 2002: - Eliminate redundant 405 I2C controller reset - Fix "deprecated multi-line string" warning diff --git a/Makefile b/Makefile index 837422d..92b711e 100644 --- a/Makefile +++ b/Makefile @@ -68,6 +68,7 @@ SUBDIRS = tools \ net \ rtc \ dtt \ + drivers \ examples ######################################################################### @@ -85,6 +86,8 @@ OBJS += board/$(BOARDDIR)/lib$(BOARD).a \ cpu/$(CPU)/lib$(CPU).a \ $(ARCH)/lib$(ARCH).a +OBJS += drivers/libdrivers.a + ifeq ($(CPU),ppc4xx) OBJS += cpu/$(CPU)/resetvec.o endif diff --git a/board/cu824/Makefile b/board/cu824/Makefile index e515e6e..35b8428 100644 --- a/board/cu824/Makefile +++ b/board/cu824/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ns16550.o serial.o dc2114x.o +OBJS = $(BOARD).o flash.o $(LIB): .depend $(OBJS) $(AR) crv $@ $^ diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c index 6cdac49..7d53c16 100644 --- a/board/cu824/cu824.c +++ b/board/cu824/cu824.c @@ -24,6 +24,7 @@ #include #include #include +#include #define BOARD_REV_REG 0xFE80002B @@ -99,3 +100,28 @@ long int initdram(int board_type) Done: return ret; } + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), + pci_cfgfunc_config_device, { CFG_ETH_IOBASE, + 0, + PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init(bd_t *bd) +{ + pci_mpc824x_init(bd, &hose); +} diff --git a/board/cu824/dc2114x.c b/board/cu824/dc2114x.c deleted file mode 100644 index bc1ce06..0000000 --- a/board/cu824/dc2114x.c +++ /dev/null @@ -1,610 +0,0 @@ -#include -#include -#include - - /* PCI Registers. - */ -#define PCI_VENDOR_ID 0x00 -#define PCI_COMMAND 0x04 -#define PCI_CLASS_REVISION 0x08 -#define PCI_LATENCY_TIMER 0x0d -#define PCI_BASE_ADDRESS_0 0x10 -#define PCI_CFDA_PSM 0x43 - -#define PCI_COMMAND_IO 0x1 -#define PCI_COMMAND_MASTER 0x4 - -#define CFRV_RN 0x000000f0 /* Revision Number */ -#define CBIO_MASK -128 - -#define WAKEUP 0x00 /* Power Saving Wakeup */ -#define SLEEP 0x80 /* Power Saving Sleep Mode */ - - -#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ -#define DC2114x_DID 0x1900 /* Unique Device ID # */ -#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -#define DC21142 (DC2114x_DID | 0x0010) -#define DC21143 (DC2114x_DID | 0x0030) - -#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) - - /* Ethernet chip registers. - */ -#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */ -#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */ -#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */ -#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */ -#define DE4X5_STS iobase + 0x028 /* Status Register */ -#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */ -#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */ -#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */ - - /* Register bits. - */ -#define BMR_SWR 0x00000001 /* Software Reset */ -#define STS_TS 0x00700000 /* Transmit Process State */ -#define STS_RS 0x000e0000 /* Receive Process State */ -#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -#define OMR_SR 0x00000002 /* Start/Stop Receive */ -#define OMR_PS 0x00040000 /* Port Select */ -#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ -#define OMR_PM 0x00000080 /* Pass All Multicast */ - - /* Descriptor bits. - */ -#define R_OWN 0x80000000 /* Own Bit */ -#define RD_RER 0x02000000 /* Receive End Of Ring */ -#define RD_LS 0x00000100 /* Last Descriptor */ -#define RD_ES 0x00008000 /* Error Summary */ -#define TD_TER 0x02000000 /* Transmit End Of Ring */ -#define T_OWN 0x80000000 /* Own Bit */ -#define TD_LS 0x40000000 /* Last Segment */ -#define TD_FS 0x20000000 /* First Segment */ -#define TD_ES 0x00008000 /* Error Summary */ -#define TD_SET 0x08000000 /* Setup Packet */ - - -#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ -#define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define SROM_SR 0x00000800 /* Select Serial ROM when set */ - -#define DT_IN 0x00000004 /* Serial Data In */ -#define DT_CLK 0x00000002 /* Serial ROM Clock */ -#define DT_CS 0x00000001 /* Serial ROM Chip Select */ - -#define POLL_DEMAND 1 - -#define RESET_DE4X5 {\ - int i;\ - i=inl(DE4X5_BMR);\ - udelay(1000);\ - outl(i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ - outl(i, DE4X5_BMR);\ - udelay(1000);\ - for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\ - udelay(1000);\ -} - -#define START_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr |= OMR_ST | OMR_SR;\ - outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ -} - -#define STOP_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr &= ~(OMR_ST|OMR_SR);\ - outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ -} - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ -#define RX_BUFF_SZ PKTSIZE_ALIGN - -#define TOUT_LOOP 1000000 - -#define SETUP_FRAME_LEN 192 -#define ETH_ALEN 6 - - -struct de4x5_desc { - volatile s32 status; - u32 des1; - u32 buf; - u32 next; -}; - - -static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ - -static char rxRingSize; -static char txRingSize; - -static u_long iobase; - -static void send_setup_frame(bd_t * bis); -static void check_hw_addr(bd_t * bis); -static short srom_rd(u_long address, u_char offset); -static void srom_latch(u_int command, u_long address); -static void srom_command(u_int command, u_long address); -static void srom_address(u_int command, u_long address, u_char offset); -static short srom_data(u_int command, u_long address); -static void sendto_srom(u_int command, u_long addr); -static int getfrom_srom(u_long addr); - -static inline int inl(u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr + 0xfe000000)); -} - -static inline void outl (int command, u_long addr) -{ - *(volatile u_long *)(addr + 0xfe000000) = cpu_to_le32(command); -} - -int eth_init(bd_t *bis) -{ - int i, status = 0; - int vendor, device, l; - int cfrv; - unsigned char timer; - - - CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, l); - - l >>= 8; - - if (l != 0x00020000) - { - printf("Error: Can not find an ethernet card on the PCI bus %d " - "in slot %d\n", CFG_ETH_DEV_FN >> 16, - (CFG_ETH_DEV_FN & 0xFFFF) >> 11); - goto Done; - } - - CONFIG_READ_WORD(0x80000000 | PCI_VENDOR_ID | CFG_ETH_DEV_FN, vendor); - - device = (vendor >> 16) & 0xffff; - vendor = vendor & 0xffff; - device = device << 8; - - if (! is_DC2114x) - { - printf("Error: The chip is not DC2114x.\n"); - goto Done; - } - - /* Get the chip configuration revision register. - */ - CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, - cfrv); - - device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); - - if (device != DC21143) - { - printf("Error: The chip is not DC21143.\n"); - goto Done; - } - - /* Check if I/O accesses and Bus Mastering are enabled. - */ - CONFIG_READ_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, status); - - if (!(status & PCI_COMMAND_IO)) - { - status |= PCI_COMMAND_IO; - CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - } - - if (!(status & PCI_COMMAND_IO)) - { - printf("Error: Can not enable I/O access.\n"); - goto Done; - } - - if (!(status & PCI_COMMAND_MASTER)) - { - status |= PCI_COMMAND_MASTER; - CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - } - if (!(status & PCI_COMMAND_MASTER)) - { - printf("Error: Can not enable Bus Mastering.\n"); - goto Done; - } - - /* Check the latency timer for values >= 0x60. - */ - CONFIG_READ_BYTE(0x80000000 | PCI_LATENCY_TIMER | CFG_ETH_DEV_FN, - timer); - if (timer < 0x60) - { - CONFIG_WRITE_BYTE(0x80000000 | PCI_LATENCY_TIMER | - CFG_ETH_DEV_FN, - 0X60); - } - - /* Set I/O base register. - */ - CONFIG_WRITE_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN, - CFG_ETH_IOBASE); - - CONFIG_READ_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN, - iobase); - - if (iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - goto Done; - } - - iobase &= CBIO_MASK; - - /* Ensure we're not sleeping. - */ - CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, WAKEUP); - - udelay(10 * 1000); - - check_hw_addr(bis); - - RESET_DE4X5; - - if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; - } - - outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); - - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].status = cpu_to_le32(R_OWN); - rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32((u_long)NetRxPackets[i]); - rx_ring[i].next = 0; - } - - for (i=0; i < NUM_TX_DESC; i++) - { - tx_ring[i].status = 0; - tx_ring[i].des1 = 0; - tx_ring[i].buf = 0; - tx_ring[i].next = 0; - } - - rxRingSize = NUM_RX_DESC; - txRingSize = NUM_TX_DESC; - - /* Write the end of list marker to the descriptor lists. - */ - rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); - - /* Tell the adapter where the TX/RX rings are located. - */ - outl((u_long)&rx_ring, DE4X5_RRBA); - outl((u_long)&tx_ring, DE4X5_TRBA); - - START_DE4X5; - - tx_new = 0; - rx_new = 0; - - send_setup_frame(bis); - -Done: - - return 0; -} - -int eth_send(volatile void *packet, int length) -{ - int status = 0; - int i; - - if (length <= 0) - { - printf("eth: bad packet size: %d\n", length); - goto out; - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)packet); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - - if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) - { -#if 0 - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); -#endif - status++; - } - - out: - return status; -} - -int eth_rx(void) -{ - s32 status; - int length = 0; - - for ( ; ; ) - { - status = (s32)le32_to_cpu(rx_ring[rx_new].status); - - if (status & R_OWN) - { - break; - } - - if (status & RD_LS) - { - /* Valid frame status. - */ - if (status & RD_ES) - { - /* There was an error. - */ - printf("RX error status = 0x%08X\n", status); - } - else - { - /* A valid frame received. - */ - length = (le32_to_cpu(rx_ring[rx_new].status) >> - 16); - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(NetRxPackets[rx_new], length - 4); - } - - /* Change buffer ownership for this frame, back - * to the adapter. - */ - rx_ring[rx_new].status = cpu_to_le32(R_OWN); - } - - /* Update entry information. - */ - rx_new = (rx_new + 1) % rxRingSize; - } - - return length; -} - -void eth_halt(void) -{ - if (iobase != CFG_ETH_IOBASE) { - /* Ethernet has not been initialized yet. */ - return; - } - - STOP_DE4X5; - outl(0, DE4X5_SICR); - CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, SLEEP); -} - -static void check_hw_addr(bd_t *bis) -{ - unsigned char hw_addr[ETH_ALEN]; - u_short tmp, *p = (short *)(&hw_addr[0]); - int i, j = 0; - - for (i = 0; i < (ETH_ALEN >> 1); i++) - { - tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if ((j == 0) || (j == 0x2fffd)) - { - printf("Warning: can't read HW address from SROM.\n"); - goto Done; - } - - for (i = 0; i < ETH_ALEN; i++) - { - if (hw_addr[i] != bis->bi_enetaddr[i]) - { - printf("Warning: HW addresses don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - goto Done; - } - } - -Done: - return; -} - -static void send_setup_frame(bd_t *bis) -{ - int i; - char setup_frame[SETUP_FRAME_LEN]; - char * pa = &setup_frame[0]; - - memset(pa, 0xff, SETUP_FRAME_LEN); - - for (i = 0; i < ETH_ALEN; i++) - { - *(pa + (i & 1)) = bis->bi_enetaddr[i]; - if (i & 0x01) - { - pa += 4; - } - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)&setup_frame[0]); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - -#if 0 - if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) - { - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - } -#endif -out: - return; -} - - /* SROM Read. - */ -static short -srom_rd(u_long addr, u_char offset) -{ - sendto_srom(SROM_RD | SROM_SR, addr); - - srom_latch(SROM_RD | SROM_SR | DT_CS, addr); - srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data(SROM_RD | SROM_SR | DT_CS, addr); -} - -static void -srom_latch(u_int command, u_long addr) -{ - sendto_srom(command, addr); - sendto_srom(command | DT_CLK, addr); - sendto_srom(command, addr); - - return; -} - -static void -srom_command(u_int command, u_long addr) -{ - srom_latch(command, addr); - srom_latch(command, addr); - srom_latch((command & 0x0000ff00) | DT_CS, addr); - - return; -} - -static void -srom_address(u_int command, u_long addr, u_char offset) -{ - int i; - signed char a; - - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) { - srom_latch(command | ((a < 0) ? DT_IN : 0), addr); - } - udelay(1); - - i = (getfrom_srom(addr) >> 3) & 0x01; - - return; -} - -static short -srom_data(u_int command, u_long addr) -{ - int i; - short word = 0; - s32 tmp; - - for (i=0; i<16; i++) { - sendto_srom(command | DT_CLK, addr); - tmp = getfrom_srom(addr); - sendto_srom(command, addr); - - word = (word << 1) | ((tmp >> 3) & 0x01); - } - - sendto_srom(command & 0x0000ff00, addr); - - return word; -} - -static void -sendto_srom(u_int command, u_long addr) -{ - outl(command, addr); - udelay(1); - - return; -} - -static int -getfrom_srom(u_long addr) -{ - s32 tmp; - - tmp = inl(addr); - udelay(1); - - return tmp; -} - diff --git a/board/cu824/ns16550.c b/board/cu824/ns16550.c deleted file mode 100644 index 52dc29f..0000000 --- a/board/cu824/ns16550.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines - */ - -#include -#include "ns16550.h" - -typedef struct NS16550 *NS16550_t; - -const NS16550_t COM_PORTS[] = { (NS16550_t) (0xfe800080), - (NS16550_t) (0xfe8000c0) }; - -volatile struct NS16550 * -NS16550_init(int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -return (com_port); -} - -void -NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -} - -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0) ; - com_port->thr = c; -} - -unsigned char -NS16550_getc(volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0) ; - return (com_port->rbr); -} - -int NS16550_tstc(volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} - - - diff --git a/board/cu824/ns16550.h b/board/cu824/ns16550.h deleted file mode 100644 index cd8815c..0000000 --- a/board/cu824/ns16550.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - */ - - -struct NS16550 - { - unsigned long rbr; /* 0 */ - unsigned long ier; /* 1 */ - unsigned long fcr; /* 2 */ - unsigned long lcr; /* 3 */ - unsigned long mcr; /* 4 */ - unsigned long lsr; /* 5 */ - unsigned long msr; /* 6 */ - unsigned long scr; /* 7 */ - }; - -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -#define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*reciever soft reset*/ -#define FCR_TXSR 0x04 /*transmitter soft reset*/ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask*/ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble*/ -#define LCR_EPS 0x10 /* Even Parity Select*/ -#define LCR_STKP 0x20 /* Stick Parity*/ -#define LCR_SBRK 0x40 /* Set Break*/ -#define LCR_BKSE 0x80 /* Bank select enable*/ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc(volatile struct NS16550 *com_port); -int NS16550_tstc(volatile struct NS16550 *com_port); -void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); - diff --git a/board/eltec/bab750/Makefile b/board/eltec/bab750/Makefile index 0b448bf..d8529f9 100644 --- a/board/eltec/bab750/Makefile +++ b/board/eltec/bab750/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ns16550.o ns87308.o serial.o speed.o \ - dc2114x.o w83c553f.o mpc106_pci.o mpc106.o sym53c8xx.o +OBJS = $(BOARD).o flash.o speed.o mpc106_pci.o mpc106.o SOBJS = mpc106_init.o $(LIB): .depend $(OBJS) $(SOBJS) diff --git a/board/eltec/bab750/dc2114x.c b/board/eltec/bab750/dc2114x.c deleted file mode 100644 index 1a141e0..0000000 --- a/board/eltec/bab750/dc2114x.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -/* PCI Registers. - */ -#define PCI_CFDA_PSM 0x43 - -#define CFRV_RN 0x000000f0 /* Revision Number */ -#define CBIO_MASK 0xffffff80 - -#define WAKEUP 0x00 /* Power Saving Wakeup */ -#define SLEEP 0x80 /* Power Saving Sleep Mode */ - - -#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ -#define DC2114x_DID 0x0019 /* Unique Device ID # */ -#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -#define DC21142 (DC2114x_DID << 8 | 0x0010) -#define DC21143 (DC2114x_DID << 8 | 0x0030) - -#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) - -/* Ethernet chip registers. - */ -#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */ -#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */ -#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */ -#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */ -#define DE4X5_STS iobase + 0x028 /* Status Register */ -#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */ -#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */ -#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */ - -/* Register bits. - */ -#define BMR_SWR 0x00000001 /* Software Reset */ -#define STS_TS 0x00700000 /* Transmit Process State */ -#define STS_RS 0x000e0000 /* Receive Process State */ -#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -#define OMR_SR 0x00000002 /* Start/Stop Receive */ -#define OMR_PS 0x00040000 /* Port Select */ -#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ -#define OMR_PM 0x00000080 /* Pass All Multicast */ - -/* Descriptor bits. - */ -#define R_OWN 0x80000000 /* Own Bit */ -#define RD_RER 0x02000000 /* Receive End Of Ring */ -#define RD_LS 0x00000100 /* Last Descriptor */ -#define RD_ES 0x00008000 /* Error Summary */ -#define TD_TER 0x02000000 /* Transmit End Of Ring */ -#define T_OWN 0x80000000 /* Own Bit */ -#define TD_LS 0x40000000 /* Last Segment */ -#define TD_FS 0x20000000 /* First Segment */ -#define TD_ES 0x00008000 /* Error Summary */ -#define TD_SET 0x08000000 /* Setup Packet */ - - -#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ -#define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define SROM_SR 0x00000800 /* Select Serial ROM when set */ - -#define DT_IN 0x00000004 /* Serial Data In */ -#define DT_CLK 0x00000002 /* Serial ROM Clock */ -#define DT_CS 0x00000001 /* Serial ROM Chip Select */ - -#define POLL_DEMAND 1 - -#define RESET_DE4X5 {\ - int i;\ - i=inl(DE4X5_BMR);\ - udelay(1000);\ - outl(i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ - outl(i, DE4X5_BMR);\ - udelay(1000);\ - for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\ - udelay(1000);\ -} - -#define START_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr |= OMR_ST | OMR_SR;\ - outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ -} - -#define STOP_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr &= ~(OMR_ST|OMR_SR);\ - outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ -} - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ -#define RX_BUFF_SZ PKTSIZE_ALIGN - -#define TOUT_LOOP 1000000 - -#define SETUP_FRAME_LEN 192 -#define ETH_ALEN 6 - - -struct de4x5_desc { - volatile s32 status; - u32 des1; - u32 buf; - u32 next; -}; - -static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ - -static char rxRingSize; -static char txRingSize; - -static u_long iobase; - -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); - -static void send_setup_frame(bd_t * bis); -static void check_hw_addr(bd_t * bis); -static short srom_rd(u_long address, u_char offset); -static void srom_latch(u_int command, u_long address); -static void srom_command(u_int command, u_long address); -static void srom_address(u_int command, u_long address, u_char offset); -static short srom_data(u_int command, u_long address); -static void sendto_srom(u_int command, u_long addr); -static int getfrom_srom(u_long addr); - -static int inl(u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr)); -} - -static void outl (int command, u_long addr) -{ - *(volatile u_long *)(addr) = cpu_to_le32(command); -} - - -int devbusfn = 0; - -int eth_init(bd_t *bis) -{ - int i, status = 0; - int device; - int cfrv; - unsigned char timer; - - devbusfn = PCI_Find_Device(DC2114x_VID, DC2114x_DID); - if (devbusfn == -1) - { - printf("Error: Cannot find an ethernet card on any PCI bus."); - goto Done; - } - - /* Get the chip configuration revision register. */ - cfrv = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_REVISION, 4); - - device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); - - if (device != DC21143) - { - printf("Error: The chip is not DC21143.\n"); - goto Done; - } - - status = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_COMMAND, 2); - status |= PCI_CMD_MASTER | PCI_CMD_IOEN | PCI_CMD_MEMEN; - PCI_Write_CFG_Reg(devbusfn, PCI_CFG_COMMAND, status, 2); - - /* Check the latency timer for values >= 0x60. */ - timer = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_LATENCY_TIMER, 1); - - if (timer < 0x60) - { - PCI_Write_CFG_Reg(devbusfn, PCI_CFG_LATENCY_TIMER, 0x60, 1); - } - - /* read BAR for memory space access */ - iobase = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_BASE_ADDRESS_1, 4); - - iobase &= CBIO_MASK; - iobase |= CFG_60X_PCI_MEM_OFFSET; - - /* Ensure we're not sleeping. */ - PCI_Write_CFG_Reg(devbusfn, PCI_CFDA_PSM, WAKEUP, 1); - - udelay(10 * 1000); - - check_hw_addr(bis); - - RESET_DE4X5; - - if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) - { - printf("Error: Cannot reset ethernet controller.\n"); - goto Done; - } - - outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); - - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].status = cpu_to_le32(R_OWN); - rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32(phys_to_bus((void*)NetRxPackets[i])); - rx_ring[i].next = 0; - } - - for (i=0; i < NUM_TX_DESC; i++) - { - tx_ring[i].status = 0; - tx_ring[i].des1 = 0; - tx_ring[i].buf = 0; - tx_ring[i].next = 0; - } - - rxRingSize = NUM_RX_DESC; - txRingSize = NUM_TX_DESC; - - /* Write the end of list marker to the descriptor lists. */ - rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); - - /* Tell the adapter where the TX/RX rings are located. */ - outl(phys_to_bus(&rx_ring), DE4X5_RRBA); - outl(phys_to_bus(&tx_ring), DE4X5_TRBA); - - START_DE4X5; - - tx_new = 0; - rx_new = 0; - - send_setup_frame(bis); - -Done: - return 0; -} - -int eth_send(volatile void *packet, int length) -{ - int status = 0; - int i; - - if (length <= 0) - { - printf("eth: bad packet size: %d\n", length); - goto out; - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((void*)packet)); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - -#if 0 /* test-only */ - if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) - { - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - status++; - } -#endif - - out: - return status; -} - -int eth_rx(void) -{ - s32 status; - int length = 0; - - for ( ; ; ) { - status = (s32)le32_to_cpu(rx_ring[rx_new].status); - - if (status & R_OWN) { - break; - } - - if (status & RD_LS) { - /* Valid frame status. - */ - if (status & RD_ES) { - /* There was an error. - */ - printf("RX error status = 0x%08X\n", status); - } - else { - /* A valid frame received. - */ - length = (le32_to_cpu(rx_ring[rx_new].status) >> - 16); - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(NetRxPackets[rx_new], length - 4); - } - - /* Change buffer ownership for this frame, back - * to the adapter. - */ - rx_ring[rx_new].status = cpu_to_le32(R_OWN); - } - - /* Update entry information. - */ - rx_new = (rx_new + 1) % rxRingSize; - } - - return length; -} - -void eth_halt(void) -{ -#if 1 - STOP_DE4X5; - outl(0, DE4X5_SICR); - if (devbusfn > 0) - PCI_Write_CFG_Reg(devbusfn, PCI_CFDA_PSM, SLEEP, 1); -#endif -} - -static void check_hw_addr(bd_t *bis) -{ - unsigned char hw_addr[ETH_ALEN]; - u_short tmp, *p = (short *)(&hw_addr[0]); - int i, j = 0; - - for (i = 0; i < (ETH_ALEN >> 1); i++) { - tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if ((j == 0) || (j == 0x2fffd)) { - printf("Warning: can't read HW address from SROM.\n"); - goto Done; - } - - for (i = 0; i < ETH_ALEN; i++) { - if (hw_addr[i] != bis->bi_enetaddr[i]) { - printf("Warning: HW addresses don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - goto Done; - } - } - -Done: - return; -} - -static void send_setup_frame(bd_t *bis) -{ - int i; - char setup_frame[SETUP_FRAME_LEN]; - char *pa = &setup_frame[0]; - - memset(pa, 0xff, SETUP_FRAME_LEN); - - for (i = 0; i < ETH_ALEN; i++) { - *(pa + (i & 1)) = bis->bi_enetaddr[i]; - if (i & 0x01) - { - pa += 4; - } - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i >= TOUT_LOOP) { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus(&setup_frame[0])); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { - if (i >= TOUT_LOOP) { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - - if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { - printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); - } -out: - return; -} - -/* SROM Read. - */ -static short -srom_rd(u_long addr, u_char offset) -{ - sendto_srom(SROM_RD | SROM_SR, addr); - - srom_latch(SROM_RD | SROM_SR | DT_CS, addr); - srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data(SROM_RD | SROM_SR | DT_CS, addr); -} - -static void -srom_latch(u_int command, u_long addr) -{ - sendto_srom(command, addr); - sendto_srom(command | DT_CLK, addr); - sendto_srom(command, addr); - - return; -} - -static void -srom_command(u_int command, u_long addr) -{ - srom_latch(command, addr); - srom_latch(command, addr); - srom_latch((command & 0x0000ff00) | DT_CS, addr); - - return; -} - -static void -srom_address(u_int command, u_long addr, u_char offset) -{ - int i; - signed char a; - - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) { - srom_latch(command | ((a < 0) ? DT_IN : 0), addr); - } - udelay(1); - - i = (getfrom_srom(addr) >> 3) & 0x01; - - return; -} - -static short -srom_data(u_int command, u_long addr) -{ - int i; - short word = 0; - s32 tmp; - - for (i=0; i<16; i++) { - sendto_srom(command | DT_CLK, addr); - tmp = getfrom_srom(addr); - sendto_srom(command, addr); - - word = (word << 1) | ((tmp >> 3) & 0x01); - } - - sendto_srom(command & 0x0000ff00, addr); - - return word; -} - -static void -sendto_srom(u_int command, u_long addr) -{ - outl(command, addr); - udelay(1); - - return; -} - -static int -getfrom_srom(u_long addr) -{ - s32 tmp; - - tmp = inl(addr); - udelay(1); - - return tmp; -} - diff --git a/board/eltec/bab750/mpc106_pci.c b/board/eltec/bab750/mpc106_pci.c index 2b47c85..0f76d11 100644 --- a/board/eltec/bab750/mpc106_pci.c +++ b/board/eltec/bab750/mpc106_pci.c @@ -30,24 +30,10 @@ #include #include #include +#include #ifdef CONFIG_PCI -/* - * These are the lowest addresses allowed for PCI configuration. - * They correspond to lowest available I/O and Memory addresses. - * In the case where where multiple PMM regs are being used to map - * different PLB to PCI regions, each region should have it's own - * minimum address. - */ -unsigned long LowestMemAddr1 = CFG_MIN_PCI_MEMADDR1; -unsigned long LowestMemAddr2 = CFG_MIN_PCI_MEMADDR2; -unsigned long LowestIOAddr = CFG_PCI_PCI_IOADDR; - -unsigned long MaxBusNum = 0; - -unsigned char ShortPCIListing = 0; - /* * Subroutine: pci_init * @@ -58,34 +44,86 @@ unsigned char ShortPCIListing = 0; * Return: None * */ -void pci_init(bd_t *bd) + +void pci_mpc106_init(bd_t *bd, struct pci_controller *hose) { - unsigned int pcicmd; - unsigned int pcistat; - unsigned int picr1; - unsigned int picr2; + unsigned short pcicmd, pcistat; + unsigned int picr1, picr2; unsigned int pvr = get_pvr(); + int reg_num = 0; puts("PCI: "); - picr2 = PCI_Read_CFG_Reg(PCIDEVID_MPC106, PCI_PICR2, 4); + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + reg_num++, + MPC106_PCI_MEMORY_BUS, + MPC106_PCI_MEMORY_PHYS, + MPC106_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + reg_num++, + MPC106_PCI_MEM_BUS, + MPC106_PCI_MEM_PHYS, + MPC106_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MPC106_PCI_IO_BUS, + MPC106_PCI_IO_PHYS, + MPC106_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MPC106_ISA_IO_BUS, + MPC106_ISA_IO_PHYS, + MPC106_ISA_IO_SIZE, + PCI_REGION_IO); + +#ifndef CFG_ADDRESS_MAP_A + /* ISA/PCI memory space */ + pci_set_region(hose->regions + reg_num++, + MPC106_ISA_MEM_BUS, + MPC106_ISA_MEM_PHYS, + MPC106_ISA_MEM_SIZE, + PCI_REGION_MEM); +#endif + + hose->region_count = reg_num; + + pci_setup_indirect(hose, + MPC106_REG_ADDR, + MPC106_REG_DATA); + + pci_register_hose(hose); + + /* + * + */ + + pci_hose_read_config_dword(hose, PCIDEVID_MPC106, PCI_PICR2, &picr2); picr2 |= PICR2_CF_SNOOP_WS(3) | PICR2_CF_FLUSH_L2 | PICR2_CF_L2_HIT_DELAY(3) | PICR2_CF_APHASE_WS(3); picr2 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN); - PCI_Write_CFG_Reg(PCIDEVID_MPC106, PCI_PICR2, picr2, 4); + pci_hose_write_config_dword(hose, PCIDEVID_MPC106, PCI_PICR2, picr2); - pcicmd = PCI_Read_CFG_Reg(PCIDEVID_MPC106, PCI_CFG_COMMAND, 2); + pci_hose_read_config_word(hose, PCIDEVID_MPC106, PCI_COMMAND, &pcicmd); pcicmd |= (CMD_SERR | PCI_CMD_MASTER | PCI_CMD_MEMEN); - PCI_Write_CFG_Reg(PCIDEVID_MPC106, PCI_CFG_COMMAND, pcicmd, 2); + pci_hose_write_config_word(hose, PCIDEVID_MPC106, PCI_COMMAND, pcicmd); /* clear non-reserved bits in status register */ - pcistat = PCI_Read_CFG_Reg(PCIDEVID_MPC106, PCI_CFG_STATUS, 2); + pci_hose_read_config_word(hose, PCIDEVID_MPC106, PCI_STATUS, &pcistat); pcistat |= PCI_STAT_NO_RSV_BITS; - PCI_Write_CFG_Reg(PCIDEVID_MPC106, PCI_CFG_STATUS, pcistat, 2); + pci_hose_write_config_word(hose, PCIDEVID_MPC106, PCI_STATUS, pcistat); - picr1 = PCI_Read_CFG_Reg(PCIDEVID_MPC106, PCI_PICR1, 4); + pci_hose_read_config_dword(hose, PCIDEVID_MPC106, PCI_PICR1, &picr1); if (PVR_VER(pvr) == 0x0008) picr1 |= PICR1_PROC_TYPE_603; else @@ -94,775 +132,29 @@ void pci_init(bd_t *bd) picr1 |= PICR1_CF_CBA(63) | PICR1_CF_BREAD_WS(2); picr1 |= PICR1_MCP_EN | PICR1_CF_DPARK | PICR1_CF_LOOP_SNOOP | PICR1_CF_APARK; - PCI_Write_CFG_Reg(PCIDEVID_MPC106, PCI_PICR1, picr1, 4); + pci_hose_write_config_dword(hose, PCIDEVID_MPC106, PCI_PICR1, picr1); #ifdef CONFIG_PCI_PNP - /* - * Scan the PCI bus and configure devices found. - */ puts("scanning bus for devices ..."); - - PCI_Scan(0); #endif /* CONFIG_PCI_PNP */ - puts("OK\n"); -} - -/* - * Subroutine: PCI_Scan - * - * Description: Scan through all allowable PCI IDs and configure - * those for which the vendor ID indicates there is a - * device present. Routine scans only function 0. - * - * Inputs: BusNum Bus number where scanning begins - * - * Return: Number of devices found on the bus. - * - */ -int PCI_Scan(int BusNum) -{ - int Device; - int Function; - int BusDevFunc; - int Found = 0; - unsigned int HeaderType = 0; - unsigned int VendorID = 0; - -#ifdef DEBUG - printf("Scanning PCI bus %d\n", BusNum); -#endif - - /* - * Start with device 0, the MPC106 is device 0. sr: 09-07-2001 - */ - for (Device = 0; Device < CFG_MAX_PCI_DEVICES; Device++) { - HeaderType = 0; - VendorID = 0; - for (Function = 0; Function < CFG_MAX_PCI_FUNCTIONS; Function++) { - /* - * If this is not a multi-function device, we skip the rest - */ - if (Function && !(HeaderType & 0x80)) - break; - - BusDevFunc = (BusNum << 16) | - (Device << 11) | - (Function << 8); - - VendorID = PCI_Read_CFG_Reg (BusDevFunc, - PCI_CFG_VENDOR_ID, 2); - if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) - continue; - - HeaderType = PCI_Read_CFG_Reg(BusDevFunc, - PCI_CFG_HEADER_TYPE, 1); -#ifdef DEBUG - printf("\nPCI Device %d Funtion %d is present\n", - Device, Function); -#endif - if (HeaderType & 0x01) { - /* PCI-PCI Bridge */ - PCI_Config_Bridge(BusDevFunc); - } else { - PCI_Config_Device(BusDevFunc, 6); - } - Found++; - } - } - return Found; -} - -/* - * Subroutine: PCI_Read_CFG_Reg - * - * Description: Read a PCI configuration register - * - * Inputs: BusDevFunc PCI Bus+Device+Function number - * Reg Configuration register number - * Width Number of bytes to read (1, 2, or 4) - * - * Return: Value of the configuration register read. - * For reads shorter than 4 bytes, return value - * is LSB-justified - */ -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width) -{ - unsigned int RegAddr; - - /* - * bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) - */ - RegAddr = MPC106_REG | ((Reg|BusDevFunc) & 0xFFFFFFFC); - - /* - * Write reg to PCI Config Address - */ - out32r(MPC106_REG_ADDR, RegAddr); - - /* - * Read reg value from PCI Config Data - */ - switch (Width) { - case 1: - return ((unsigned int) in8(MPC106_REG_DATA | (Reg & 0x3))); - case 2: - return ((unsigned int) in16r(MPC106_REG_DATA | (Reg & 0x3))); - case 4: - return (in32r(MPC106_REG_DATA | (Reg & 0x3))); - } - - return 0; /* not reached: just to satisfy the compiler */ -} - -/* - * Subroutine: PCI_Write_CFG_Reg - * - * Description: Write a PCI configuration register. - * - * Inputs: BusDevFunc PCI Bus+Device+Function number - * Reg Configuration register number - * Value Configuration register value - * Width Number of bytes to write (1, 2, or 4) - * - * Return: 0 Successful - * - */ -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width) -{ - unsigned int RegAddr; - - /* - * bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) - * (DWORD alignment) - */ - RegAddr = MPC106_REG | ((Reg|BusDevFunc) & 0xFFFFFFFC); - - /* - * Write reg to PCI Config Address - */ - out32r(MPC106_REG_ADDR, RegAddr); - - /* - * Perform a read to update the data register. - */ - in32r(MPC106_REG_DATA | (Reg & 0x3)); - - /* - * Write reg value to PCI Config Data - */ - switch (Width) { - case 1: out8 (MPC106_REG_DATA | (Reg & 0x3), - (unsigned char)(Value & 0xFF)); - break; - case 2: out16r (MPC106_REG_DATA | (Reg & 0x3), - (unsigned short)(Value & 0xFFFF)); - break; - case 4: out32r (MPC106_REG_DATA | (Reg & 0x3), Value); - break; - } - - return 0; -} - -/* - * Subroutine: PCI_Config_Device - * - * Description: Configure a PCI device by examining its I/O and memory - * address space needs and allocating address space to it by - * programming the address decoders in the Base Address Registers. - * - * Inputs: BusDevFunc Bus+Device+Function number - * NumBaseAddr Number of base address registers to - * configure - * - * Return: None - * - */ -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) -{ - int AddrSlot, i; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val; - - unsigned long pcicmd; - pcicmd = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - PCI_Write_CFG_Reg (BusDevFunc, PCI_CFG_COMMAND, - pcicmd & ~(PCI_CMD_MEMEN|PCI_CMD_IOEN), 2); - - for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) { - /* - * Write virtual address into register to check LSB. - * LSB == 1 => IO space, else memory space. - */ - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - 0xFFFFFFFF, 4); - - AddrDesc = PCI_Read_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - 4); - - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; /* 01/04/99 MCG */ - -#ifdef DEBUG - printf ("Read Base Addr Reg %d = 0x%08lx\n", - AddrSlot, AddrDesc); -#endif - - if ((AddrDesc & 1) == 1) { /* I/O space */ - AddrDesc &= 0xFFFFFFFC; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; -#ifdef DEBUG - printf(" PCI I/O space = 0x%lx bytes\n", AddrDesc); -#endif - for (AddrProg = CFG_PCI_PCI_IOADDR; - AddrProg < LowestIOAddr; - AddrProg += AddrDesc) { - ; /* empty */ - } - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - AddrProg, 4); -#ifdef DEBUG - printf(" PCI I/O addr = 0x%lx\n", AddrProg); -#endif - LowestIOAddr = AddrProg + AddrDesc; - } else { /* memory space */ - AddrDesc &= 0xFFFFFFF0; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; - - if ((unsigned long)AddrDesc < 4096) - AddrDesc = 4096; -#ifdef DEBUG - printf(" PCI memory space = 0x%lx bytes \n",AddrDesc); -#endif - for (AddrProg = CFG_MIN_PCI_MEMADDR1; - AddrProg < LowestMemAddr1; - AddrProg += AddrDesc) { - ; /* empty */ - } - - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - AddrProg, 4); -#ifdef DEBUG - printf(" PCI memory addr = 0x%lx\n", AddrProg); -#endif - LowestMemAddr1 = AddrProg + AddrDesc; - } - } - - /* - * Assign expansion ROM address - */ - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 0xFFFFFFFE, 4); - - AddrDesc = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - - if (AddrDesc != 0) { -#ifdef DEBUG - printf("Read Expansion ROM Addr Reg = 0x%08lx\n" , AddrDesc); -#endif - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; -#ifdef DEBUG - printf(" PCI Expansion ROM space = 0x%lx bytes\n", AddrDesc); -#endif - for (AddrProg = CFG_MIN_PCI_MEMADDR1; - AddrProg < LowestMemAddr1; - AddrProg += AddrDesc) { - ; /* empty */ - } - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, AddrProg, 4); -#ifdef DEBUG - printf(" PCI Expansion ROM addr = 0x%lx\n", AddrProg); -#endif - LowestMemAddr1 = AddrProg + AddrDesc; - } - - Min_Gnt_Val = 0x80; - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, Min_Gnt_Val, 1); /* - * Disable interrupt line, if device says it wants to use interrupts - */ - if (PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1) != 0) - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 0xFF, 1); - /* - * Enable i/o space and memory space on this device - */ - PCI_Write_CFG_Reg (BusDevFunc, PCI_CFG_COMMAND, - pcicmd | PCI_CMD_MEMEN | PCI_CMD_IOEN, 2); -} - -/* - * Subroutine: PCI_Config_Bridge - * - * Description: Configure a PCI-PCI bridge - * - * Inputs: BusDevFunc Bus+Device+Function number - * - * Return: None - * - */ -void PCI_Config_Bridge(int BusDevFunc) -{ - int SecondaryBus; - int PrimaryBus; - int CommandReg_Val; - int InitialLowestIOAddr, InitialLowestMemAddr; - int IOBase, MemBase; - int IOLimit, MemLimit; - - InitialLowestIOAddr = LowestIOAddr; - InitialLowestMemAddr = LowestMemAddr1; - - CommandReg_Val = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - - /* Configure bridge's base address registers */ - PCI_Config_Device(BusDevFunc, 2); - - /* - * PCI_config_device() for the bridge could have changed the values in - * LowestIOAddr and LowestMemAddr1, if the bridge itself uses - * I/O and/or memory space. - */ - if ( LowestIOAddr > InitialLowestIOAddr ) /* bridge uses IO space? */ - CommandReg_Val |= 0x01; /* enable I/O Space */ - - if ( LowestMemAddr1 > InitialLowestMemAddr ) /* bridge uses memory space? */ - CommandReg_Val |= 0x02; /* enable Memory Space */ - - PrimaryBus = (BusDevFunc >> 16) & 0xFF; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_PRIMARYBUS, PrimaryBus, 1); - - SecondaryBus = ++MaxBusNum; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SECONDARYBUS, SecondaryBus, 1); - - /* - * Start with max. possible value for subordinate bus number - * Later, after any additional child busses are found, we'll update this - */ - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, 0xFF, 1); - - /* IO Base must be on 4Kb boundary. Adjust if needed */ - if ((LowestIOAddr % 4096) != 0) - LowestIOAddr += 4096 - (LowestIOAddr % 4096); - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOBASE, - (LowestIOAddr>>8) & 0xF0, 1); - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOBASEUPPER16, - (LowestIOAddr>>16) & 0xFFFF, 2); - - IOBase = LowestIOAddr; - - /* Mem Base must be on 1 MB boundary. adjust if needed */ - if ((LowestMemAddr1 % 0x100000) != 0) - LowestMemAddr1 += 0x100000 - (LowestMemAddr1 % 0x100000); - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_MEMBASE, - (LowestMemAddr1>>16) & 0xFFF0, 2); - MemBase = LowestMemAddr1; - - /* - * secondary bus on this bridge - */ - PCI_Scan(SecondaryBus); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, MaxBusNum, 1); - - IOLimit = LowestIOAddr; - if (LowestIOAddr > IOBase) { /* IO space used on secondary bus? */ - CommandReg_Val |= 0x01; /* enable IO Space */ - IOLimit--; /* IOLimit is highest used address */ - } - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOLIMIT, - ((IOLimit)>>8) & 0xF0, 1); - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOLIMITUPPER16, - ((IOLimit)>>16) & 0xFFFF, 2); - - /* - * IOLIMIT is the starting address of a 4K block forwarded by the bridge. - * Round LowestIOAddr up to the next 4K boundary if IO space is enabled. - */ - if ((CommandReg_Val & 0x01) == 0x01) - LowestIOAddr = (IOLimit | 0xFFF) + 1; - - MemLimit = LowestMemAddr1; - if ( LowestMemAddr1 > MemBase ) { /* mem. space is used on secondary bus? */ - CommandReg_Val |= 0x02; /* enable Memory Space */ - MemLimit--; /* MemLimit is highest used address */ - } - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_MEMLIMIT, - ((MemLimit)>>16) & 0xFFF0, 2); - - /* - * MEMLIMIT is the starting address of a 1M block forwarded by the bridge. - * Round LowestMemAddr up to the next 1M boundary - * if Memory space is enabled. + * Scan the PCI bus and configure devices found. */ + hose->last_busno = pci_hose_scan(hose); - if ( (CommandReg_Val & 0x02) == 0x02 ) - LowestMemAddr1 = (MemLimit | 0xFFFFF) + 1; - - /* Enable Bus Master on secondary bus */ - CommandReg_Val |= 0x04; - - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, CommandReg_Val, 2); -} - -/* - * Subroutine: PCI_Find_Device - * - * Description: Locate a PCI device by vendor and device number on any bus. - * - * Inputs: VendorID Value of the device's Vendor ID field - * DeviceID Value of the device's Device ID field - * - * Return: < 0 Device not found - * (int) PCI Bus+Device+Function number - * - */ -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID) -{ - int Device; - int BusDevFunc; - int BusNum; - -#if CFG_SCSI_SCAN_BUS_REVERSE - for (BusNum = MaxBusNum; BusNum >= 0; BusNum--) { -#else - for (BusNum = 0; BusNum <= MaxBusNum; BusNum++) { -#endif - for (Device = 0; Device < CFG_MAX_PCI_DEVICES; Device++) { - BusDevFunc = (BusNum << 16) | (Device << 11); - - if (PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2) == VendorID - && PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2) == DeviceID) { - return (BusDevFunc); - } - } - } - return (-1); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCI) -/* - * Follows routines for the output of infos about devices on PCI bus. - */ - -/* - * Subroutine: do_pciinfo - * - * Description: Handler for 'pciinfo' command.. - * - * Inputs: argv[1] may contain the number of the bus to be scanned. - * Default is bus 0. - * - * Return: None - * - */ -void do_pciinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - char *s; - int bus_no = 0; - - if (argc == 2) - { - bus_no = (int)simple_strtoul(argv[1], NULL, 10); - } - - if ((s = getenv("pci_listing")) != NULL) - ShortPCIListing = (strcmp(s, "short") == 0) ? 1 : 0; - else - ShortPCIListing = 0; - - pciinfo(bus_no); -} - - -/* - * Subroutine: pciinfo - * - * Description: Show information about devices on PCI bus. - * Depending on the define CFG_SHORT_PCI_LISTING - * the output will be more or less exhaustive. - * - * Inputs: bus_no the number of the bus to be scanned. - * - * Return: None - * - */ -void pciinfo(int BusNum) -{ - int Device; - int Function; - unsigned int HeaderType; - unsigned int VendorID; - int BusDevFunc; - - printf("Scanning PCI devices on bus %d\n", BusNum); - - if (ShortPCIListing) { - printf("No. VendorId DeviceId Device Class Sub-Class\n"); - printf("________________________________________________________\n"); - } - - for (Device = 0; Device < CFG_MAX_PCI_DEVICES; Device++) { - HeaderType = 0; - VendorID = 0; - for (Function = 0; Function < CFG_MAX_PCI_FUNCTIONS; Function++) { - /* - * If this is not a multi-function device, we skip the rest. - */ - if (Function && !(HeaderType & 0x80)) - break; - - BusDevFunc = (BusNum << 16) | - (Device << 11) | - (Function << 8); - - VendorID = PCI_Read_CFG_Reg (BusDevFunc, PCI_CFG_VENDOR_ID, 2); - if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) - continue; - - HeaderType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - - if (ShortPCIListing) - printf("%02d.%d ", Device, Function); - else - printf("\nFound PCI device %d, function %d:\n", - Device, Function); - - PCI_Header_Show(BusDevFunc); - } - } + puts("OK\n"); } - /* - * Subroutine: PCI_Header_Show - * - * Description: Reads the header of the specified PCI device. - * - * Inputs: BusDevFunc Bus+Device+Function number - * - * Return: None * */ -void PCI_Header_Show(int BusDevFunc) -{ - PCI_HEADER_DEVICE headerDevice; - PCI_HEADER_BRIDGE headerBridge; - PCI_HEADER_DEVICE * pD = &headerDevice; - PCI_HEADER_BRIDGE * pB = &headerBridge; - - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - - if (pD->headerType & 0x01) { /* PCI-to-PCI bridge */ - pB->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pB->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pB->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pB->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 2); - pB->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pB->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pB->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pB->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pB->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pB->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pB->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pB->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pB->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pB->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pB->priBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRIMARY_BUS, 1); - pB->secBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SECONDARY_BUS, 1); - pB->subBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBORDINATE_BUS, 1); - pB->secLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_LATENCY, 1); - pB->ioBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE, 1); - pB->ioLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT, 1); - pB->secStatus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_STATUS, 2); - pB->memBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_BASE, 2); - pB->memLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_LIMIT, 2); - pB->preBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE, 2); - pB->preLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT, 2); - pB->preBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE_U, 4); - pB->preLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT_U, 4); - pB->ioBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE_U, 2); - pB->ioLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT_U, 2); - pB->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_ROM_BASE, 4); - pB->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_LINE, 1); - pB->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_PIN, 1); - pB->control = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRIDGE_CONTROL, 2); - PCI_Bheader_Print(pB); - } else { /* PCI device */ - pD->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pD->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pD->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pD->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 1); - pD->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pD->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pD->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pD->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pD->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pD->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pD->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pD->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pD->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pD->base2 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_2, 4); - pD->base3 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_3, 4); - pD->base4 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_4, 4); - pD->base5 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_5, 4); - pD->cis = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CIS, 4); - pD->subVendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_VENDER_ID, 2); - pD->subSystemId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_SYSTEM_ID, 2); - pD->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - pD->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 1); - pD->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1); - pD->minGrant = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MIN_GRANT, 1); - pD->maxLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MAX_LATENCY, 1); - PCI_Dheader_Print(pD); - } -} -static char *PCI_classes[] = { - "Build before PCI Rev2.0", - "Mass storage controller", - "Network controller ", - "Display controller ", - "Multimedia device ", - "Memory controller ", - "Bridge device ", - "Simple comm. controller", - "Base system peripheral ", - "Input device ", - "Docking station ", - "Processor ", - "Serial bus controller ", - "Reserved entry ", - "Does not fit any class " -}; - -/* - * Subroutine: PCI_Dheader_Print - * - * Description: Prints the header of the specified PCI device. - * - * Inputs: pD pointer to device header info - * - * Return: None - * - */ -void PCI_Dheader_Print(PCI_HEADER_DEVICE * pD) -{ - if (ShortPCIListing) { - printf("0x%.4x 0x%.4x %s 0x%.2x\n", - (ushort)pD->vendorId, - (ushort)pD->deviceId, - PCI_classes[(uchar)pD->classCode], - (uchar)pD->subClass); - } else { - printf(" vendor ID = 0x%.4x\n", (ushort)pD->vendorId); - printf(" device ID = 0x%.4x\n", (ushort)pD->deviceId); - printf(" command register = 0x%.4x\n", (ushort)pD->command); - printf(" status register = 0x%.4x\n", (ushort)pD->status); - printf(" revision ID = 0x%.2x\n", (uchar)pD->revisionId); - printf(" class code = 0x%.2x (%s)\n", - (uchar)pD->classCode, - PCI_classes[(int)pD->classCode]); - printf(" sub class code = 0x%.2x\n", (uchar)pD->subClass); - printf(" programming interface = 0x%.2x\n", (uchar)pD->progIf); - printf(" cache line = 0x%.2x\n", (uchar)pD->cacheLine); - printf(" latency time = 0x%.2x\n", (uchar)pD->latency); - printf(" header type = 0x%.2x\n", (uchar)pD->headerType); - printf(" BIST = 0x%.2x\n", (uchar)pD->bist); - printf(" base address 0 = 0x%.8x\n", pD->base0); - printf(" base address 1 = 0x%.8x\n", pD->base1); - printf(" base address 2 = 0x%.8x\n", pD->base2); - printf(" base address 3 = 0x%.8x\n", pD->base3); - printf(" base address 4 = 0x%.8x\n", pD->base4); - printf(" base address 5 = 0x%.8x\n", pD->base5); - printf(" cardBus CIS pointer = 0x%.8x\n", pD->cis); - printf(" sub system vendor ID = 0x%.4x\n", (ushort)pD->subVendorId); - printf(" sub system ID = 0x%.4x\n", (ushort)pD->subSystemId); - printf(" expansion ROM base address = 0x%.8x\n", pD->romBase); - printf(" interrupt line = 0x%.2x\n", (uchar)pD->intLine); - printf(" interrupt pin = 0x%.2x\n", (uchar)pD->intPin); - printf(" min Grant = 0x%.2x\n", (uchar)pD->minGrant); - printf(" max Latency = 0x%.2x\n", (uchar)pD->maxLatency); - } -} +static struct pci_controller hose; -/* - * Subroutine: PCI_Bheader_Print - * - * Description: Prints the header of the specified PCI-to-PCI bridge. - * - * Inputs: pB pointer to bridge header info - * - * Return: None - * - */ -void PCI_Bheader_Print (PCI_HEADER_BRIDGE * pB) +void pci_init(bd_t *bd) { - if (ShortPCIListing) { - printf("0x%.4x 0x%.4x %s 0x%.2x\n", - (ushort)pB->vendorId, - (ushort)pB->deviceId, - PCI_classes[(uchar)pB->classCode], - (uchar)pB->subClass); - } else { - printf (" vendor ID = 0x%.4x\n", (ushort)pB->vendorId); - printf (" device ID = 0x%.4x\n", (ushort)pB->deviceId); - printf (" command register = 0x%.4x\n", (ushort)pB->command); - printf (" status register = 0x%.4x\n", (ushort)pB->status); - printf (" revision ID = 0x%.2x\n", (uchar)pB->revisionId); - printf (" class code = 0x%.2x (%s)\n", - (uchar)pB->classCode, - PCI_classes[(int)pB->classCode]); - printf (" sub class code = 0x%.2x\n", (uchar)pB->subClass); - printf (" programming interface = 0x%.2x\n", (uchar)pB->progIf); - printf (" cache line = 0x%.2x\n", (uchar)pB->cacheLine); - printf (" latency time = 0x%.2x\n", (uchar)pB->latency); - printf (" header type = 0x%.2x\n", (uchar)pB->headerType); - printf (" BIST = 0x%.2x\n", (uchar)pB->bist); - printf (" base address 0 = 0x%.8x\n", pB->base0); - printf (" base address 1 = 0x%.8x\n", pB->base1); - printf (" primary bus number = 0x%.2x\n", (uchar)pB->priBus); - printf (" secondary bus number = 0x%.2x\n", (uchar)pB->secBus); - printf (" subordinate bus number = 0x%.2x\n", (uchar)pB->subBus); - printf (" secondary latency timer = 0x%.2x\n", (uchar)pB->secLatency); - printf (" IO base = 0x%.2x\n", (uchar)pB->ioBase); - printf (" IO limit = 0x%.2x\n", (uchar)pB->ioLimit); - printf (" secondary status = 0x%.4x\n", (ushort)pB->secStatus); - printf (" memory base = 0x%.4x\n", (ushort)pB->memBase); - printf (" memory limit = 0x%.4x\n", (ushort)pB->memLimit); - printf (" prefetch memory base = 0x%.4x\n", (ushort)pB->preBase); - printf (" prefetch memory limit = 0x%.4x\n", (ushort)pB->preLimit); - printf (" prefetch memory base upper = 0x%.8x\n", pB->preBaseUpper); - printf (" prefetch memory limit upper = 0x%.8x\n", pB->preLimitUpper); - printf (" IO base upper 16 bits = 0x%.4x\n", (ushort)pB->ioBaseUpper); - printf (" IO limit upper 16 bits = 0x%.4x\n", (ushort)pB->ioLimitUpper); - printf (" expansion ROM base address = 0x%.8x\n", pB->romBase); - printf (" interrupt line = 0x%.2x\n", (uchar)pB->intLine); - printf (" interrupt pin = 0x%.2x\n", (uchar)pB->intPin); - printf (" bridge control = 0x%.4x\n", (ushort)pB->control); - } + pci_mpc106_init(bd, &hose); } -#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ - #endif /* CONFIG_PCI */ diff --git a/board/eltec/bab750/ns16550.c b/board/eltec/bab750/ns16550.c deleted file mode 100644 index f2181c5..0000000 --- a/board/eltec/bab750/ns16550.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines - */ - -#include -#include "ns16550.h" - - -void -NS16550_init(volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; /* interrupt enable register */ - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -} - -void -NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -} - -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0) ; - com_port->thr = c; -} - -unsigned char -NS16550_getc(volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0) ; - return (com_port->rbr); -} - -int NS16550_tstc(volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} - - - diff --git a/board/eltec/bab750/ns16550.h b/board/eltec/bab750/ns16550.h deleted file mode 100644 index b694e86..0000000 --- a/board/eltec/bab750/ns16550.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - */ - - -struct NS16550 - { - unsigned char rbr; /* 0 Rx */ - unsigned char ier; /* 1 interrupt enable register, Divisor Latch High */ - unsigned char fcr; /* 2 fifo control rgister */ - unsigned char lcr; /* 3 line control register */ - unsigned char mcr; /* 4 modem control register */ - unsigned char lsr; /* 5 line status register */ - unsigned char msr; /* 6 modem status register */ - unsigned char scr; /* 7 scratch pad register */ - }; - -typedef struct NS16550 *NS16550_t; - -#define thr rbr /* Tx */ -#define iir fcr /* interrupt identification register */ -#define dll rbr /* divisor latch low */ -#define dlm ier /* divisor latch high */ - -#define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*reciever soft reset*/ -#define FCR_TXSR 0x04 /*transmitter soft reset*/ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask*/ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble*/ -#define LCR_EPS 0x10 /* Even Parity Select*/ -#define LCR_STKP 0x20 /* Stick Parity*/ -#define LCR_SBRK 0x40 /* Set Break*/ -#define LCR_BKSE 0x80 /* Bank select enable*/ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -void NS16550_init(volatile struct NS16550 *com_port, int baud_divisor); -void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc(volatile struct NS16550 *com_port); -int NS16550_tstc(volatile struct NS16550 *com_port); - diff --git a/board/eltec/bab750/ns87308.c b/board/eltec/bab750/ns87308.c deleted file mode 100644 index 2720e60..0000000 --- a/board/eltec/bab750/ns87308.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * 09-18-2001 Andreas Heppel, Sysgo RTS GmbH: - * Added initialisation of additional logical devices on the chip. - */ - -#include - -#include "ns87308.h" -#include "ns16550.h" /* to configure the 87308's internal 16550's */ -#include /* to configure 87308's RTC */ - -void initialise_ns87308 (void) -{ - unsigned char data; - - /* - * Switch floppy drive to PS/2 mode. - */ - read_pnp_config(SUPOERIO_CONF1, &data); - data &= 0xFB; - write_pnp_config(SUPOERIO_CONF1, data); - - PNP_SET_DEVICE_BASE(LDEV_UART1, COM1); - PNP_SET_DEVICE_BASE(LDEV_UART2, COM2); - - PNP_SET_DEVICE_BASE(LDEV_KBC1, KBC1_BASE); - write_pnp_config(LUN_CONFIG_REG, 0); - write_pnp_config(CBASE_HIGH, 0x00); - write_pnp_config(CBASE_LOW, 0x64); - - PNP_ACTIVATE_DEVICE(LDEV_MOUSE); - - PNP_SET_DEVICE_BASE(LDEV_FDC, FDC_BASE); - write_pnp_config(LUN_CONFIG_REG, 0x40); - - PNP_SET_DEVICE_BASE(LDEV_PARP, LPT_BASE); - PNP_SET_DEVICE_BASE(LDEV_GPIO, GPIO_BASE); - - PNP_SET_DEVICE_BASE(LDEV_RTC_APC, RTC_PORT(0)); - PNP_SET_DEVICE_BASE(LDEV_POWRMAN, PWMAN_BASE); - - /* Enable all units */ - pci_writeb(0x00, CFG_ISA_IO + PWMAN_BASE); - eieio(); - pci_writeb(0x7d, CFG_ISA_IO + PWMAN_BASE + 1); - - pci_writeb(0x01, CFG_ISA_IO + PWMAN_BASE); - eieio(); - pci_writeb(0x87, CFG_ISA_IO + PWMAN_BASE + 1); - - /* SuperI/O clock source is 24MHz via X1 */ - pci_writeb(0x03, CFG_ISA_IO + PWMAN_BASE); - eieio(); - pci_writeb(0x00, CFG_ISA_IO + PWMAN_BASE + 1); - - /* - * set up the NVRAM access registers - * NVRAM's controlled by the configurable CS line from the 87308 - */ - PNP_PGCS_CSLINE_BASE(0, 0x76); - PNP_PGCS_CSLINE_CONF(0, 0x40); - PNP_PGCS_CSLINE_BASE(1, 0x70); - PNP_PGCS_CSLINE_CONF(1, 0x1C); - PNP_PGCS_CSLINE_BASE(2, 0x71); - PNP_PGCS_CSLINE_CONF(2, 0x1C); -} diff --git a/board/eltec/bab750/serial.c b/board/eltec/bab750/serial.c deleted file mode 100644 index d9f0bba..0000000 --- a/board/eltec/bab750/serial.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include "config.h" -#include "ns16550.h" -#include "ns87308.h" - -/* - * Minimal serial functions needed to use one87308's UARTs - * as serial console interface. - */ - -#if (CONFIG_CONS_INDEX == 1) -#define console (CFG_ISA_IO + COM1) -#elif (CONFIG_CONS_INDEX == 2) -#define console (CFG_ISA_IO + COM2) -#else -#error "Invalid COM port for console output (must be 1 or 2)." -#endif - -void -serial_init (unsigned long dummy, int baudrate) -{ - int clock_divisor = 115200/baudrate; - - initialise_ns87308(); - - NS16550_init((NS16550_t)console, clock_divisor); -} - -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)console, '\r'); - - NS16550_putc((NS16550_t)console, c); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - - -int -serial_getc(void) -{ - return NS16550_getc((NS16550_t)console); -} - -int -serial_tstc(void) -{ - return NS16550_tstc((NS16550_t)console); -} - -void -serial_setbrg (unsigned long dummy, int baudrate) -{ - int clock_divisor = 115200/baudrate; - NS16550_reinit((NS16550_t)console, clock_divisor); -} diff --git a/board/eltec/bab750/speed.c b/board/eltec/bab750/speed.c index 6e30147..95eaf56 100644 --- a/board/eltec/bab750/speed.c +++ b/board/eltec/bab750/speed.c @@ -28,7 +28,7 @@ #include #include -#include "ns87308.h" +#include /* Access functions for the Machine State Register */ @@ -52,7 +52,7 @@ ulong get_bus_freq (ulong ignore) /* * The GPIO Port 1 on BAB750 reflects the bus speed. */ - volatile struct GPIO *gpio = (struct GPIO *)(CFG_ISA_IO + GPIO_BASE); + volatile struct GPIO *gpio = (struct GPIO *)(CFG_ISA_IO + CFG_NS87308_GPIO_BASE); unsigned char data = gpio->dta1; diff --git a/board/eltec/bab750/sym53c8xx.c b/board/eltec/bab750/sym53c8xx.c deleted file mode 100644 index 134a035..0000000 --- a/board/eltec/bab750/sym53c8xx.c +++ /dev/null @@ -1,785 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * partly derived from - * linux/drivers/scsi/sym53c8xx.c - * - */ - -/* - * SCSI support based on the chip sym53C810. - * - * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH - * The local version of this driver for the BAB750 board does not - * use interrupts but polls the chip instead (see the call of - * 'handle_scsi_int()' in 'scsi_issue()'. - */ - -#include -#include -#include -#include -#include -#include "sym53c8xx.h" -#include - -#undef SYM53C8XX_DEBUG - -#ifdef SYM53C8XX_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) - - -#undef SCSI_SINGLE_STEP -/* - * Single Step is only used for debug purposes - */ -#ifdef SCSI_SINGLE_STEP -static unsigned long start_script_select; -static unsigned long start_script_msgout; -static unsigned long start_script_msgin; -static unsigned long start_script_msg_ext; -static unsigned long start_script_cmd; -static unsigned long start_script_data_in; -static unsigned long start_script_data_out; -static unsigned long start_script_status; -static unsigned long start_script_complete; -static unsigned long start_script_error; -static unsigned long start_script_reselection; -static unsigned int len_script_select; -static unsigned int len_script_msgout; -static unsigned int len_script_msgin; -static unsigned int len_script_msg_ext; -static unsigned int len_script_cmd; -static unsigned int len_script_data_in; -static unsigned int len_script_data_out; -static unsigned int len_script_status; -static unsigned int len_script_complete; -static unsigned int len_script_error; -static unsigned int len_script_reselection; -#endif - - -static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ -static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ -static unsigned long script_select[8]; /* script for selection */ -static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ -static unsigned long script_msgin[14]; /* script for message in phase */ -static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ -static unsigned long script_cmd[18]; /* script for command phase */ -static unsigned long script_data_in[8]; /* script for data in phase */ -static unsigned long script_data_out[8]; /* script for data out phase */ -static unsigned long script_status[6]; /* script for status phase */ -static unsigned long script_complete[10]; /* script for complete */ -static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ -static unsigned long script_error[2]; /* script for error handling */ - -static unsigned long int_stat[3]; /* interrupt status */ -static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ - - -#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ - -#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ -#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ - -/********************************************************************************* - * forward declerations - */ - -void scsi_chip_init(void); -void handle_scsi_int(void); - - -/******************************************************************************** - * reports SCSI errors to the user - */ -void scsi_print_error(ccb *pccb) -{ - int i; - printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); - printf(" CCB: "); - for(i=0;icmdlen;i++) - printf("%02X ",pccb->cmd[i]); - printf("(len=%d)\n",pccb->cmdlen); - printf(" Cntrl: "); - switch(pccb->contr_stat) { - case SIR_COMPLETE: printf("Complete (no Error)\n"); break; - case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; - case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; - case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; - case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; - case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; - case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; - case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; - case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; - case INT_ON_FY: printf("Interrupt on fly\n"); break; - case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; - case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; - case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; - case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; - default: printf("unknown status %lx\n",pccb->contr_stat); break; - } - printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); - switch(pccb->sense_buf[2]&0xf) { - case SENSE_NO_SENSE: printf("No Sense)"); break; - case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; - case SENSE_NOT_READY: printf("Not Ready)"); break; - case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; - case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; - case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; - case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; - case SENSE_DATA_PROTECT: printf("Data Protect)"); break; - case SENSE_BLANK_CHECK: printf("Blank check)"); break; - case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; - case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; - case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; - case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; - case SENSE_MISCOMPARE: printf("Misscompare\n"); break; - default: printf("Illegal Sensecode\n"); break; - } - printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); - printf(" Status: "); - switch(pccb->status) { - case S_GOOD : printf("Good\n"); break; - case S_CHECK_COND: printf("Check condition\n"); break; - case S_COND_MET: printf("Condition Met\n"); break; - case S_BUSY: printf("Busy\n"); break; - case S_INT: printf("Intermediate\n"); break; - case S_INT_COND_MET: printf("Intermediate condition met\n"); break; - case S_CONFLICT: printf("Reservation conflict\n"); break; - case S_TERMINATED: printf("Command terminated\n"); break; - case S_QUEUE_FULL: printf("Task set full\n"); break; - default: printf("unknown: %02X\n",pccb->status); break; - } - -} - - - -/****************************************************************************** - * sets-up the SCSI controller - * the base memory address is retrived via the PCI_Read_CFG_Reg - */ -void scsi_low_level_init(int busdevfunc) -{ - unsigned long cmd; - unsigned long addr; - unsigned char vec; - vec=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_DEV_INT_LINE, 1); - addr=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_BASE_ADDRESS_1, 4); - - addr |= CFG_60X_PCI_MEM_OFFSET; - /* - * Enable bus mastering in case this has not been done, yet. - */ - cmd=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_COMMAND, 4); - cmd |= PCI_CMD_MASTER; - PCI_Write_CFG_Reg(busdevfunc, PCI_CFG_COMMAND, cmd, 4); - - scsi_mem_addr=addr; - scsi_chip_init(); - scsi_bus_reset(); -} - - -/************************************************************************************ - * Low level Part of SCSI Driver - */ - -/* - * big-endian -> little endian conversion for the script - */ -unsigned long swap_script(unsigned long val) -{ - unsigned long tmp; - tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); - return tmp; -} - - -void scsi_write_byte(ulong offset,unsigned char val) -{ - out8(scsi_mem_addr+offset,val); -} - - -unsigned char scsi_read_byte(ulong offset) -{ - return(in8(scsi_mem_addr+offset)); -} - - -/******************************************************************************** - * interrupt handler - */ -void handle_scsi_int(void) -{ - unsigned char stat,stat1,stat2; - unsigned short sstat; - int i; -#ifdef SCSI_SINGLE_STEP - unsigned long tt; -#endif - stat=scsi_read_byte(ISTAT); - if((stat & DIP)==DIP) { /* DMA Interrupt pending */ - stat1=scsi_read_byte(DSTAT); -#ifdef SCSI_SINGLE_STEP - if((stat1 & SSI)==SSI) - { - tt=in32r(scsi_mem_addr+DSP); - if(((tt)>=start_script_select) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_msgout) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_msgin) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_msg_ext) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_cmd) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_data_in) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_data_out) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_status) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_complete) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_error) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_reselection) && ((tt)>2); - goto end_single; - } - printf("sc: %lx\n",tt); -end_single: - stat2=scsi_read_byte(DCNTL); - stat2|=STD; - scsi_write_byte(DCNTL,stat2); - } -#endif - if((stat1 & SIR)==SIR) /* script interrupt */ - { - int_stat[0]=in32(scsi_mem_addr+DSPS); - } - if((stat1 & DFE)==0) { /* fifo not epmty */ - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ - stat2=scsi_read_byte(STEST3); - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ - } - } - if((stat & SIP)==SIP) { /* scsi interrupt */ - sstat = (unsigned short)scsi_read_byte(SIST+1); - sstat <<=8; - sstat |= (unsigned short)scsi_read_byte(SIST); - for(i=0;i<3;i++) { - if(int_stat[i]==0) - break; /* found an empty int status */ - } - int_stat[i]=SCSI_INT_STATE | sstat; - stat1=scsi_read_byte(DSTAT); - if((stat1 & DFE)==0) { /* fifo not epmty */ - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ - stat2=scsi_read_byte(STEST3); - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ - } - } - if((stat & INTF)==INTF) { /* interrupt on Fly */ - scsi_write_byte(ISTAT,stat); /* clear it */ - for(i=0;i<3;i++) { - if(int_stat[i]==0) - break; /* found an empty int status */ - } - int_stat[i]=INT_ON_FY; - } -} - -void scsi_bus_reset(void) -{ - unsigned char t; - int i; - int end = CFG_SCSI_SPIN_UP_TIME*1000; - - t=scsi_read_byte(SCNTL1); - scsi_write_byte(SCNTL1,(t | CRST)); - udelay(50); - scsi_write_byte(SCNTL1,t); - - puts("SCSI: waiting for devices to spin up"); - for(i=0;i>8)); - scsi_write_byte(DIEN,script_int_mask); -} - -void scsi_write_dsp(unsigned long start) -{ - unsigned long val; -#ifdef SCSI_SINGLE_STEP - unsigned char t; -#endif - val = start; - out32r(scsi_mem_addr + DSP,start); -#ifdef SCSI_SINGLE_STEP - t=scsi_read_byte(DCNTL); - t|=STD; - scsi_write_byte(DCNTL,t); -#endif -} - -/* only used for debug purposes */ -void scsi_print_script(void) -{ - printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); - printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); - printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); - printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); - printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); - printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); - printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); - printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); - printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); - printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); -} - - - -void scsi_set_script(ccb *pccb) -{ - int i; - i=0; - script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); - script_select[i++]=0; /* LED ON */ - script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ - script_select[i++]=0; - /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ - script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); - script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */ - script_select[i++]=swap_script(SCR_JUMP); /* next section */ - /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ - script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */ - -#ifdef SCSI_SINGLE_STEP - start_script_select=(unsigned long)&script_select[0]; - len_script_select=i*4; -#endif - - i=0; - script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); - script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; - script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); - script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0])); - script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ - script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */ - script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ - script_msgout[i++]=SIR_MSG_OUT_NO_CMD; - -#ifdef SCSI_SINGLE_STEP - start_script_msgout=(unsigned long)&script_msgout[0]; - len_script_msgout=i*4; -#endif - i=0; - script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); - script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_status[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); - script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ - script_cmd[i++]=SIR_CMD_OUT_ILL_PH; -#ifdef SCSI_SINGLE_STEP - start_script_cmd=(unsigned long)&script_cmd[0]; - len_script_cmd=i*4; -#endif - i=0; - script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ - script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ - script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); - script_data_out[i++]=swap_script(phys_to_bus(&script_status[0])); - script_data_out[i++]=swap_script(SCR_INT); - script_data_out[i++]=SIR_DATA_OUT_ERR; - -#ifdef SCSI_SINGLE_STEP - start_script_data_out=(unsigned long)&script_data_out[0]; - len_script_data_out=i*4; -#endif - i=0; - script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ - script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ - script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); - script_data_in[i++]=swap_script(phys_to_bus(&script_status[0])); - script_data_in[i++]=swap_script(SCR_INT); - script_data_in[i++]=SIR_DATA_IN_ERR; -#ifdef SCSI_SINGLE_STEP - start_script_data_in=(unsigned long)&script_data_in[0]; - len_script_data_in=i*4; -#endif - i=0; - script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); - script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); - script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0])); - script_msgin[i++]=swap_script(SCR_INT); - script_msgin[i++]=SIR_MSG_RECEIVED; -#ifdef SCSI_SINGLE_STEP - start_script_msgin=(unsigned long)&script_msgin[0]; - len_script_msgin=i*4; -#endif - i=0; - script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ - script_msg_ext[i++]=0; - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_INT); - script_msg_ext[i++]=SIR_MSG_OVER7; -#ifdef SCSI_SINGLE_STEP - start_script_msg_ext=(unsigned long)&script_msg_ext[0]; - len_script_msg_ext=i*4; -#endif - i=0; - script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); - script_status[i++]=swap_script(phys_to_bus(&pccb->status)); - script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); - script_status[i++]=swap_script(phys_to_bus(&script_msgin[0])); - script_status[i++]=swap_script(SCR_INT); - script_status[i++]=SIR_STATUS_ILL_PH; -#ifdef SCSI_SINGLE_STEP - start_script_status=(unsigned long)&script_status[0]; - len_script_status=i*4; -#endif - i=0; - script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_WAIT_DISC); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); - script_complete[i++]=0; /* LED OFF */ - script_complete[i++]=swap_script(SCR_INT); - script_complete[i++]=SIR_COMPLETE; -#ifdef SCSI_SINGLE_STEP - start_script_complete=(unsigned long)&script_complete[0]; - len_script_complete=i*4; -#endif - i=0; - script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ - script_error[i++]=SIR_SCRIPT_ERROR; -#ifdef SCSI_SINGLE_STEP - start_script_error=(unsigned long)&script_error[0]; - len_script_error=i*4; -#endif - i=0; - script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ - script_reselection[i++]=0; - script_reselection[i++]=swap_script(SCR_WAIT_RESEL); - script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */ -#ifdef SCSI_SINGLE_STEP - start_script_reselection=(unsigned long)&script_reselection[0]; - len_script_reselection=i*4; -#endif -} - - - -void scsi_issue(ccb *pccb) -{ - int i; - unsigned short sstat; - int retrycnt; /* retry counter */ - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - /* struct pccb must be set-up correctly */ - retrycnt=0; - PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); - pccb->trans_bytes=0; /* no bytes transfered yet */ - scsi_set_script(pccb); /* fill in SCRIPT */ - scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */ - script_int_mask=0xff; /* enable all Ints */ - scsi_int_enable(); - scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */ - /* now we have to wait for IRQs */ -retry: - /* - * This version of the driver is _not_ interrupt driven, - * but polls the chip's interrupt registers (ISTAT, DSTAT). - */ - while(int_stat[0]==0) - handle_scsi_int(); - - if(int_stat[0]==SIR_COMPLETE) { - if(pccb->msgin[0]==M_DISCONNECT) { - PRINTF("Wait for reselection\n"); - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */ - goto retry; - } - pccb->contr_stat=SIR_COMPLETE; - return; - } - if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ - sstat=(unsigned short)int_stat[0]; - if((sstat & STO)==STO) { /* selection timeout */ - pccb->contr_stat=SCSI_SEL_TIME_OUT; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Selection Timeout\n",pccb->target); - return; - } - if((sstat & UDC)==UDC) { /* unexpected disconnect */ - pccb->contr_stat=SCSI_UNEXP_DIS; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); - return; - } - if((sstat & RSL)==RSL) { /* reselection */ - pccb->contr_stat=SCSI_UNEXP_DIS; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); - return; - } - if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ - if(retrycnttrans_bytes=pccb->datalen - - ((unsigned long)scsi_read_byte(DBC) | - ((unsigned long)scsi_read_byte(DBC+1)<<8) | - ((unsigned long)scsi_read_byte(DBC+2)<<16)); - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - retrycnt++; - PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", - pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); - scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */ - goto retry; - } - if((sstat & MA)==MA) - pccb->contr_stat=SCSI_MA_TIME_OUT; - else - pccb->contr_stat=SCSI_HNS_TIME_OUT; - PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); - return; - } /* no phase int */ -/* if((sstat & CMP)==CMP) { - pccb->contr_stat=SIR_COMPLETE; - return; - } -*/ - PRINTF("SCSI INT %lX\n",int_stat[0]); - pccb->contr_stat=int_stat[0]; - return; - } /* end scsi int */ - PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); - pccb->contr_stat=int_stat[0]; - return; -} - -int scsi_exec(ccb *pccb) -{ - unsigned char tmpcmd[16],tmpstat; - int i,retrycnt,t; - unsigned long transbytes,datalen; - unsigned char *tmpptr; - retrycnt=0; -retry: - scsi_issue(pccb); - if(pccb->contr_stat!=SIR_COMPLETE) - return FALSE; - if(pccb->status==S_GOOD) - return TRUE; - if(pccb->status==S_CHECK_COND) { /* check condition */ - for(i=0;i<16;i++) - tmpcmd[i]=pccb->cmd[i]; - pccb->cmd[0]=SCSI_REQ_SENSE; - pccb->cmd[1]=pccb->lun<<5; - pccb->cmd[2]=0; - pccb->cmd[3]=0; - pccb->cmd[4]=14; - pccb->cmd[5]=0; - pccb->cmdlen=6; - pccb->msgout[0]=SCSI_IDENTIFY; - transbytes=pccb->trans_bytes; - tmpptr=pccb->pdata; - pccb->pdata=&pccb->sense_buf[0]; - datalen=pccb->datalen; - pccb->datalen=14; - tmpstat=pccb->status; - scsi_issue(pccb); - for(i=0;i<16;i++) - pccb->cmd[i]=tmpcmd[i]; - pccb->trans_bytes=transbytes; - pccb->pdata=tmpptr; - pccb->datalen=datalen; - pccb->status=tmpstat; - PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, - pccb->sense_buf[12],pccb->sense_buf[13]); - switch(pccb->sense_buf[2]&0xf) { - case SENSE_NO_SENSE: - case SENSE_RECOVERED_ERROR: - /* seems to be ok */ - return TRUE; - break; - case SENSE_NOT_READY: - if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { - /* if device is not in process of becoming ready */ - return FALSE; - break; - } /* else fall through */ - case SENSE_UNIT_ATTENTION: - if(retrycnttarget,retrycnt); - for(t=0;ttarget,retrycnt); - return FALSE; - default: - return FALSE; - } - } - PRINTF("Status = %X\n",pccb->status); - return FALSE; -} - - - - -void scsi_chip_init(void) -{ - /* first we issue a soft reset */ - scsi_write_byte(ISTAT,SRST); - udelay(1000); - scsi_write_byte(ISTAT,0); - /* setup chip */ - scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ - scsi_write_byte(SCNTL1,0x00); - scsi_write_byte(SCNTL2,0x00); - scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ - scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ - scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ - scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ - scsi_int_mask=0x0000; /* no Interrupt is enabled */ - script_int_mask=0x00; - scsi_int_enable(); - scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ - scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ - scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ - scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ - scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ - scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ - scsi_write_byte(STEST3,0x80); /* enable tolerANT */ - scsi_write_byte(CTEST3,0x04); /* clear FIFO */ - scsi_write_byte(CTEST4,0x00); - scsi_write_byte(CTEST5,0x00); -#ifdef SCSI_SINGLE_STEP -/* scsi_write_byte(DCNTL,IRQM | SSM); */ - scsi_write_byte(DCNTL,IRQD | SSM); - scsi_write_byte(DMODE,MAN); -#else -/* scsi_write_byte(DCNTL,IRQM); */ - scsi_write_byte(DCNTL,IRQD); - scsi_write_byte(DMODE,0x00); -#endif -} -#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ - - diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile index 4e444f2..d4a4e65 100644 --- a/board/esd/adciop/Makefile +++ b/board/esd/adciop/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ../common/dc2114x.o pci.o +OBJS = $(BOARD).o flash.o ../common/pci.o $(LIB): $(OBJS) $(AR) crv $@ $^ diff --git a/board/esd/adciop/pci.c b/board/esd/adciop/pci.c deleted file mode 100644 index 7386a72..0000000 --- a/board/esd/adciop/pci.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -/* PCI Registers. - */ -#define PCI_VENDOR_ID 0x00 -#define PCI_COMMAND 0x04 -#define PCI_CLASS_REVISION 0x08 -#define PCI_LATENCY_TIMER 0x0d -#define PCI_BASE_ADDRESS_0 0x10 -#define PCI_BASE_ADDRESS_1 0x14 -#define PCI_BASE_ADDRESS_2 0x18 -#define PCI_CFDA_PSM 0x43 - -#define PCI_COMMAND_IO 0x1 -#define PCI_COMMAND_MEM 0x2 -#define PCI_COMMAND_MASTER 0x4 - -#define CBIO_MASK -128 - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Read_CFG_Reg -| Description: Read a PCI configuration register -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Width Number of bytes to read (1, 2, or 4) -| Return value: -| (unsigned int) Value of the configuration register read. -| For reads shorter than 4 bytes, return value -| is LSB-justified -+-----------------------------------------------------------------------------*/ -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width) -{ - unsigned long conAdrVal; - unsigned long val; - unsigned long Value = 0; - - /* generate coded value for CON_ADR register */ - - conAdrVal = BusDevFunc | (Reg & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - /* shift to position */ - switch (Width) - { - case 1: - val >>= ((Reg & 0x03) * 8); - val &= 0xff; - Value = (unsigned char) val; - break; - case 2: - val >>= ((Reg & (int)(0x02) ) * 8); - val &= 0xffff; - Value = (unsigned short) val; - break; - case 4: - Value = (unsigned long) val; - break; - } - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return (Value); -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Write_CFG_Reg -| Description: Write a PCI configuration register. -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Value Configuration register value -| Width Number of bytes to write (1, 2, or 4) -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width) -{ - unsigned long conAdrVal; - unsigned long val; - - conAdrVal = BusDevFunc | (Reg & 0xfc) | 0x80000000; - - /* shift to position */ - { - unsigned long ldata; - int mask; - - val = PCI_Read_CFG_Reg(BusDevFunc, Reg & ~3, 4); - - switch (Width) - { - case 1: - mask = 0x000000ff; - ldata = (((unsigned long)Value) & mask) << ((Reg & (int)0x03) * 8); - mask <<= ((Reg & 0x03) * 8); - Value = (val & ~mask) | ldata; - break; - case 2: - mask = 0x0000ffff; - ldata = (((unsigned long)Value) & mask) << ((Reg & (int)0x02) * 8); - mask <<= ((Reg & (int)0x02) * 8); - Value = (val & ~mask) | ldata; - break; - case 4: - break; - } - - } - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, Value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} diff --git a/board/esd/common/dc2114x.c b/board/esd/common/dc2114x.c deleted file mode 100644 index 3849bee..0000000 --- a/board/esd/common/dc2114x.c +++ /dev/null @@ -1,1063 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -/* phy seed setup */ -#define AUTO 99 -#define _100BASET 100 -#define _10BASET 10 -#define HALF 22 -#define FULL 44 - -/* phy register offsets */ -#define PHY_BMCR 0x00 -#define PHY_BMSR 0x01 -#define PHY_PHY1DR1 0x02 -#define PHY_PHYIDR2 0x03 -#define PHY_ANAR 0x04 -#define PHY_ANLPAR 0x05 -#define PHY_ANER 0x06 -#define PHY_ANNPTR 0x07 -#define PHY_PHYSTS 0x10 -#define PHY_MIPSCR 0x11 -#define PHY_MIPGSR 0x12 -#define PHY_DCR 0x13 -#define PHY_FCSCR 0x14 -#define PHY_RECR 0x15 -#define PHY_PCSR 0x16 -#define PHY_LBR 0x17 -#define PHY_10BTSCR 0x18 -#define PHY_PHYCTRL 0x19 - -/*phy ANLPAR */ -#define PHY_ANLPAR_NP 0x8000 -#define PHY_ANLPAR_ACK 0x4000 -#define PHY_ANLPAR_RF 0x2000 -#define PHY_ANLPAR_T4 0x0200 -#define PHY_ANLPAR_TXFD 0x0100 -#define PHY_ANLPAR_TX 0x0080 -#define PHY_ANLPAR_10FD 0x0040 -#define PHY_ANLPAR_10 0x0020 -#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ - -/* PCI Registers. - */ -#define PCI_VENDOR_ID 0x00 -#define PCI_COMMAND 0x04 -#define PCI_CLASS_REVISION 0x08 -#define PCI_LATENCY_TIMER 0x0d -#define PCI_BASE_ADDRESS_0 0x10 -#define PCI_BASE_ADDRESS_1 0x14 -#define PCI_BASE_ADDRESS_2 0x18 -#define PCI_CFDA_PSM 0x43 - -#define PCI_COMMAND_IO 0x1 -#define PCI_COMMAND_MEM 0x2 -#define PCI_COMMAND_MASTER 0x4 - -#define CFRV_RN 0x000000f0 /* Revision Number */ -#define CBIO_MASK -128 - -#define WAKEUP 0x00 /* Power Saving Wakeup */ -#define SLEEP 0x80 /* Power Saving Sleep Mode */ - - -#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ -#define DC2114x_DID 0x1900 /* Unique Device ID # */ -#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -#define DC21142 (DC2114x_DID | 0x0010) -#define DC21143 (DC2114x_DID | 0x0030) - -#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) - -/* Ethernet chip registers. - */ -#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */ -#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */ -#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */ -#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */ -#define DE4X5_STS iobase + 0x028 /* Status Register */ -#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */ -#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */ -#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */ - -/* Register bits. - */ -#define BMR_SWR 0x00000001 /* Software Reset */ -#define STS_TS 0x00700000 /* Transmit Process State */ -#define STS_RS 0x000e0000 /* Receive Process State */ -#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -#define OMR_SR 0x00000002 /* Start/Stop Receive */ -#define OMR_PS 0x00040000 /* Port Select */ -#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ -#define OMR_PM 0x00000080 /* Pass All Multicast */ - -/* Descriptor bits. - */ -#define R_OWN 0x80000000 /* Own Bit */ -#define RD_RER 0x02000000 /* Receive End Of Ring */ -#define RD_LS 0x00000100 /* Last Descriptor */ -#define RD_ES 0x00008000 /* Error Summary */ -#define TD_TER 0x02000000 /* Transmit End Of Ring */ -#define T_OWN 0x80000000 /* Own Bit */ -#define TD_LS 0x40000000 /* Last Segment */ -#define TD_FS 0x20000000 /* First Segment */ -#define TD_ES 0x00008000 /* Error Summary */ -#define TD_SET 0x08000000 /* Setup Packet */ - - -#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ -#define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define SROM_SR 0x00000800 /* Select Serial ROM when set */ - -#define DT_IN 0x00000004 /* Serial Data In */ -#define DT_CLK 0x00000002 /* Serial ROM Clock */ -#define DT_CS 0x00000001 /* Serial ROM Chip Select */ - -#define POLL_DEMAND 1 - -#define RESET_DE4X5 {\ - int i;\ - i=inl(DE4X5_BMR);\ - udelay(1000);\ - outl(i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ - outl(i, DE4X5_BMR);\ - udelay(1000);\ - for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\ - udelay(1000);\ -} - -#define START_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr |= OMR_ST | OMR_SR;\ - outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ -} - -#define STOP_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr &= ~(OMR_ST|OMR_SR);\ - outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ -} - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ -#define RX_BUFF_SZ PKTSIZE_ALIGN - -#define TOUT_LOOP 1000000 - -#define SETUP_FRAME_LEN 192 -#define ETH_ALEN 6 - - -struct de4x5_desc { - volatile s32 status; - u32 des1; - u32 buf; - u32 next; -}; - -static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ - -static char rxRingSize; -static char txRingSize; - -static u_long iobase; - -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); - -static void send_setup_frame(bd_t * bis); -static void check_hw_addr(bd_t * bis); -static short srom_rd(u_long address, u_char offset); -static void srom_latch(u_int command, u_long address); -static void srom_command(u_int command, u_long address); -static void srom_address(u_int command, u_long address, u_char offset); -static short srom_data(u_int command, u_long address); -static void sendto_srom(u_int command, u_long addr); -static int getfrom_srom(u_long addr); - -static void updateSRom(bd_t *bis); - -static unsigned long dcCsrRead(unsigned long, int); - - -static int inl(u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr)); -} - -static void outl (int command, u_long addr) -{ - *(volatile u_long *)(addr) = cpu_to_le32(command); -} - - -int eth_init(bd_t *bis) -{ - int i, status = 0; - int vendor, device, l; - int cfrv; - unsigned char timer; - unsigned long bmcr; - -#if 0 // test-only - { - int val; - - for (l=0; l<6; l++) - { - printf("%02x: ", l*0x10); - for (i=0; i<4; i++) - { - val = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, l*16+i*4, 4); - printf("%08x ", val); - } - printf("\n"); - } - printf("\n"); - } -#endif - - l = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_CLASS_REVISION, 4); - - l >>= 8; - - if (l != 0x00020000) - { - printf("Error: Can not find an ethernet card on the PCI bus %d " - "in slot %d\n", CFG_ETH_DEV_FN >> 16, - (CFG_ETH_DEV_FN & 0xFFFF) >> 11); - goto Done; - } - - vendor = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_VENDOR_ID, 4); - - device = (vendor >> 16) & 0xffff; - vendor = vendor & 0xffff; - device = device << 8; - - if (! is_DC2114x) - { - printf("Error: The chip is not DC2114x.\n"); - goto Done; - } - - /* Get the chip configuration revision register. - */ - cfrv = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_CLASS_REVISION, 4); - - device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); - - if (device != DC21143) - { - printf("Error: The chip is not DC21143.\n"); - goto Done; - } - - status = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_COMMAND, 2); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEM; - PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_COMMAND, status, 2); - - /* Check the latency timer for values >= 0x60. - */ - timer = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_LATENCY_TIMER, 1); - if (timer < 0x60) - { - PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_LATENCY_TIMER, 0x60, 1); - } - - /* Set I/O base register. - */ - PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_BASE_ADDRESS_0, CFG_ETH_IOBASE, 4); - iobase = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_BASE_ADDRESS_0, 4); - - PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_BASE_ADDRESS_1, CFG_ETH_IOBASE, 4); - iobase = PCI_Read_CFG_Reg(CFG_ETH_DEV_FN, PCI_BASE_ADDRESS_1, 4); - - if (iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - goto Done; - } - - iobase &= CBIO_MASK; - iobase += 0xc0000000; // test-only - - /* Ensure we're not sleeping. - */ - PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_CFDA_PSM, WAKEUP, 1); - - udelay(10 * 1000); - - check_hw_addr(bis); - - RESET_DE4X5; - - if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) - { - printf("Error: Can not reset ethernet controller.\n"); - - goto Done; - } - - outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); - - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].status = cpu_to_le32(R_OWN); - rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32((u_long)NetRxPackets[i]); - rx_ring[i].next = 0; - } - - for (i=0; i < NUM_TX_DESC; i++) - { - tx_ring[i].status = 0; - tx_ring[i].des1 = 0; - tx_ring[i].buf = 0; - tx_ring[i].next = 0; - } - - rxRingSize = NUM_RX_DESC; - txRingSize = NUM_TX_DESC; - - /* Write the end of list marker to the descriptor lists. - */ - rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); - - /* Tell the adapter where the TX/RX rings are located. - */ - outl((u_long)&rx_ring, DE4X5_RRBA); - outl((u_long)&tx_ring, DE4X5_TRBA); - - START_DE4X5; - - tx_new = 0; - rx_new = 0; - - bmcr = dcCsrRead(0, PHY_ANLPAR); - printf("ENET Speed is %d Mbps - %s duplex connection\n", - ((bmcr & PHY_ANLPAR_100) != 0) ? 100 : 10, - ((bmcr & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) ? "FULL" : "HALF"); - - send_setup_frame(bis); - - Done: - - return 0; -} - -int eth_send(volatile void *packet, int length) -{ - int status = 0; - int i; - - if (length <= 0) - { - printf("eth: bad packet size: %d\n", length); - goto out; - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)packet); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - -#if 0 // test-only - if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) - { - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - status++; - } -#endif - - out: - return status; -} - -int eth_rx(void) -{ - s32 status; - int length = 0; - - for ( ; ; ) - { - status = (s32)le32_to_cpu(rx_ring[rx_new].status); - - if (status & R_OWN) - { - break; - } - - if (status & RD_LS) - { - /* Valid frame status. - */ - if (status & RD_ES) - { - /* There was an error. - */ - printf("RX error status = 0x%08X\n", status); - } - else - { - /* A valid frame received. - */ - length = (le32_to_cpu(rx_ring[rx_new].status) >> - 16); - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(NetRxPackets[rx_new], length - 4); - } - - /* Change buffer ownership for this frame, back - * to the adapter. - */ - rx_ring[rx_new].status = cpu_to_le32(R_OWN); - } - - /* Update entry information. - */ - rx_new = (rx_new + 1) % rxRingSize; - } - - return length; -} - -void eth_halt(void) -{ -#if 1 - if (iobase != CFG_ETH_IOBASE) { - /* Ethernet has not been initialized yet. */ - return; - } - - STOP_DE4X5; - outl(0, DE4X5_SICR); - PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_CFDA_PSM, SLEEP, 1); -#endif -} - -static void check_hw_addr(bd_t *bis) -{ - unsigned char hw_addr[ETH_ALEN]; - u_short tmp, *p = (short *)(&hw_addr[0]); - int i, j = 0; - - for (i = 0; i < (ETH_ALEN >> 1); i++) - { - tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if ((j == 0) || (j == 0x2fffd)) - { - printf("Warning: can't read HW address from SROM.\n"); - if ((bis->bi_enetaddr[0] != 0) || (bis->bi_enetaddr[1] != 0) || - (bis->bi_enetaddr[2] != 0) || (bis->bi_enetaddr[3] != 0) || - (bis->bi_enetaddr[4] != 0) || (bis->bi_enetaddr[5] != 0)) - { - printf("Updating SROM data - please wait...\n"); - updateSRom(bis); - } - goto Done; - } - - for (i = 0; i < ETH_ALEN; i++) - { - if (hw_addr[i] != bis->bi_enetaddr[i]) - { - printf("Warning: HW addresses don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - if ((bis->bi_enetaddr[0] != 0) || (bis->bi_enetaddr[1] != 0) || - (bis->bi_enetaddr[2] != 0) || (bis->bi_enetaddr[3] != 0) || - (bis->bi_enetaddr[4] != 0) || (bis->bi_enetaddr[5] != 0)) - { - printf("Updating SROM data - please wait...\n"); - updateSRom(bis); - } - goto Done; - } - } - -Done: - return; -} - -static void send_setup_frame(bd_t *bis) -{ - int i; - char setup_frame[SETUP_FRAME_LEN]; - char * pa = &setup_frame[0]; - - memset(pa, 0xff, SETUP_FRAME_LEN); - - for (i = 0; i < ETH_ALEN; i++) - { - *(pa + (i & 1)) = bis->bi_enetaddr[i]; - if (i & 0x01) - { - pa += 4; - } - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)&setup_frame[0]); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - - if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) - { - printf("TX error status2 = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - } -out: - return; -} - -/* SROM Read. - */ -static short -srom_rd(u_long addr, u_char offset) -{ - sendto_srom(SROM_RD | SROM_SR, addr); - - srom_latch(SROM_RD | SROM_SR | DT_CS, addr); - srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data(SROM_RD | SROM_SR | DT_CS, addr); -} - -static void -srom_latch(u_int command, u_long addr) -{ - sendto_srom(command, addr); - sendto_srom(command | DT_CLK, addr); - sendto_srom(command, addr); - - return; -} - -static void -srom_command(u_int command, u_long addr) -{ - srom_latch(command, addr); - srom_latch(command, addr); - srom_latch((command & 0x0000ff00) | DT_CS, addr); - - return; -} - -static void -srom_address(u_int command, u_long addr, u_char offset) -{ - int i; - signed char a; - - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) { - srom_latch(command | ((a < 0) ? DT_IN : 0), addr); - } - udelay(1); - - i = (getfrom_srom(addr) >> 3) & 0x01; - - return; -} - -static short -srom_data(u_int command, u_long addr) -{ - int i; - short word = 0; - s32 tmp; - - for (i=0; i<16; i++) { - sendto_srom(command | DT_CLK, addr); - tmp = getfrom_srom(addr); - sendto_srom(command, addr); - - word = (word << 1) | ((tmp >> 3) & 0x01); - } - - sendto_srom(command & 0x0000ff00, addr); - - return word; -} - -static void -sendto_srom(u_int command, u_long addr) -{ - outl(command, addr); - udelay(1); - - return; -} - -static int -getfrom_srom(u_long addr) -{ - s32 tmp; - - tmp = inl(addr); - udelay(1); - - return tmp; -} - -/*************************************************************************** - * - * Routines for srom write access - * - */ - -#define DECPCI_REG_OFFSET 0x08 /* quad word aligned */ -#define LONGSWAP(data) ((unsigned long) \ - (((unsigned long)(data) >> 24) | \ - ((unsigned long)(data) << 24) | \ - (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \ - (((unsigned long)(data) << 8) & 0x00ff0000 ))) -#define PCISWAP(x) LONGSWAP(x) /* processor big endian */ - -/******************************************************************************* -* -* dcCsrWrite - select and write a CSR register -* -*/ -static void dcCsrWrite -( - unsigned long devAdrs, /* device address base */ - int reg, /* register to select */ - unsigned long value /* value to write */ - ) -{ - unsigned long * csrReg; - - csrReg = (unsigned long *)(devAdrs + (reg * DECPCI_REG_OFFSET)); - - /* write val to CSR */ - - *(csrReg) = PCISWAP(value); -} - -/******************************************************************************* -* -* dcCsrRead - select and read a CSR register -* -*/ -static unsigned long dcCsrRead -( - unsigned long devAdrs, /* device address base */ - int reg /* register to select */ - ) -{ - unsigned long * csrReg; /* csr register */ - unsigned long csrData; /* data in csr register */ - - csrReg = (unsigned long *)(devAdrs + (reg * DECPCI_REG_OFFSET)); - - csrData = *csrReg; - - /* get contents of CSR */ - - return (PCISWAP(csrData)); -} - -/* define CSRs and descriptors */ - -#define CSR0 0 /* csr 0 */ -#define CSR1 1 /* csr 1 */ -#define CSR2 2 /* csr 2 */ -#define CSR3 3 /* csr 3 */ -#define CSR4 4 /* csr 4 */ -#define CSR5 5 /* csr 5 */ -#define CSR6 6 /* csr 6 */ -#define CSR7 7 /* csr 7 */ -#define CSR8 8 /* csr 8 */ -#define CSR9 9 /* csr 9 */ -#define CSR10 10 /* csr 10 */ -#define CSR11 11 /* csr 11 */ -#define CSR12 12 /* csr 12 */ -#define CSR13 13 /* csr 13 */ -#define CSR14 14 /* csr 14 */ -#define CSR15 15 /* csr 15 */ - -/* CSR9 Ethernet Address ROM Register */ - -#define CSR9_DNV 0x80000000 /* Data not valid */ -#define CSR9_DAT_MSK 0x000000FF /* data mask */ -#define ENET_ROM_SIZE 8 /* ethernet rom register size */ - - -/* CSR9 Serial Address ROM and MII Management Register for the DEC21140 */ - -#define CSR9_040_DNVAL 0x80000000 /* Data not valid - 21040 */ - -#define CSR9_MDI 0x00080000 /* MII mgmt data in - 21140+ */ -#define CSR9_MDI_SHF 19 -#define CSR9_MII_RD 0x00040000 /* MII mgmt read mode - 21140+ */ -#define CSR9_MII_WR 0x00000000 /* MII mgmt write mode - 21140+ */ -#define CSR9_MDO 0x00020000 /* MII mgmt write data - 21140+ */ -#define CSR9_MDO_SHF 17 -#define CSR9_MDC 0x00010000 /* MII mgmt clock - 21140+ */ -#define CSR9_RD 0x00004000 /* Read command - 21140+ */ -#define CSR9_WR 0x00002000 /* Write command - 21140+ */ -#define CSR9_BR 0x00001000 /* Boot rom select - 21140+ */ -#define CSR9_SR 0x00000800 /* Serial rom select - 21140+ */ -#define CSR9_REG 0x00000400 /* External register select - 21140+ */ -#define CSR9_DATA 0x000000FF /* Data */ -#define CSR9_DATA_OUT 0x00000008 /* Shift read data from SROM - 21140+ */ -#define CSR9_DATA_IN 0x00000004 /* Shift write data into SROM - 21140+*/ -#define CSR9_SROM_CLK 0x00000002 /* SCLK output to SROM - 21140+ */ -#define CSR9_SROM_CS 0x00000001 /* SerialROM chip select - 21140+ */ - -#define CSR9_MII_DBIT_RD(X) (((X) & CSR9_MDI) >> CSR9_MDI_SHF) -#define CSR9_MII_DBIT_WR(X) (((X) & 0x1) << CSR9_MDO_SHF) - -#define NSDELAY(nsec) { \ - volatile int nx = 0; \ - volatile int loop = (int)(nsec); \ - for (nx = 0; nx < loop; nx++); \ - } - -#ifndef DC_CSR_READ -#define DC_CSR_READ(devAdrs, csrNum) \ - dcCsrRead ((devAdrs), (csrNum)) -#endif /* DC_CSR_READ */ - -#ifndef DC_CSR_WRITE -#define DC_CSR_WRITE(devAdrs, csrNum, csrVal) \ - dcCsrWrite((devAdrs), (csrNum), (csrVal)) -#endif /* DC_CSR_WRITE */ - -#define DC_CSR_UPDATE(devAdrs, csrNum, csrBits) \ - DC_CSR_WRITE((devAdrs), (csrNum), \ - DC_CSR_READ((devAdrs), (csrNum)) | (csrBits)) - -#define DC_CSR_RESET(devAdrs, csrNum, csrBits) \ - DC_CSR_WRITE((devAdrs), (csrNum), \ - DC_CSR_READ((devAdrs), (csrNum)) & ~(csrBits)) - -#define DC_INT_ENABLE(devAdrs, X) \ - DC_CSR_UPDATE ((devAdrs), CSR7, (X)) - -#define DC_INT_DISABLE(devAdrs, X) \ - DC_CSR_RESET ((devAdrs), CSR7, (X)) - -#define DC_SROM_WRITE(devAdrs, adrs, delay) \ - { \ - DC_CSR_WRITE ((devAdrs), CSR9, (adrs) | CSR9_SR | CSR9_WR); \ - NSDELAY(delay); \ - } - -#define DC_SROM_READ(devAdrs) \ - ((DC_CSR_READ ((devAdrs), CSR9) & 0x08) >> 3) - -/* Reading a serial EEPROM is a "bit" grungy, but we work our way through:->.*/ -/* This code is a "nasty" timing loop, but PC compatible machines are - *supposed* to delay an ISA-compatible period for the SLOW_DOWN_IO macro. */ -#define eeprom_delay() NSDELAY(100) - -#undef inl -#undef outl -#define outl(val, addr) DC_SROM_WRITE(addr, val, 0) -#define inl(addr) DC_SROM_READ(addr) - -#undef debug -#define debug 0 - - -/* EEPROM_Ctrl bits. */ -#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ -#define EE_CS 0x01 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ -#define EE_WRITE_0 0x4801 -#define EE_WRITE_1 0x4805 -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ -#define EE_ENB (0x4800 | EE_CS) - -/* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) - -/* Note: this routine returns extra data bits for size detection. */ -static int read_eeprom(long ioaddr, int location, int addr_len) -{ - int i; - unsigned retval = 0; - long ee_addr = ioaddr; - int read_cmd = location | (EE_READ_CMD << addr_len); - - outl(EE_ENB & ~EE_CS, ee_addr); - outl(EE_ENB, ee_addr); - - if (debug > 2) - printf(" EEPROM read at %d ", location); - - /* Shift the read command bits out. */ - for (i = 4 + addr_len; i >= 0; i--) { - short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; - outl(EE_ENB | dataval, ee_addr); - eeprom_delay(); - outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); - eeprom_delay(); - if (debug > 2) - printf("%lX", inl(ee_addr) & 15); - retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); - } - outl(EE_ENB, ee_addr); - if (debug > 2) - printf(" :%lX:", inl(ee_addr) & 15); - - for (i = 16; i > 0; i--) { - outl(EE_ENB | EE_SHIFT_CLK, ee_addr); - eeprom_delay(); - if (debug > 2) - printf("%lX", inl(ee_addr) & 15); - retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); - outl(EE_ENB, ee_addr); - eeprom_delay(); - } - - /* Terminate the EEPROM access. */ - outl(EE_ENB & ~EE_CS, ee_addr); - if (debug > 2) - printf(" EEPROM value at %d is %5.5x.\n", location, retval); - return retval; -} - - -/* This executes a generic EEPROM command, typically a write or write enable. - It returns the data output from the EEPROM, and thus may also be used for - reads. */ -static int do_eeprom_cmd(int ioaddr, int cmd, int cmd_len) -{ - unsigned retval = 0; - int ee_addr = ioaddr; - - if (debug > 1) - printf(" EEPROM op 0x%x: ", cmd); - - outl(EE_ENB | EE_SHIFT_CLK, ee_addr); - - /* Shift the command bits out. */ - do { - short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; - outl(dataval, ee_addr); - eeprom_delay(); - if (debug > 2) - printf("%lX", inl(ee_addr) & 15); - outl(dataval | EE_SHIFT_CLK, ee_addr); - eeprom_delay(); - retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); - } while (--cmd_len >= 0); - outl(EE_ENB, ee_addr); - - /* Terminate the EEPROM access. */ - outl(EE_ENB & ~EE_CS, ee_addr); - if (debug > 1) - printf(" EEPROM result is 0x%5.5x.\n", retval); - return retval; -} - - -static int dcWriteRom(int ioaddr, int index, int new_value) -{ - int ee_addr_size = read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; - int i; - unsigned short newval; - - udelay(10*1000); /* test-only */ - - if (debug > 1) - { - printf("ee_addr_size=%d.\n", ee_addr_size); - printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); - } - /* Enable programming modes. */ - do_eeprom_cmd(ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); - /* Do the actual write. */ - do_eeprom_cmd(ioaddr, - (((EE_WRITE_CMD< 1) - printf(" Write finished after %d ticks.\n", i); - /* Disable programming. */ - do_eeprom_cmd(ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size); - /* And read the result. */ - newval = do_eeprom_cmd(ioaddr, - (((EE_READ_CMD< 1) - printf(" New value at offset %d is %4.4x.\n", index, newval); - return 1; -} - - -static void updateSRom(bd_t *bis) -{ - unsigned short addrShort; - - /* taken from ramix pmc-module */ - dcWriteRom(iobase, 0x00, 0x140b); - dcWriteRom(iobase, 0x01, 0x6610); - dcWriteRom(iobase, 0x02, 0x0); - dcWriteRom(iobase, 0x03, 0x0); - dcWriteRom(iobase, 0x04, 0x0); - dcWriteRom(iobase, 0x05, 0x0); - dcWriteRom(iobase, 0x06, 0x0); - dcWriteRom(iobase, 0x07, 0x0); - - dcWriteRom(iobase, 0x08, 0x00a3); - dcWriteRom(iobase, 0x09, 0x0103); - - dcWriteRom(iobase, 0x0a, 0x0200); /* Ethernet Addr... */ - dcWriteRom(iobase, 0x0b, 0x0027); - addrShort = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); - dcWriteRom(iobase, 0x0c, addrShort); /* ...Ethernet Addr */ - - dcWriteRom(iobase, 0x0d, 0x1f00); - dcWriteRom(iobase, 0x0e, 0x0); - dcWriteRom(iobase, 0x0f, 0x0); - - dcWriteRom(iobase, 0x10, 0x0108); - dcWriteRom(iobase, 0x11, 0x038d); /* set extended format bit 0x80 !!! */ - dcWriteRom(iobase, 0x12, 0x0); - dcWriteRom(iobase, 0x13, 0x0); - dcWriteRom(iobase, 0x14, 0xe078); - dcWriteRom(iobase, 0x15, 0x0001); - dcWriteRom(iobase, 0x16, 0x0040); - dcWriteRom(iobase, 0x17, 0x0018); - - dcWriteRom(iobase, 0x18, 0x0); - dcWriteRom(iobase, 0x19, 0x0); - dcWriteRom(iobase, 0x1a, 0x0); - dcWriteRom(iobase, 0x1b, 0x0); - dcWriteRom(iobase, 0x1c, 0x0); - dcWriteRom(iobase, 0x1d, 0x0); - dcWriteRom(iobase, 0x1e, 0x0); - dcWriteRom(iobase, 0x1f, 0x0); - - dcWriteRom(iobase, 0x20, 0x0); - dcWriteRom(iobase, 0x21, 0x0); - dcWriteRom(iobase, 0x22, 0x0); - dcWriteRom(iobase, 0x23, 0x0); - dcWriteRom(iobase, 0x24, 0x0); - dcWriteRom(iobase, 0x25, 0x0); - dcWriteRom(iobase, 0x26, 0x0); - dcWriteRom(iobase, 0x27, 0x0); - - dcWriteRom(iobase, 0x28, 0x0); - dcWriteRom(iobase, 0x29, 0x0); - dcWriteRom(iobase, 0x2a, 0x0); - dcWriteRom(iobase, 0x2b, 0x0); - dcWriteRom(iobase, 0x2c, 0x0); - dcWriteRom(iobase, 0x2d, 0x0); - dcWriteRom(iobase, 0x2e, 0x0); - dcWriteRom(iobase, 0x2f, 0x0); - - dcWriteRom(iobase, 0x30, 0x0); - dcWriteRom(iobase, 0x31, 0x0); - dcWriteRom(iobase, 0x32, 0x0); - dcWriteRom(iobase, 0x33, 0x0); - dcWriteRom(iobase, 0x34, 0x0); - dcWriteRom(iobase, 0x35, 0x0); - dcWriteRom(iobase, 0x36, 0x0); - dcWriteRom(iobase, 0x37, 0x0); - - dcWriteRom(iobase, 0x38, 0x0); - dcWriteRom(iobase, 0x39, 0x0); - dcWriteRom(iobase, 0x3a, 0x0); - dcWriteRom(iobase, 0x3b, 0x0); - dcWriteRom(iobase, 0x3c, 0x0); - dcWriteRom(iobase, 0x3d, 0x0); - dcWriteRom(iobase, 0x3e, 0x0); - dcWriteRom(iobase, 0x3f, 0x4e07); -} diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c new file mode 100644 index 0000000..770804e --- /dev/null +++ b/board/esd/common/pci.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +u_long pci9054_iobase; + + +#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ +#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ + + +/*-----------------------------------------------------------------------------+ +| Subroutine: pci9054_read_config_dword +| Description: Read a PCI configuration register +| Inputs: +| hose PCI Controller +| dev PCI Bus+Device+Function number +| offset Configuration register number +| value Address of the configuration register value +| Return value: +| 0 Successful ++-----------------------------------------------------------------------------*/ +int pci9054_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32* value) +{ + unsigned long conAdrVal; + unsigned long val; + + /* generate coded value for CON_ADR register */ + conAdrVal = dev | (offset & 0xfc) | 0x80000000; + + /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ + *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; + + /* Note: *pResult comes back as -1 if machine check happened */ + val = in32r(PCI_PRIMARY_CDR); + + *value = (unsigned long) val; + + out32r(PCI_PRIMARY_CAR, 0); + + if ((*(unsigned long *)0x50000304) & 0x60000000) + { + /* clear pci master/target abort bits */ + *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; + } + + return 0; +} + +/*-----------------------------------------------------------------------------+ +| Subroutine: pci9054_write_config_dword +| Description: Write a PCI configuration register. +| Inputs: +| hose PCI Controller +| dev PCI Bus+Device+Function number +| offset Configuration register number +| Value Configuration register value +| Return value: +| 0 Successful +| Updated for pass2 errata #6. Need to disable interrupts and clear the +| PCICFGADR reg after writing the PCICFGDATA reg. ++-----------------------------------------------------------------------------*/ +int pci9054_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + unsigned long conAdrVal; + + conAdrVal = dev | (offset & 0xfc) | 0x80000000; + + *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; + + out32r(PCI_PRIMARY_CDR, value); + + out32r(PCI_PRIMARY_CAR, 0); + + /* clear pci master/target abort bits */ + *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; + + return (0); +} + +static struct pci_ops pci9054_ops = { + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + pci9054_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + pci9054_write_config_dword +}; + +/*----------------------------------------------------------------------- + */ + +#ifdef CONFIG_DASA_SIM +static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *_) +{ + unsigned int iobase; + unsigned short status = 0; + unsigned char timer; + + /* + * Configure PLX PCI9054 + */ + pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); + status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); + + /* Check the latency timer for values >= 0x60. + */ + pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); + if (timer < 0x60) + { + pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); + } + + /* Set I/O base register. + */ + pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); + pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); + + pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); + + if (pci9054_iobase == 0xffffffff) + { + printf("Error: Can not set I/O base register.\n"); + return; + } +} +#endif + +static struct pci_config_table pci9054_config_table[] = { +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), + pci_cfgfunc_config_device, { CFG_ETH_IOBASE, + CFG_ETH_IOBASE, + PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, +#ifdef CONFIG_DASA_SIM + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), + pci_dasa_sim_config_pci9054 }, +#endif +#endif + { } +}; + +static struct pci_controller pci9054_hose = { + ops: &pci9054_ops, + config_table: pci9054_config_table, +}; + +void pci_init(bd_t *dummy) +{ + struct pci_controller *hose = &pci9054_hose; + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + 0x00000000, 0x00000000, 0x01000000, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI Memory space */ + pci_set_region(hose->regions + 1, + 0x00000000, 0xc0000000, 0x10000000, + PCI_REGION_MEM); + + hose->region_count = 2; + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +} diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile index 985d58c..29aaf3b 100644 --- a/board/esd/dasa_sim/Makefile +++ b/board/esd/dasa_sim/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ../common/dc2114x.o cmd_dasa_sim.o \ - eeprom.o pci.o +OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o $(LIB): $(OBJS) $(AR) crv $@ $^ diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index df7aeb3..5cbfe22 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -24,7 +24,7 @@ #include #include - +#include #define OK 0 #define ERROR (-1) @@ -36,11 +36,6 @@ extern u_long pci9054_iobase; -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); -void pci9054_init(void); - - /*************************************************************************** * * Routines for PLX PCI9054 eeprom access @@ -50,16 +45,16 @@ void pci9054_init(void); static unsigned int PciEepromReadLongVPD(int offs) { unsigned int value; - unsigned long ret; + unsigned int ret; int count; - PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, 0x4c, (offs<<16) | 0x0003, 4); + pci_write_config_dword(CFG_PCI9054_DEV_FN, 0x4c, (offs<<16) | 0x0003); count = 0; for (;;) { udelay(10 * 1000); - ret = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, 0x4c, 4); + pci_read_config_dword(CFG_PCI9054_DEV_FN, 0x4c, &ret); if ((ret & 0x80000000) != 0) { break; @@ -69,13 +64,13 @@ static unsigned int PciEepromReadLongVPD(int offs) count++; if (count > 10) { - printf("\nTimeout: ret=%08lx - Please try again!\n", ret); + printf("\nTimeout: ret=%08x - Please try again!\n", ret); break; } } } - value = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, 0x50, 4); + pci_read_config_dword(CFG_PCI9054_DEV_FN, 0x50, &value); return value; } @@ -83,17 +78,17 @@ static unsigned int PciEepromReadLongVPD(int offs) static int PciEepromWriteLongVPD(int offs, unsigned int value) { - unsigned long ret; + unsigned int ret; int count; - PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, 0x50, value, 4); - PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, 0x4c, (offs<<16) | 0x80000003, 4); + pci_write_config_dword(CFG_PCI9054_DEV_FN, 0x50, value); + pci_write_config_dword(CFG_PCI9054_DEV_FN, 0x4c, (offs<<16) | 0x80000003); count = 0; for (;;) { udelay(10 * 1000); - ret = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, 0x4c, 4); + pci_read_config_dword(CFG_PCI9054_DEV_FN, 0x4c, &ret); if ((ret & 0x80000000) == 0) { break; @@ -103,7 +98,7 @@ static int PciEepromWriteLongVPD(int offs, unsigned int value) count++; if (count > 10) { - printf("\nTimeout: ret=%08lx - Please try again!\n", ret); + printf("\nTimeout: ret=%08x - Please try again!\n", ret); break; } } @@ -124,7 +119,7 @@ static void showPci9054(void) printf("%02x: ", l*0x10); for (i=0; i<4; i++) { - val = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, l*16+i*4, 4); + pci_read_config_dword(CFG_PCI9054_DEV_FN, l*16+i*4, &val); printf("%08x ", val); } printf("\n"); @@ -215,8 +210,6 @@ static void clearPci9054(void) /* ------------------------------------------------------------------------- */ int do_pci9054(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - pci9054_init(); - if (strcmp(argv[1], "info") == 0) { showPci9054(); diff --git a/board/esd/dasa_sim/pci.c b/board/esd/dasa_sim/pci.c deleted file mode 100644 index 5570b65..0000000 --- a/board/esd/dasa_sim/pci.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -/* PCI Registers. - */ -#define PCI_VENDOR_ID 0x00 -#define PCI_COMMAND 0x04 -#define PCI_CLASS_REVISION 0x08 -#define PCI_LATENCY_TIMER 0x0d -#define PCI_BASE_ADDRESS_0 0x10 -#define PCI_BASE_ADDRESS_1 0x14 -#define PCI_BASE_ADDRESS_2 0x18 -#define PCI_CFDA_PSM 0x43 - -#define PCI_COMMAND_IO 0x1 -#define PCI_COMMAND_MEM 0x2 -#define PCI_COMMAND_MASTER 0x4 - -#define CBIO_MASK -128 - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Read_CFG_Reg -| Description: Read a PCI configuration register -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Width Number of bytes to read (1, 2, or 4) -| Return value: -| (unsigned int) Value of the configuration register read. -| For reads shorter than 4 bytes, return value -| is LSB-justified -+-----------------------------------------------------------------------------*/ -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width) -{ - unsigned long conAdrVal; - unsigned long val; - unsigned long Value = 0; - - /* generate coded value for CON_ADR register */ - - conAdrVal = BusDevFunc | (Reg & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - /* shift to position */ - switch (Width) - { - case 1: - val >>= ((Reg & 0x03) * 8); - val &= 0xff; - Value = (unsigned char) val; - break; - case 2: - val >>= ((Reg & (int)(0x02) ) * 8); - val &= 0xffff; - Value = (unsigned short) val; - break; - case 4: - Value = (unsigned long) val; - break; - } - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return (Value); -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Write_CFG_Reg -| Description: Write a PCI configuration register. -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Value Configuration register value -| Width Number of bytes to write (1, 2, or 4) -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width) -{ - unsigned long conAdrVal; - unsigned long val; - - conAdrVal = BusDevFunc | (Reg & 0xfc) | 0x80000000; - - /* shift to position */ - { - unsigned long ldata; - int mask; - - val = PCI_Read_CFG_Reg(BusDevFunc, Reg & ~3, 4); - - switch (Width) - { - case 1: - mask = 0x000000ff; - ldata = (((unsigned long)Value) & mask) << ((Reg & (int)0x03) * 8); - mask <<= ((Reg & 0x03) * 8); - Value = (val & ~mask) | ldata; - break; - case 2: - mask = 0x0000ffff; - ldata = (((unsigned long)Value) & mask) << ((Reg & (int)0x02) * 8); - mask <<= ((Reg & (int)0x02) * 8); - Value = (val & ~mask) | ldata; - break; - case 4: - break; - } - - } - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, Value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - - -/*----------------------------------------------------------------------- - */ - -void pci9054_init(void) -{ - int status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - status = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_COMMAND, 2); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEM; - PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_COMMAND, status, 2); - - /* Check the latency timer for values >= 0x60. - */ - timer = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 1); - if (timer < 0x60) - { - PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60, 1); - } - - /* Set I/O base register. - */ - PCI_Write_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE, 4); - pci9054_iobase = PCI_Read_CFG_Reg(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, 4); - - pci9054_iobase &= CBIO_MASK; - pci9054_iobase += 0xc0000000; // test-only - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile index 4f209e1..31e24df 100644 --- a/board/evb64260/Makefile +++ b/board/evb64260/Makefile @@ -27,7 +27,7 @@ LIB = lib$(BOARD).a SOBJS = misc.o OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ - eth.o eth_addrtbl.o ns16550.o mpsc.o i2c.o \ + eth.o eth_addrtbl.o mpsc.o i2c.o \ sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o diff --git a/board/evb64260/ns16550.c b/board/evb64260/ns16550.c deleted file mode 100644 index 06a3ea8..0000000 --- a/board/evb64260/ns16550.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines - * - * further modified by Josh Huber to support - * the DUART on the Galileo Eval board. (evb64260) - */ - -#include -#include "ns16550.h" - -#ifdef ZUMA_NTL -/* no 16550 device */ -#else -const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), - (NS16550_t) (CFG_DUART_IO + 0x20) }; - -volatile struct NS16550 * -NS16550_init(int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - - /* Clear & enable FIFOs */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; - return (com_port); -} - -void -NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - - /* Clear & enable FIFOs */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; -} - -void -NS16550_putc(volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0) ; - com_port->thr = c; -} - -unsigned char -NS16550_getc(volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0) ; - return (com_port->rbr); -} - -int -NS16550_tstc(volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} -#endif diff --git a/board/evb64260/ns16550.h b/board/evb64260/ns16550.h deleted file mode 100644 index c8b62c2..0000000 --- a/board/evb64260/ns16550.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * - * further modified to support the DUART in the Galileo eval board - * modifications (c) Josh Huber , Mission Critical Linux, Inc. - */ - -#ifndef __NS16550_H__ -#define __NS16550_H__ - -/* the padding is necessary because on the galileo board the UART is - wired in with the 3 address lines shifted over by 2 bits */ -struct NS16550 -{ - unsigned char rbr; /* 0 */ - int pad1:24; - - unsigned char ier; /* 1 */ - int pad2:24; - - unsigned char fcr; /* 2 */ - int pad3:24; - - unsigned char lcr; /* 3 */ - int pad4:24; - - unsigned char mcr; /* 4 */ - int pad5:24; - - unsigned char lsr; /* 5 */ - int pad6:24; - - unsigned char msr; /* 6 */ - int pad7:24; - - unsigned char scr; /* 7 */ - int pad8:24; -} __attribute__ ((packed)); - -/* aliases */ -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -#define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*reciever soft reset*/ -#define FCR_TXSR 0x04 /*transmitter soft reset*/ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask*/ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble*/ -#define LCR_EPS 0x10 /* Even Parity Select*/ -#define LCR_STKP 0x20 /* Stick Parity*/ -#define LCR_SBRK 0x40 /* Set Break*/ -#define LCR_BKSE 0x80 /* Bank select enable*/ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc(volatile struct NS16550 *com_port); -int NS16550_tstc(volatile struct NS16550 *com_port); -void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); - -typedef struct NS16550 *NS16550_t; - -extern const NS16550_t COM_PORTS[]; - -#endif diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c index f7c57da..feb9490 100644 --- a/board/evb64260/pci.c +++ b/board/evb64260/pci.c @@ -3,6 +3,8 @@ /* Copyright - Galileo technology. */ #include +#include + #include #undef DEBUG @@ -20,42 +22,6 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { static const unsigned int BAR_REG[]={BAR0,BAR1,BAR2,BAR3,BAR4,BAR5}; -static PCI_DEVICE pci_dev_list[2][PCI_MAX_DEVICES]; -static unsigned int pci_mem_bar_alloc[2]={CFG_PCI0_MEM_BASE,CFG_PCI1_MEM_BASE}; -static unsigned int pci_io_bar_alloc[2]={CFG_PCI0_IO_SPACE_PCI,CFG_PCI1_IO_SPACE_PCI}; - -static void decode_class(char *buf, int class) -{ - static const char * const decode_legend[] = { - "Old generation device", /* 0 */ - "Mass storage controller", /* 1 */ - "Network controller", /* 2 */ - "Display controller", /* 3 */ - "Multimedia device", /* 4 */ - "Memory controller", /* 5 */ - "Bridge Device", /* 6 */ - "Simple Communication controllers", /* 7 */ - "Base system peripherals", /* 8 */ - "Input Devices", /* 9 */ - "Docking stations", /* a */ - "Processors", /* b */ - "Serial bus controllers", /* c */ - "Wireless controllers", /* d */ - "Intelligent I/O controllers", /* e */ - "Satellite communication controllers", /* f */ - "Encryption/Decryption controllers", /* 10 */ - "Data acquisition and signal processing controllers", /* 11 */ - "\0" - }; - - if(class>=0 && class<=0x11) - strncpy(buf,decode_legend[class],40); - else if(class==0xff) - strncpy(buf,"Other",40); - else - sprintf(buf,"Unknown class 0x%x", class); -} - static const unsigned int pci_p2p_configuration_reg[]={ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION}; @@ -91,143 +57,6 @@ static const unsigned int pci_scs_bank_size[2][4] = { static const unsigned int pci_p2p_configuration[] = { PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION}; -static u32 size_bar(int host, int barnum, int device, PCI_BAR *bar) -{ - u32 detect, size=0; - - pciWriteConfigReg(host,BAR_REG[barnum],device,0x0); - if((((detect=pciReadConfigReg(host,BAR_REG[barnum],device))&~9)!=0x0)) { - static const int ide_bar[]={8,4,8,4,0,0}; - u32 classCode = pciReadConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID, - device); - if((classCode>>16)!=0x0101) { - printf(" %d:%d weird bar and not PCI/IDE (classCode=%08x)\n", - device,barnum,classCode); - printf(" %d:%d 0->bar: BAR:%x\n", device,barnum,detect); - pciWriteConfigReg(host,BAR_REG[barnum],device,0xffffffff); - detect=pciReadConfigReg(host,BAR_REG[barnum],device); - printf(" %d:%d f->bar: BAR:%x\n", device,barnum,detect); - return 0; - } - - bar->type &= ~BAR_MEM_TYPE_MASK; /* set to type 0 */ - return ide_bar[barnum]; - } - - pciWriteConfigReg(host,BAR_REG[barnum],device,0xffffffff); - bar->detectBase = pciReadConfigReg(host,BAR_REG[barnum],device); - - if(bar->detectBase == 0) { /* case of an empty BAR */ - return 0; - } - - if (bar->type & BAR_SEL_MEM_IO) { - bar->type &= BAR_SEL_MEM_IO; - size = ~(bar->detectBase & 0xfffffffc) + 1; - } else { - size = ~(bar->detectBase & 0xfffffff0) + 1; - } - - return size; - -} - -/******************************************************************** -* pciScanDevices - This function scan PCIn bus, if found any device on -* this bus it interrogate the Device for the information -* it can discover. -* The fields with all information are the following: -* char type[20]; -* unsigned int deviceNum; -* unsigned int venID; -* unsigned int deviceID; -* struct { -* unsigned int base; -* unsigned int size; -* unsigned int type; -* } bar[6]; -* -* Inputs: PCI_DEVICE* pciDetect - Pointer to an array of STRUCT PCI_DEVICE. -* unsigned int numberOfElment - The PCI_DEVICE Array length. -* Output: None. -*********************************************************************/ -void pciScanDevices(PCI_HOST host, PCI_DEVICE* pciDetect,unsigned int numberOfElment) -{ - PCI_DEVICE* pciArrayPointer = pciDetect; - unsigned int id; /* PCI Configuration register 0x0.*/ - unsigned int device; /* device`s Counter.*/ - unsigned int classCode; /* PCI Configuration register 0x8 */ - unsigned int arrayCounter = 0; - unsigned int memBaseAddress; - unsigned int pciCause; - - RESET_REG_BITS(pci_error_cause_reg[host],BIT8); /* clears PCI_0 cause. */ - - PCI_MASTER_ENABLE(host,SELF); - - for(device = 0 ; device < PCI_MAX_DEVICES ; device ++) - { - id = pciReadConfigReg(host, PCI_DEVICE_AND_VENDOR_ID,device); - GT_REG_READ(pci_error_cause_reg[host],&pciCause); - /* Clearing bit 8 of in the Cause Register by writing 0. */ - RESET_REG_BITS(pci_error_cause_reg[host],BIT8); /* clears PCI_n cause. */ - if ( (id != 0xffffffff) && !(pciCause & BIT8) ) { /* agent was found */ - int i; -#if 0 - if(device!=0) { - int statcmd = pciReadConfigReg(host,PCI_STATUS_AND_COMMAND, - device); - statcmd &= ~(MASTER_ENABLE | MEMORY_ENABLE | I_O_ENABLE); - /* disable this device */ - pciWriteConfigReg(host,PCI_STATUS_AND_COMMAND, device, statcmd); - } -#endif - - classCode = pciReadConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID, - device); - - pciArrayPointer->host = host; - pciArrayPointer->deviceNum = device; - pciArrayPointer->venID = ( id & 0xffff); - pciArrayPointer->deviceID = ( ( id & 0xffff0000) >> 16 ); - -#ifdef IDE_SET_NATIVE_MODE - if ((classCode >> 16) == 0x0101) { /* IDE/PCI hack to set to native mode */ -#ifdef DEBUG - printf("%d:%d setting PCI IDE native mode\n", host, device); -#endif - pciWriteConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID,device, - classCode | 0x0500); - - for(i=0x50;i<0x5b;i+=4) { - printf("%x: %08x\n",i, pciReadConfigReg(host,i,device)); - } - } -#endif - - for(i=0;i<6;i++) { - PCI_BAR *pbar=&pciArrayPointer->bar[i]; - /* BARn parameters */ - memBaseAddress = pciReadConfigReg(host,BAR_REG[i],device); - pbar->type = memBaseAddress & BAR_CONFIG_MASK; - pbar->base = memBaseAddress & 0xfffff000; - pbar->size = size_bar(host,i,device, pbar); - /* restore the previous value to BAR_n base */ - pciWriteConfigReg(host,BAR_REG[i],device,memBaseAddress); - } - - decode_class(pciArrayPointer->type, classCode>>24); - - arrayCounter++; /* point to the next element in the Array. */ - if(arrayCounter == numberOfElment) - return; /* When the Array is fully used, return. */ - /* Else, points to next free Element.*/ - pciArrayPointer = &pciDetect[arrayCounter]; - } - } - pciArrayPointer->deviceNum = -1; /* -1 => End of List */ -} - /******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register * - Make sure the GT is configured as a master before writing @@ -426,224 +255,6 @@ unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, } } -#if 0 // FIXME eventually - this is crap -/******************************************************************** -* pci0ScanSelfBars - update in PCI_SELF_BARS struct all bars base and sizes. -* -* Inputs: PCI_SELF_BARS *pci0SelfBars - the struct which the data will be update -* in. -*********************************************************************/ -void pci0ScanSelfBars(PCI_SELF_BARS *pciSelfBars) -{ - unsigned int size; - pciSelfBars->SCS0Base = pciReadConfigReg(0,PCI_SCS_0_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_0_BANK_SIZE); - if(size) - pciSelfBars->SCS0Size = size + 0x1000; - else - pciSelfBars->SCS0Size = 0; - pciSelfBars->SCS1Base = pciReadConfigReg(0,PCI_SCS_1_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_1_BANK_SIZE); - if(size) - pciSelfBars->SCS1Size = size + 0x1000; - else - pciSelfBars->SCS1Size = 0; - pciSelfBars->SCS2Base = pciReadConfigReg(0,PCI_SCS_2_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_2_BANK_SIZE); - if(size) - pciSelfBars->SCS2Size = size + 0x1000; - else - pciSelfBars->SCS2Size = 0; - pciSelfBars->SCS3Base = pciReadConfigReg(0,PCI_SCS_3_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_3_BANK_SIZE); - if(size) - pciSelfBars->SCS3Size = size + 0x1000; - else - size = 0; - pciSelfBars->CS0Base = pciReadConfigReg(0,PCI_CS_0_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_0_BANK_SIZE); - if(size) - pciSelfBars->CS0Size = size + 0x1000; - else - pciSelfBars->CS0Size = 0; - pciSelfBars->CS1Base = pciReadConfigReg(0,PCI_CS_1_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_1_BANK_SIZE); - if(size) - pciSelfBars->CS1Size = size + 0x1000; - else - pciSelfBars->CS1Size = 0; - pciSelfBars->CS2Base = pciReadConfigReg(0,PCI_CS_2_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_2_BANK_SIZE); - if(size) - pciSelfBars->CS2Size = size + 0x1000; - else - pciSelfBars->CS2Size = 0; - pciSelfBars->CS3Base = pciReadConfigReg(0,PCI_CS_3_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_3_BANK_SIZE); - if(size) - pciSelfBars->CS3Size = size + 0x1000; - else - pciSelfBars->CS3Size = 0; - pciSelfBars->CSBootBase = pciReadConfigReg(0,PCI_BOOTCS_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_BOOT_BANK_SIZE); - if(size) - pciSelfBars->CSBootSize = size + 0x1000; - else - pciSelfBars->CSBootSize = 0; - pciSelfBars->internalMemBase = pciReadConfigReg(0, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & - 0xfffff000; - pciSelfBars->internalIOBase = pciReadConfigReg(0, - PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & - 0xfffff000; - pciSelfBars->P2PMem0Base = pciReadConfigReg(0,PCI_P2P_MEM0_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0P2P_MEM0_BAR_SIZE); - if(size) - pciSelfBars->P2PMem0Size = size + 0x1000; - else - pciSelfBars->P2PMem0Size = 0; - pciSelfBars->P2PMem1Base = pciReadConfigReg(0,PCI_P2P_MEM1_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0P2P_MEM1_BAR_SIZE); - if(size) - pciSelfBars->P2PMem1Size = size + 0x1000; - else - pciSelfBars->P2PMem1Size = 0; - pciSelfBars->P2PIOBase = pciReadConfigReg(0,PCI_P2P_I_O_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0P2P_I_O_BAR_SIZE); - if(size) - pciSelfBars->P2PIOSize = size + 0x1000; - else - pciSelfBars->P2PIOSize = 0; - pciSelfBars->CPUBase = pciReadConfigReg(0,PCI_CPU_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CPU_BAR_SIZE); - if(size) - pciSelfBars->CPUSize = size + 0x1000; - else - pciSelfBars->CPUSize = 0; -} - -/******************************************************************** -* pci1ScanSelfBars - update in PCI_SELF_BARS struct all bars base and sizes. -* -* Inputs: PCI_SELF_BARS *pci1SelfBars - the struct which the data will be update -* in. -*********************************************************************/ -void pci1ScanSelfBars(PCI_SELF_BARS *pciSelfBars) -{ - unsigned int size; - pciSelfBars->SCS0Base = pciReadConfigReg(1,PCI_SCS_0_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_0_BANK_SIZE); - if(size) - pciSelfBars->SCS0Size = size + 0x1000; - else - pciSelfBars->SCS0Size = 0; - pciSelfBars->SCS1Base = pciReadConfigReg(1,PCI_SCS_1_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_1_BANK_SIZE); - if(size) - pciSelfBars->SCS1Size = size + 0x1000; - else - pciSelfBars->SCS1Size = 0; - pciSelfBars->SCS2Base = pciReadConfigReg(1,PCI_SCS_2_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_2_BANK_SIZE); - if(size) - pciSelfBars->SCS2Size = size + 0x1000; - else - pciSelfBars->SCS2Size = 0; - pciSelfBars->SCS3Base = pciReadConfigReg(1,PCI_SCS_3_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0SCS_3_BANK_SIZE); - if(size) - pciSelfBars->SCS3Size = size + 0x1000; - else - size = 0; - pciSelfBars->CS0Base = pciReadConfigReg(1,PCI_CS_0_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_0_BANK_SIZE); - if(size) - pciSelfBars->CS0Size = size + 0x1000; - else - pciSelfBars->CS0Size = 0; - pciSelfBars->CS1Base = pciReadConfigReg(1,PCI_CS_1_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_1_BANK_SIZE); - if(size) - pciSelfBars->CS1Size = size + 0x1000; - else - pciSelfBars->CS1Size = 0; - pciSelfBars->CS2Base = pciReadConfigReg(1,PCI_CS_2_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_2_BANK_SIZE); - if(size) - pciSelfBars->CS2Size = size + 0x1000; - else - pciSelfBars->CS2Size = 0; - pciSelfBars->CS3Base = pciReadConfigReg(1,PCI_CS_3_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_3_BANK_SIZE); - if(size) - pciSelfBars->CS3Size = size + 0x1000; - else - pciSelfBars->CS3Size = 0; - pciSelfBars->CSBootBase = pciReadConfigReg(1,PCI_BOOTCS_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CS_BOOT_BANK_SIZE); - if(size) - pciSelfBars->CSBootSize = size + 0x1000; - else - pciSelfBars->CSBootSize = 0; - pciSelfBars->internalMemBase = pciReadConfigReg(1, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & - 0xfffff000; - pciSelfBars->internalIOBase = pciReadConfigReg(1, - PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & - 0xfffff000; - pciSelfBars->P2PMem0Base = pciReadConfigReg(1,PCI_P2P_MEM0_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0P2P_MEM0_BAR_SIZE); - if(size) - pciSelfBars->P2PMem0Size = size + 0x1000; - else - pciSelfBars->P2PMem0Size = 0; - pciSelfBars->P2PMem1Base = pciReadConfigReg(1,PCI_P2P_MEM1_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0P2P_MEM1_BAR_SIZE); - if(size) - pciSelfBars->P2PMem1Size = size + 0x1000; - else - pciSelfBars->P2PMem1Size = 0; - pciSelfBars->P2PIOBase = pciReadConfigReg(1,PCI_P2P_I_O_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0P2P_I_O_BAR_SIZE); - if(size) - pciSelfBars->P2PIOSize = size + 0x1000; - else - pciSelfBars->P2PIOSize = 0; - pciSelfBars->CPUBase = pciReadConfigReg(1,PCI_CPU_BASE_ADDRESS,SELF) & - 0xfffff000; - size = GTREGREAD(PCI_0CPU_BAR_SIZE); - if(size) - pciSelfBars->CPUSize = size + 0x1000; - else - pciSelfBars->CPUSize = 0; -} -#endif - /******************************************************************** * pciGetRegOffset - Gets the register offset for this region config. * @@ -699,30 +310,6 @@ static unsigned int pciGetRemapOffset(PCI_HOST host, PCI_REGION region) return PCI_0MEMORY0_ADDRESS_REMAP; } -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress(PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset=pciGetRegOffset(host, region); - - GT_REG_READ(regOffset, ®Base); - GT_REG_READ(regOffset+8, ®End); - - if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 20; - return regBase; -} - bool pciMapSpace(PCI_HOST host, PCI_REGION region, unsigned int remapBase, unsigned int bankBase,unsigned int bankLength) { unsigned int low=0xfff; @@ -782,372 +369,6 @@ void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, unsigned int pciDramBase, GT_REG_WRITE(pci_scs_bank_size[host][bank], pciDramSize-1); } -#if 0 // FIXME eventually - this is crap -/******************************************************************** -* pci0MapInternalRegSpace - Maps the internal registers memory space for the -* slave. -* -* Inputs: base of pci0 internal register -*********************************************************************/ -void pci0MapInternalRegSpace(unsigned int pci0InternalBase) -{ - pci0InternalBase = pci0InternalBase & 0xfffff000; - pci0InternalBase = pci0InternalBase | (pciReadConfigReg(0, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF, - pci0InternalBase); -} - -/******************************************************************** -* pci1MapInternalRegSpace - Maps the internal registers memory space for the -* slave. -* -* Inputs: base of pci1 internal register -*********************************************************************/ -void pci1MapInternalRegSpace(unsigned int pci1InternalBase) -{ - pci1InternalBase = pci1InternalBase & 0xfffff000; - pci1InternalBase = pci1InternalBase | (pciReadConfigReg(1, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF, - pci1InternalBase); -} - -/******************************************************************** -* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the -* slave. -* -* Inputs: base of pci0 internal io register -*********************************************************************/ -void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase) -{ - pci0InternalBase = pci0InternalBase & 0xfffff000; - pci0InternalBase = pci0InternalBase | (pciReadConfigReg(0, - PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF, - pci0InternalBase); -} - -/******************************************************************** -* pci1MapInternalRegIOSpace - Maps the internal registers IO space for the -* slave. -* Inputs: base of pci1 internal io register -*********************************************************************/ -void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase) -{ - pci1InternalBase = pci1InternalBase & 0xfffff000; - pci1InternalBase = pci1InternalBase | (pciReadConfigReg(1, - PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF, - pci1InternalBase); -} - -/******************************************************************** -* pci0MapDevice0MemorySpace - Maps PCI0 device0 memory spaces for the slave. -* -* Inputs: base and length of pci0 device0 -*********************************************************************/ -void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, - unsigned int pci0Dev0Length) -{ - pci0Dev0Base = pci0Dev0Base & 0xfffff000; - pci0Dev0Base = pci0Dev0Base | (pciReadConfigReg(0, - PCI_CS_0_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_CS_0_BASE_ADDRESS,SELF,pci0Dev0Base ); - if(pci0Dev0Length == 0) - pci0Dev0Length++; - GT_REG_WRITE(PCI_0CS_0_BANK_SIZE,pci0Dev0Length-1); -} - -/******************************************************************** -* pci0MapDevice1MemorySpace - Maps PCI0 device1 memory spaces for the slave. -* -* Inputs: base and length of pci0 device1 -*********************************************************************/ -void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, - unsigned int pci0Dev1Length) -{ - pci0Dev1Base = pci0Dev1Base & 0xfffff000; - pci0Dev1Base = pci0Dev1Base | (pciReadConfigReg(0, - PCI_CS_1_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_CS_1_BASE_ADDRESS,SELF,pci0Dev1Base ); - if(pci0Dev1Length == 0) - pci0Dev1Length++; - GT_REG_WRITE(PCI_0CS_1_BANK_SIZE,pci0Dev1Length-1); -} - -/******************************************************************** -* pci0MapDevice2MemorySpace - Maps PCI0 device2 memory spaces for the slave. -* -* Inputs: base and length of pci0 device1 -*********************************************************************/ -void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, - unsigned int pci0Dev2Length) -{ - pci0Dev2Base = pci0Dev2Base & 0xfffff000; - pci0Dev2Base = pci0Dev2Base | (pciReadConfigReg(0, - PCI_CS_2_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_CS_2_BASE_ADDRESS,SELF,pci0Dev2Base ); - if(pci0Dev2Length == 0) - pci0Dev2Length++; - GT_REG_WRITE(PCI_0CS_2_BANK_SIZE,pci0Dev2Length-1); -} - -/******************************************************************** -* pci1MapDevice0MemorySpace - Maps PCI1 device0 memory spaces for the slave. -* -* Inputs: base and length of pci1 device0 -*********************************************************************/ -void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, - unsigned int pci1Dev0Length) -{ - pci1Dev0Base = pci1Dev0Base & 0xfffff000; - pci1Dev0Base = pci1Dev0Base | (pciReadConfigReg(1, - PCI_CS_0_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_CS_0_BASE_ADDRESS,SELF,pci1Dev0Base ); - if(pci1Dev0Length == 0) - pci1Dev0Length++; - GT_REG_WRITE(PCI_1CS_0_BANK_SIZE,pci1Dev0Length-1); -} - -/******************************************************************** -* pci1MapDevice1MemorySpace - Maps PCI1 device1 memory spaces for the slave. -* -* Inputs: base and lengthof pci1 device1 -*********************************************************************/ -void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, - unsigned int pci1Dev1Length) -{ - pci1Dev1Base = pci1Dev1Base & 0xfffff000; - pci1Dev1Base = pci1Dev1Base | (pciReadConfigReg(1, - PCI_CS_1_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_CS_1_BASE_ADDRESS,SELF,pci1Dev1Base); - if(pci1Dev1Length == 0) - pci1Dev1Length++; - GT_REG_WRITE(PCI_1CS_1_BANK_SIZE,pci1Dev1Length-1); -} - -/******************************************************************** -* pci1MapDevice2MemorySpace - Maps PCI1 device2 memory spaces for the slave. -* -* Inputs: base and length of pci1 device2 -*********************************************************************/ -void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, - unsigned int pci1Dev2Length) -{ - pci1Dev2Base = pci1Dev2Base & 0xfffff000; - pci1Dev2Base = pci1Dev2Base | (pciReadConfigReg(1, - PCI_CS_2_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_CS_2_BASE_ADDRESS,SELF,pci1Dev2Base); - if(pci1Dev2Length == 0) - pci1Dev2Length++; - GT_REG_WRITE(PCI_1CS_2_BANK_SIZE,pci1Dev2Length-1); -} - -/******************************************************************** -* pci0MapDevice3MemorySpace - Maps PCI0 devices 3 spaces for the slave. -* -* Inputs: base and length of pci0 device3. -*********************************************************************/ -void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, - unsigned int pci0Dev3Length) -{ - pci0Dev3Base = pci0Dev3Base & 0xfffff000; - pci0Dev3Base = pci0Dev3Base | (pciReadConfigReg(0, - PCI_CS_3_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_CS_3_BASE_ADDRESS,SELF,pci0Dev3Base ); - if(pci0Dev3Length == 0) - pci0Dev3Length++; - GT_REG_WRITE(PCI_0CS_3_BANK_SIZE , pci0Dev3Length-1); -} - -/******************************************************************** -* pci0MapBootDeviceMemorySpace - Maps PCI0 boot memory spaces for the slave. -* -* Inputs: base and length of pci0 boot. -*********************************************************************/ -void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, - unsigned int pci0DevBootLength) -{ - pci0DevBootBase = pci0DevBootBase & 0xfffff000; - pci0DevBootBase = pci0DevBootBase | (pciReadConfigReg(0, - PCI_BOOTCS_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_BOOTCS_BASE_ADDRESS,SELF,pci0DevBootBase ); - if(pci0DevBootLength == 0) - pci0DevBootLength++; - GT_REG_WRITE(PCI_0CS_BOOT_BANK_SIZE , pci0DevBootLength-1); -} - -/******************************************************************** -* pci1MapDevice3MemorySpace - Maps PCI1 devices 3 spaces for the slave. -* -* Inputs: base and length of pci1 device3. -*********************************************************************/ -void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, - unsigned int pci1Dev3Length) -{ - pci1Dev3Base = pci1Dev3Base & 0xfffff000; - pci1Dev3Base = pci1Dev3Base | (pciReadConfigReg(1, - PCI_CS_3_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_CS_3_BASE_ADDRESS,SELF,pci1Dev3Base ); - if(pci1Dev3Length == 0) - pci1Dev3Length++; - GT_REG_WRITE(PCI_1CS_3_BANK_SIZE , pci1Dev3Length-1); -} - -/******************************************************************** -* pci1MapBootDeviceMemorySpace - Maps PCI1 boot memory spaces for the slave. -* -* Inputs: base and length of pci1 boot. -*********************************************************************/ -void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, - unsigned int pci1DevBootLength) -{ - pci1DevBootBase = pci1DevBootBase & 0xfffff000; - pci1DevBootBase = pci1DevBootBase | (pciReadConfigReg(1, - PCI_BOOTCS_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_BOOTCS_BASE_ADDRESS,SELF,pci1DevBootBase ); - if(pci1DevBootLength == 0) - pci1DevBootLength++; - GT_REG_WRITE(PCI_1CS_BOOT_BANK_SIZE , pci1DevBootLength-1); -} - -/******************************************************************** -* pci0p2pMem0 - Maps PCI0 pci2pci memory0 spaces for the slave. -* -* Inputs: base and length of pci0P2pMem0 -*********************************************************************/ -void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, - unsigned int pci0P2pMem0Length) - -{ - pci0P2pMem0Base = pci0P2pMem0Base & 0xfffff000; - pci0P2pMem0Base = pci0P2pMem0Base | (pciReadConfigReg(0, - PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_P2P_MEM0_BASE_ADDRESS,SELF,pci0P2pMem0Base); - if(pci0P2pMem0Length == 0) - pci0P2pMem0Length++; - GT_REG_WRITE(PCI_0P2P_MEM0_BAR_SIZE , pci0P2pMem0Length-1); -} - -/******************************************************************** -* pci1p2pMem0 - Maps PCI1 pci2pci memory0 spaces for the slave. -* -* Inputs: base and length of pci1P2pMem0 -*********************************************************************/ -void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, - unsigned int pci1P2pMem0Length) -{ - pci1P2pMem0Base = pci1P2pMem0Base & 0xfffff000; - pci1P2pMem0Base = pci1P2pMem0Base | (pciReadConfigReg(1, - PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_P2P_MEM0_BASE_ADDRESS,SELF,pci1P2pMem0Base); - if(pci1P2pMem0Length == 0) - pci1P2pMem0Length++; - GT_REG_WRITE(PCI_1P2P_MEM0_BAR_SIZE , pci1P2pMem0Length-1); -} - -/******************************************************************** -* pci0p2pMem1 - Maps PCI0 pci2pci memory1 spaces for the slave. -* -* Inputs: base and length of pci0P2pMem1 -*********************************************************************/ -void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, - unsigned int pci0P2pMem1Length) -{ - pci0P2pMem1Base = pci0P2pMem1Base & 0xfffff000; - pci0P2pMem1Base = pci0P2pMem1Base | (pciReadConfigReg(0, - PCI_P2P_MEM1_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_P2P_MEM1_BASE_ADDRESS,SELF,pci0P2pMem1Base ); - if(pci0P2pMem1Length == 0) - pci0P2pMem1Length++; - GT_REG_WRITE(PCI_0P2P_MEM1_BAR_SIZE , pci0P2pMem1Length-1); -} - -/******************************************************************** -* pci1p2pMem1 - Maps PCI1 pci2pci memory1 spaces for the slave. -* -* Inputs: base and length of pci1P2pMem1 -*********************************************************************/ -void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, - unsigned int pci1P2pMem1Length) -{ - pci1P2pMem1Base = pci1P2pMem1Base & 0xfffff000; - pci1P2pMem1Base = pci1P2pMem1Base | (pciReadConfigReg(1, - PCI_P2P_MEM1_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_P2P_MEM1_BASE_ADDRESS,SELF,pci1P2pMem1Base ); - if(pci1P2pMem1Length == 0) - pci1P2pMem1Length++; - GT_REG_WRITE(PCI_1P2P_MEM1_BAR_SIZE , pci1P2pMem1Length-1); -} - -/******************************************************************** -* pci0p2pIO - Maps PCI0 pci2pci io spaces for the slave. -* -* Inputs: base and length of pci0P2pIo -*********************************************************************/ -void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, - unsigned int pci0P2pIoLength) -{ - pci0P2pIoBase = pci0P2pIoBase & 0xfffff000; - pci0P2pIoBase = pci0P2pIoBase | (pciReadConfigReg(0, - PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_P2P_I_O_BASE_ADDRESS,SELF,pci0P2pIoBase ); - if(pci0P2pIoLength == 0) - pci0P2pIoLength++; - GT_REG_WRITE(PCI_0P2P_I_O_BAR_SIZE , pci0P2pIoLength-1); -} - -/******************************************************************** -* pci1p2pIO - Maps PCI1 pci2pci io spaces for the slave. -* -* Inputs: base and length of pci1P2pIo -*********************************************************************/ -void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, unsigned int pci1P2pIoLength) - -{ - pci1P2pIoBase = pci1P2pIoBase & 0xfffff000; - pci1P2pIoBase = pci1P2pIoBase | (pciReadConfigReg(1, - PCI_P2P_I_O_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_P2P_I_O_BASE_ADDRESS,SELF,pci1P2pIoBase); - if(pci1P2pIoLength == 0) - pci1P2pIoLength++; - GT_REG_WRITE(PCI_1P2P_I_O_BAR_SIZE , pci1P2pIoLength-1); -} - -/******************************************************************** -* pci0CPU - Maps PCI0 cpu spaces for the slave. -* -* Inputs: base and length of pci0Cpu -*********************************************************************/ -void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs) -{ - pci0CpuBase = pci0CpuBase & 0xfffff000; - pci0CpuBase = pci0CpuBase | (pciReadConfigReg(0, - PCI_CPU_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(0,PCI_CPU_BASE_ADDRESS,SELF,pci0CpuBase ); - if(pci0CpuLengs == 0) - pci0CpuLengs++; - GT_REG_WRITE(PCI_0CPU_BAR_SIZE , pci0CpuLengs-1); -} - -/******************************************************************** -* pci1CPU - Maps PCI1 cpu spaces for the slave. -* -* Inputs: base and length of pci1Cpu -*********************************************************************/ -void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs) -{ - pci1CpuBase = pci1CpuBase & 0xfffff000; - pci1CpuBase = pci1CpuBase | (pciReadConfigReg(1, - PCI_CPU_BASE_ADDRESS,SELF) & 0x00000fff); - pciWriteConfigReg(1,PCI_CPU_BASE_ADDRESS,SELF,pci1CpuBase ); - if(pci1CpuLengs == 0) - pci1CpuLengs++; - GT_REG_WRITE(PCI_1CPU_BAR_SIZE , pci1CpuLengs-1); -} -#endif - /******************************************************************** * pciSetRegionFeatures - This function modifys one of the 8 regions with @@ -1231,39 +452,6 @@ bool pciArbiterDisable(PCI_HOST host) return true; } -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ(pci_arbiter_control[host],®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE(pci_arbiter_control[host],regData & regData); - return true; -} - /******************************************************************** * pciParkingDisable - Park on last option disable, with this function you can * disable the park on last mechanism for each agent. @@ -1300,74 +488,6 @@ bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, return true; } -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ(pci_arbiter_control[host],®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE(pci_arbiter_control[host],regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection(PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ(pci_arbiter_control[host],®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE(pci_arbiter_control[host],regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig(PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE(pci_p2p_configuration[host],regData); - return true; -} - /******************************************************************** * pciSetRegionSnoopMode - This function modifys one of the 4 regions which * supports Cache Coherency in the PCI_n interface. @@ -1408,160 +528,150 @@ bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,PCI_SNOOP_TYPE return true; } -PCI_DEVICE * -pciFindDevice(unsigned short vendorID, unsigned short deviceID) +/* + * + */ + +static int gt_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, + int offset, u32* value) { - int host; - PCI_DEVICE *dev; - for(host=PCI_HOST0;host<=PCI_HOST1;host++) { - for(dev=pci_dev_list[host];dev->deviceNum!=-1;dev++) { - if(vendorID==dev->venID && deviceID==dev->deviceID) return dev; - } - } - return NULL; + *value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset, dev); + return 0; } -static const char * const pci_type_legend[]= - {"32 bit","below 1M","64 bit", "reserved"}; +static int gt_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, + int offset, u32 value) +{ + pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, dev, value); + return 0; +} -static const char * const pci_timing_legend[]= - {"Slow","Medium","Fast","???"}; +static struct pci_ops gt_pci_ops = { + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword +}; -static int pci_alloc_bar(PCI_DEVICE *dev, int index) -{ - PCI_BAR *bar=&dev->bar[index]; - unsigned int *alloc, reg=BAR0+index*4; +/* + * + */ - if(!bar) { - printf("error, no bar\n"); - return -1; - } +static void gt_setup_ide(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[]={8,4,8,4,0,0}; + u32 bar_response, bar_value; + int bar; - if (bar->type & BAR_SEL_MEM_IO) { - alloc=&pci_io_bar_alloc[dev->host]; - } else { - alloc=&pci_mem_bar_alloc[dev->host]; - } + for (bar=0; bar<6; bar++) + { + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, 0x0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, &bar_response); - bar->base=((*alloc)+bar->size-1)&~(bar->size-1); - pciWriteConfigReg(dev->host, reg, dev->deviceNum, bar->base); - bar->base=pciReadConfigReg(dev->host, reg, dev->deviceNum)&(~1); - *alloc=bar->base+bar->size; + pciauto_region_allocate(bar_response & PCI_BASE_ADDRESS_SPACE_IO ? + hose->pci_io : hose->pci_mem, ide_bar[bar], &bar_value); - return 0; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, bar_value); + } } -#ifdef DEBUG -static char * smart_print(unsigned val, char *buf) +static void gt_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - char *unit="b"; + unsigned char pin, irq; - if(val>_1G) val/=_1G, unit="G"; - else if(val>_1M) val/=_1M, unit="M"; - else if(val>1024) val/=1024, unit="k"; + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - sprintf(buf, "%3d%s", val, unit); - return buf; -} -#endif - -static void setup_pci_devices(PCI_DEVICE *list) -{ - PCI_DEVICE *dev; - int i,irq_pin; - int command=0; - - for(dev=list;dev->deviceNum!=-1;dev++) { - int statcmd = pciReadConfigReg(dev->host,PCI_STATUS_AND_COMMAND, - dev->deviceNum); - - printf("%2d: %04x %04x (%s)\n", dev->deviceNum, dev->venID, - dev->deviceID, dev->type); - - /* latency=64, cache linesize (in words), clear bist */ - pciWriteConfigReg(dev->host, - PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE, - dev->deviceNum, (0x04 << 8) | (CACHE_LINE_SIZE / 4)); - - command = 0; - if(dev->deviceNum!=0) { - statcmd &= ~(MASTER_ENABLE | MEMORY_ENABLE | I_O_ENABLE); - /* disable this device */ - pciWriteConfigReg(dev->host,PCI_STATUS_AND_COMMAND,dev->deviceNum, - statcmd); - - } - - irq_pin=pciReadConfigReg(dev->host,PCI_INTERRUPT_PIN_AND_LINE, dev->deviceNum); - if(((irq_pin>>8)&0xff)==1) { /* only allow INT A */ - unsigned char irq=pci_irq_swizzle[dev->host][dev->deviceNum]; - if(irq) { - irq_pin&=~0xff; - irq_pin|=(irq|64); - printf(" IRQ %d\n", irq); - pciWriteConfigReg(dev->host,PCI_INTERRUPT_PIN_AND_LINE, dev->deviceNum, irq_pin); - } - } - - /* for each BAR */ - for(i=0;i<5;i++) { - if(dev->bar[i].size) { - if(dev->deviceNum!=0) { - command |= MASTER_ENABLE; - - if(dev->bar[i].type & BAR_SEL_MEM_IO) command |= I_O_ENABLE; - else command |= MEMORY_ENABLE; - - pci_alloc_bar(dev, i); - } -#ifdef DEBUG - { - char buf[10]; - printf(" BAR %d: %08x %s %s, %s%s\n",i, - dev->bar[i].base, - smart_print(dev->bar[i].size, buf), - dev->bar[i].type & BAR_SEL_MEM_IO ?"I/O":"MEM", - pci_type_legend[(dev->bar[i].type&BAR_MEM_TYPE_MASK)>>1], - dev->bar[i].type & BAR_PREFETCHABLE ?", prefetchable":"" - ); - } -#endif - } - } - - if(command) { - pciWriteConfigReg(dev->host,PCI_STATUS_AND_COMMAND,dev->deviceNum, - command | statcmd); - statcmd = pciReadConfigReg(dev->host,PCI_STATUS_AND_COMMAND, - dev->deviceNum); - } - - printf(" %s%s%s%s%dMHz, %s%s timing\n", - statcmd & (1<<0)?"I/O, ":"", - statcmd & (1<<1)?"MEM, ":"", - statcmd & (1<<2)?"Master, ":"", - statcmd & (1<<20)?"Capability list, ":"", - statcmd & (1<<21)?66:33, - statcmd & (1<<23)?"Fast back to back capable, ":"", - pci_timing_legend[(statcmd>>25)&3]); + if(pin == 1) { /* only allow INT A */ + irq = pci_irq_swizzle[(PCI_HOST)hose->cfg_addr][PCI_DEV(dev)]; + if(irq) + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } } +struct pci_config_table gt_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, + + { } +}; + +struct pci_controller pci0_hose = { + fixup_irq: gt_fixup_irq, + config_table: gt_config_table, +}; + +struct pci_controller pci1_hose = { + fixup_irq: gt_fixup_irq, + config_table: gt_config_table, +}; + void pci_init(bd_t *bd) { - PCI_HOST host; + pci0_hose.first_busno = 0; + pci0_hose.last_busno = 0xff; - printf("PCI scan...\n"); - for(host=PCI_HOST0; host<=PCI_HOST1; host++) { - pciArbiterEnable(host); + /* PCI memory space */ + pci_set_region(pci0_hose.regions + 0, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_MEM_SIZE, + PCI_REGION_MEM); - pciParkingDisable(host,1,1,1,1,1,1,1); - memset(pci_dev_list[host],0,sizeof(pci_dev_list[host])); - printf("PCI %d:\n",host); - pciScanDevices(host,pci_dev_list[host],32); - setup_pci_devices(pci_dev_list[host]); + /* PCI I/O space */ + pci_set_region(pci0_hose.regions + 1, + CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, + CFG_PCI0_IO_SIZE, + PCI_REGION_IO); - PCI_MEMORY_ENABLE(host, SELF); - } + pci0_hose.region_count = 2; + + pci0_hose.ops = >_pci_ops; + pci0_hose.cfg_addr = (unsigned int*) PCI_HOST0; + + pci_register_hose(&pci0_hose); + + pciArbiterEnable(PCI_HOST0); + pciParkingDisable(PCI_HOST0,1,1,1,1,1,1,1); + + pci0_hose.last_busno = pci_hose_scan(&pci0_hose); + + PCI_MEMORY_ENABLE(PCI_HOST0, SELF); + + pci1_hose.first_busno = pci0_hose.last_busno + 1; + pci1_hose.last_busno = 0xff; + + /* PCI memory space */ + pci_set_region(pci1_hose.regions + 0, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(pci1_hose.regions + 1, + CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + pci1_hose.region_count = 2; + + pci1_hose.ops = >_pci_ops; + pci1_hose.cfg_addr = (unsigned int*) PCI_HOST1; + + pci_register_hose(&pci1_hose); + + pciArbiterEnable(PCI_HOST1); + pciParkingDisable(PCI_HOST1,1,1,1,1,1,1,1); + + pci1_hose.last_busno = pci_hose_scan(&pci1_hose); + + PCI_MEMORY_ENABLE(PCI_HOST1, SELF); } diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index e6eec84..3d53a2f 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -30,10 +30,15 @@ #include #include #include +#include #include "serial.h" #include "mpsc.h" -#include "ns16550.h" + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, + (NS16550_t) CFG_NS16550_COM2 }; +#endif #ifdef CONFIG_MPSC @@ -41,7 +46,7 @@ void serial_init (unsigned long dummy, int baudrate) { #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) - int clock_divisor = 230400/baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / baudrate; #endif mpsc_init(baudrate); @@ -87,7 +92,7 @@ serial_setbrg (unsigned long dummy, int baudrate) void serial_init (unsigned long dummy, int baudrate) { - int clock_divisor = 230400/baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / baudrate; #ifdef CFG_INIT_CHAN1 (void)NS16550_init(0, clock_divisor); @@ -121,7 +126,7 @@ serial_tstc(void) void serial_setbrg (unsigned long dummy, int baudrate) { - int clock_divisor = 230400/baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / baudrate; #ifdef CFG_INIT_CHAN1 NS16550_reinit(COM_PORTS[0], clock_divisor); diff --git a/board/mousse/Makefile b/board/mousse/Makefile index 3a3f2f3..6d9df89 100644 --- a/board/mousse/Makefile +++ b/board/mousse/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o ns16550.o serial.o dc2114x.o\ - m48t59y.o pci.o flash.o -#pci.o +OBJS = $(BOARD).o m48t59y.o pci.o flash.o $(LIB): .depend $(OBJS) $(AR) crv $@ $^ diff --git a/board/mousse/dc2114x.c b/board/mousse/dc2114x.c deleted file mode 100644 index 0e324ac..0000000 --- a/board/mousse/dc2114x.c +++ /dev/null @@ -1,920 +0,0 @@ -/* - * MOUSSE Onboard DEC 21143-TD (DC1096B) Ethernet support. - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * DEC 21143 Ethernet driver. - */ -#include -#include -#include -#include "pci.h" -#include "mousse.h" -/* - * PCI Registers. - */ -#define PCI_VENDOR_ID PCI_CFG_VENDOR_ID -#define PCI_COMMAND PCI_CFG_COMMAND -#define PCI_CLASS_REVISION PCI_CFG_REVISION -#define PCI_BASE_ADDRESS_0 PCI_CFG_BASE_ADDRESS_0 -#define PCI_CFDA_PSM PCI_CFG_MODE - -#define PCI_COMMAND_IO PCI_CMD_IO_ENABLE -#define PCI_COMMAND_MASTER PCI_CMD_MASTER_ENABLE - -#define CFRV_RN 0x000000f0 /* Revision Number */ -#define CBIO_MASK -128 - -#define WAKEUP 0x00 /* Power Saving Wakeup */ -#define SLEEP 0x80 /* Power Saving Sleep Mode */ - -#define DC21140_VENDOR_ID 0x1011 -#define DC21140_DEVICE_ID 0x0009 -#define DC21143_VENDOR_ID 0x1011 -#define DC21143_DEVICE_ID 0x0019 - - -#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ -#define DC2114x_DID 0x1900 /* Unique Device ID # */ -#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -#define DC21142 (DC2114x_DID | 0x0010) -#define DC21143 (DC2114x_DID | 0x0030) - -#define is_DC2114x ((vendor == DC21143_VENDOR_ID) &&\ - (device == DC21143_DEVICE_ID)) - -/* - * DEC 2114x Ethernet chip registers. - */ -#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */ -#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */ -#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */ -#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */ -#define DE4X5_STS iobase + 0x028 /* Status Register */ -#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */ -#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */ -#define DE4X5_TXRX iobase + 0x070 /* SIA Transmit and Receive Register */ -#define DE4X5_GPPR iobase + 0x078 /* General Purpose Port register */ -#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */ - -/* Defines for Bus mode register */ -#define DE_BMR_BE 0x00000080 /* CSR0: Big Endian mode (bit 7) */ -#define DE_BMR_TAP_02 0x00000002 /* CSR0: Tx poll every 200 usec */ -#define DE_BMR_TAP_08 0x00000004 /* CSR0: Tx poll every 800 usec */ -#define DE_BMR_TAP_16 0x00000006 /* CSR0: Tx poll every 1.6 msec */ -#define DE_BMR_TAP_012 0x00000008 /* CSR0: Tx poll every 12.8 usec */ -#define DE_BMR_TAP_025 0x0000000A /* CSR0: Tx poll every 25.6 usec */ -#define DE_BMR_TAP_051 0x0000000C /* CSR0: Tx poll every 51.2 usec */ -#define DE_BMR_TAP_102 0x0000000E /* CSR0: Tx poll every 102.4 usec */ -#define DE_BMR_TAP_MSK 0x0000000E -#define DE_BMR_TAP_SHF 16 - -#define DE_BMR_CAL_08 0x00000010 /* CSR0: Cache adrs aligned 8 lwords */ -#define DE_BMR_CAL_16 0x00000020 /* CSR0: Cache adrs aligned 16 lwords */ -#define DE_BMR_CAL_32 0x00000030 /* CSR0: Cache adrs aligned 32 lwords */ -#define DE_BMR_CAL_MSK 0x00000030 -#define DE_BMR_CAL_SHF 10 - -#define DE_BMR_PBL_01 0x00000040 /* CSR0: DMA burst len 1 lword */ -#define DE_BMR_PBL_02 0x00000080 /* CSR0: DMA burst len 2 lwords */ -#define DE_BMR_PBL_04 0x00000100 /* CSR0: DMA burst len 4 lwords */ -#define DE_BMR_PBL_08 0x00000200 /* CSR0: DMA burst len 8 lwords */ -#define DE_BMR_PBL_16 0x00000400 /* CSR0: DMA burst len 16 lwords */ -#define DE_BMR_PBL_32 0x00000800 /* CSR0: DMA burst len 32 lwords */ -#define DE_BMR_PBL_MSK 0x00000FC0 -#define DE_BMR_PBL_SHF 2 -#define DE_BMR_RML 0x00002000 /* CSR0: PCI memory-read-multiple */ - - -/* - * Descriptor RDES0/TDES0 (status) Error summary bit defines - */ -#define ES_RX_FF (1<<30) -#define ES_RX_FL (1<<23) -#define ES_TX_FL (1<<23) -#define ES_TX_ES (1<<15) -#define ES_RX_DE (1<<14) -#define ES_TX_TO (1<<14) -#define ES_RX_RF (1<<11) -#define ES_TX_LI (1<<11) -#define ES_RX_TL (1<<7) -#define ES_TX_LC (1<<9) -#define ES_TX_EC (1<<8) -#define ES_TX_TL (1<<7) -#define ES_RX_CS (1<<6) -#define ES_RX_RW (1<<4) -#define ES_RX_RE (1<<3) -#define ES_RX_DB (1<<2) -#define ES_TX_LF (1<<2) -#define ES_RX_CE (1<<1) -#define ES_TX_UF (1<<1) -#define ES_RX_Z (1<<0) -#define ES_TX_DE (1<<0) - -/* - * Defines for status bits in STS status register. - */ -#define STS_LC (1<<27) -#define STS_GPI (1<<26) -#define STS_NIS (1<<16) -#define STS_AIS (1<<15) -#define STS_ERI (1<<14) -#define STS_FBE (1<<13) -#define STS_LNF (1<<12) -#define STS_GTE (1<<11) -#define STS_ETI (1<<10) -#define STS_RWT (1<<9) -#define STS_RPS (1<<8) -#define STS_RU (1<<7) -#define STS_RI (1<<6) -#define STS_UNF (1<<5) -#define STS_ANC (1<<4) -#define STS_TJT (1<<3) -#define STS_TU (1<<2) -#define STS_TPS (1<<1) -#define STS_TI (1<<0) - -/* - * Masks for STS receive/transmit process state, error bits - * See Also: Intel 21143 H/W Ref: Table 3-67 - */ -#define STS_ES_EB_MASK 0x03800000 -#define STS_ES_EB_SHIFT 20 -#define STS_ES_TS_MASK 0x00700000 -#define STS_ES_TS_SHIFT 20 -#define STS_ES_RS_MASK 0x000E0000 -#define STS_ES_RS_SHIFT 16 - -/* - * Misc Register bits. - */ -#define BMR_SWR 0x00000001 /* Software Reset */ -#define STS_TS 0x00700000 /* Transmit Process State */ -#define STS_RS 0x000e0000 /* Receive Process State */ - -/* OMR : (CSR6) Operation Mode Register bit defines */ -#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -#define OMR_PS 0x00040000 /* Port Select */ -#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ -#define OMR_SC 0x80000000 /* special capture effect enable */ -#define OMR_RA 0x40000000 /* receive all */ -#define OMR_SCR 0x01000000 /* scrambler mode */ -#define OMR_PCS 0x00800000 /* PCS function */ -#define OMR_TTM 0x00400000 /* tx threshold mode */ -#define OMR_SF 0x00200000 /* store and forward */ -#define OMR_HBD 0x00080000 /* heartbeat disable */ -#define OMR_CAE 0x00020000 /* capture effect enable */ -#define OMR_THR_072 0x00000000 /* threshold bytes 72 */ -#define OMR_THR_096 0x00004000 /* threshold bytes 96 */ -#define OMR_THR_128 0x00008000 /* threshold bytes 128 */ -#define OMR_THR_160 0x0000C000 /* threshold bytes 160 */ - -#define OMR_ST 0x00002000 /* start/stop Xmit command */ -#define OMR_FC 0x00001000 /* Force collision mode */ -#define OMR_OM_EL 0x00000800 /* External loopback mode */ -#define OMR_OM_IL 0x00000400 /* Internal loopback mode */ -#define OMR_OM_NOR 0x00000000 /* normal mode */ -#define OMR_FD 0x00000200 /* Full Duplex mode */ -#define OMR_PM 0x00000080 /* Pass All Multicast */ -#define OMR_PR 0x00000040 /* promiscuous mode */ -#define OMR_SB 0x00000020 /* Start/Stop Back off counter */ -#define OMR_IF 0x00000010 /* inverse filtering [RO] */ -#define OMR_PB 0x00000008 /* pass bad frames */ -#define OMR_HO 0x00000004 /* hash only filter mode [RO] */ -#define OMR_SR 0x00000002 /* Start/Stop Receive */ -#define OMR_HP 0x00000001 /* hash/perfect filter mode [RO] */ - -/* - * DMA Descriptor bits. - */ -#define R_OWN 0x80000000 /* Own Bit */ -#define RD_RER 0x02000000 /* Receive End Of Ring */ -#define RD_LS 0x00000100 /* Last Descriptor */ -#define RD_ES 0x00008000 /* Error Summary */ -#define TD_TER 0x02000000 /* Transmit End Of Ring */ -#define T_OWN 0x80000000 /* Own Bit */ -#define TD_LS 0x40000000 /* Last Segment */ -#define TD_FS 0x20000000 /* First Segment */ -#define TD_ES 0x00008000 /* Error Summary */ -#define TD_SET 0x08000000 /* Setup Packet */ -#define TD_AC (1<<26) /* Add CRC Disable: Disable CRC Addition */ -#define TD_DPD (1<<23) /* Disable padding on frames < 64 */ - -#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ -#define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define SROM_SR 0x00000800 /* Select Serial ROM when set */ - -#define DT_IN 0x00000004 /* Serial Data In */ -#define DT_CLK 0x00000002 /* Serial ROM Clock */ -#define DT_CS 0x00000001 /* Serial ROM Chip Select */ - -#define POLL_DEMAND 1 - -#define RESET_DE4X5 {\ - int i;\ - i=inl(DE4X5_BMR);\ - udelay(1000);\ - outl(i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ - outl(i, DE4X5_BMR);\ - udelay(1000);\ - for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\ - udelay(1000);\ -} - -#define START_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr |= OMR_ST | OMR_SR;\ - outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ -} - -#define STOP_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr &= ~(OMR_ST|OMR_SR);\ - outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ -} - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ -#define RX_BUFF_SZ PKTSIZE_ALIGN - -#define TOUT_LOOP 1000000 - -#define SETUP_FRAME_LEN 192 -#define ETH_ALEN 6 - -struct de4x5_desc { - volatile s32 status; -#define tdes0 status -#define rdes0 status - u32 des1; -#define tdes1 des1 -#define rdes1 des1 - u32 buf; -#define tdes2 buf -#define rdes2 buf - u32 next; -#define tdes3 next -#define rdes3 next -}; - - -static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ - -static char rxRingSize; -static char txRingSize; - -static u32 iobase, eth_online; -static int device=0, vendor=0, devno=0xd, bus=0, func=0; - -static void send_setup_frame(bd_t * bis); -static void check_hw_addr(bd_t * bis); -static short srom_rd(u_long address, u_char offset); -static void srom_latch(u_int command, u_long address); -static void srom_command(u_int command, u_long address); -static void srom_address(u_int command, u_long address, u_char offset); -static short srom_data(u_int command, u_long address); -static void sendto_srom(u_int command, u_long addr); -static int getfrom_srom(u_long addr); - -static inline int inl(u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr)); -} - -static inline void outl (int command, u_long addr) -{ - *(volatile u_long *)(addr) = cpu_to_le32(command); -} - - -void dc21x4x_init(bd_t *bis) -{ - int cfrv; - uint32 tmp; - - /* Find PCI device */ - if ( OK != pci_dev_find(DC21143_VENDOR_ID, - DC21143_DEVICE_ID,0, - &bus,&devno,&func)){ - printf("Error: Can not find an ethernet card on the PCI bus\n"); - goto Done; - } - printf("eth0: DC21143 Ethernet adapter @0x%x" - "(bus=%d, device=%d, func=%d)\n", - PCI_ENET_MEMADDR, bus,devno,func); - - /* Check revision */ - pci_config_inl(bus,devno,func, PCI_CFG_VENDOR_ID,&vendor); - device = (vendor >> 16) & 0x0000ffff; - vendor = vendor & 0x0000ffff; - if (! is_DC2114x){ - printf("Error: The chip is not DC2114x.\n"); - goto Done; - } - - pci_config_inl(bus,devno,func, PCI_CFG_REVISION, &cfrv); - /* Get the chip configuration revision register. - */ - device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); - - if (device != DC21143){ - printf("Error: The chip is not DC21143.\n"); - goto Done; - } - - if(OK != pci_dev_config(bus, devno, func, - PCI_ENET_IOADDR, - PCI_ENET_MEMADDR, - PCI_CMD_MEM_ENABLE | - PCI_CMD_MEM_ENABLE | - PCI_CMD_MASTER_ENABLE)){ - - printf("DEC 21143 PCI Device configuration failed.\n"); - goto Done; - } - - /* Set IRQ (ILINE) */ - pci_config_outl(bus, devno, func, - PCI_CFG_DEV_INT_LINE, MOUSSE_IRQ_ENET); - - /* - * Turn off snooze mode. - */ - pci_config_inl(bus,devno,func,0x40, &tmp); - if(tmp) - pci_config_outl(bus,devno,func,0x40,0x0); - - /* Read back memory base address */ - pci_config_inl(bus, devno, func, - PCI_CFG_BASE_ADDRESS_0, &iobase); - if (iobase == 0xffffffff){ - printf("Error: Can not set I/O base register (MBAR0).\n"); - goto Done; - } - - /* Clear status bits */ - iobase &= CBIO_MASK; - - /* Disable doze mode */ - pci_config_outl(bus, devno, func, PCI_CFG_MODE, WAKEUP); - - check_hw_addr(bis); - udelay(10 * 1000); - - /* Reset Chip */ - RESET_DE4X5; - - /* - * Initialization - * - * Full Duplex Mode: MII/SYM Mode: Port Select Procedure. - * CSR13<15:0> = 0 (DE4X5_SICR) - * CSR14<15:0> = 0 (DE4X5_TXRX) - * CSR15<15:0> = 0008 (DE4X5_GPPR) - * CSR6 = 1,1 (DE4X5_OMR) - * CSR6 = 00 - * - */ - /* CSR13, CSR14 */ - tmp = inl(DE4X5_SICR); - tmp &= 0xffff0000; - outl(tmp, DE4X5_SICR); - tmp = inl(DE4X5_TXRX); - tmp &= 0xffff0000; - outl(tmp, DE4X5_TXRX); - - /* AUI/BNC Mode */ - tmp = inl(DE4X5_GPPR); - tmp &= 0xffff0000; - tmp |= 0x8; - outl(tmp, DE4X5_GPPR); - - /* - * CSR6: Setup to work with transmit threshold mode, - * port select, pass all multicast, full-duplex. - */ - - tmp = inl(DE4X5_OMR); - tmp |= (OMR_SF|OMR_SDP|OMR_TTM|OMR_PS|OMR_PM|OMR_FD); - outl(tmp, DE4X5_OMR); - - eth_online = 1; - /* pci_dev_show(0); */ - Done: - return; -} - -void -dc21x4x_log_error(void) -{ - u32 stat = le32_to_cpu(tx_ring[tx_new].tdes0); - printf("TX (TDES0) error status = 0x%08X\n", stat); - if(stat & T_OWN) - printf("TXO "); - if(stat & R_OWN) - printf("RXO "); - if(stat & ES_TX_ES) - printf("ES "); - if(stat & ES_TX_DE) - printf("DE "); - if(stat & ES_TX_UF) - printf("UF "); - if(stat & ES_TX_EC) - printf("EC "); - if(stat & ES_TX_LI) - printf("Lost Carrier "); - if(stat & ES_TX_LC) - printf("LC "); - if(stat & ES_TX_TO) - printf("TJBR Timeout "); - if(stat & ES_TX_LF) - printf("Link Fail "); - printf("\nTX TDES1=0x%x (tbs1=%d tbs2=%d) TDES2=0x%x TDES3=0x%x\n", - le32_to_cpu(tx_ring[tx_new].tdes1), - le32_to_cpu(tx_ring[tx_new].tdes1) & 0x000007ff, - (le32_to_cpu(tx_ring[tx_new].tdes1) & 0x003ff800) >> 11, - le32_to_cpu(tx_ring[tx_new].tdes2), - le32_to_cpu(tx_ring[tx_new].tdes3) - ); -#if RX_DEBUG - u32 stat = le32_to_cpu(rx_ring[rx_new].status); - printf("RX (RDES0) error status = 0x%08X\n", stat); - if(stat & T_OWN) - printf("TXO "); - if(stat & R_OWN) - printf("RXO "); - if(stat & ES_RX_FF) - printf("FF "); - if(stat & ES_RX_FL) - printf("FL "); - if(stat & ES_RX_DE) - printf("DE "); - if(stat & ES_RX_RF) - printf("RF "); - if(stat & ES_RX_TL) - printf("TL "); - if(stat & ES_RX_CS) - printf("CS "); - if(stat & ES_RX_RW) - printf("RW "); - if(stat & ES_RX_RE) - printf("MII "); - if(stat & ES_RX_DB) - printf("DB "); - if(stat & ES_RX_CE) - printf("CE "); -#endif - - printf("status: "); - stat = inl(DE4X5_STS); - - if(stat & STS_LC) - printf("lc "); - if(stat & STS_GPI) - printf("gpi "); - if(stat & STS_NIS) - printf("nis "); - if(stat & STS_AIS) - printf("ais "); - if(stat & STS_ERI) - printf("eri "); - if(stat & STS_FBE) - printf("fbe "); - if(stat & STS_LNF) - printf("lnf "); - if(stat & STS_GTE) - printf("gte "); - if(stat & STS_ETI) - printf("eti "); - if(stat & STS_RWT) - printf("rwt "); - if(stat & STS_RPS) - printf("rps "); - if(stat & STS_RU) - printf("ru "); - if(stat & STS_RI) - printf("ri "); - if(stat & STS_UNF) - printf("unf "); - if(stat & STS_ANC) - printf("link "); - if(stat & STS_TJT) - printf("tjt "); - if(stat & STS_TU) - printf("tu "); - if(stat & STS_TPS) - printf("tps "); - if(stat & STS_TI) - printf("ti "); - printf("\n"); - - printf("eb=%d tps=%d rps=%d\n", - (stat & STS_ES_EB_MASK) >> STS_ES_EB_SHIFT, - (stat & STS_ES_TS_MASK) >> STS_ES_TS_SHIFT, - (stat & STS_ES_RS_MASK) >> STS_ES_RS_SHIFT); -} - - - - -int eth_init(bd_t *bis) -{ - int i; - - dc21x4x_init(bis); - - if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; - } - - outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); - - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].status = cpu_to_le32(R_OWN); - rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32((u_long)NetRxPackets[i]); - rx_ring[i].next = 0; - } - - for (i=0; i < NUM_TX_DESC; i++) - { - tx_ring[i].status = 0; - tx_ring[i].des1 = 0; - tx_ring[i].buf = 0; - tx_ring[i].next = 0; - } - - rxRingSize = NUM_RX_DESC; - txRingSize = NUM_TX_DESC; - - /* Write the end of list marker to the descriptor lists. - */ - rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); - - /* Tell the adapter where the TX/RX rings are located. - */ - outl((u_long)&rx_ring, DE4X5_RRBA); - outl((u_long)&tx_ring, DE4X5_TRBA); - - START_DE4X5; - - tx_new = 0; - rx_new = 0; - - send_setup_frame(bis); - -Done: - - return 0; -} - -int eth_send(volatile void *packet, int length) -{ - int status = 0; - int i; - -#if TX_DEBUG - unsigned char* pkt = (unsigned char*)packet; - printf("\neth_send: frame data follows ...\n============\n"); - for( i = 0; i < length; i++){ - printf("%d ", pkt[i]); - if(i > 0 && ((i % 16) == 0)) - printf("\n"); - } - printf("\n=============\n"); -#endif - - if (length <= 0) - { - printf("eth: bad packet size: %d\n", length); - goto out; - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - tx_ring[tx_new].next = 0; - tx_ring[tx_new].buf = cpu_to_le32((u_long)packet); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(inl(DE4X5_STS), DE4X5_STS); /* Clear status bits */ - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } -#if 0 - if(inl(DE4X5_STS) & STS_TU){ - printf("Transmit buffer unavailable. Retrying ...\n"); - outl(inl(DE4X5_STS), DE4X5_STS); /* Clear status bits */ - goto start; - } -#endif - - /* Determine which error, if any, we detected. - * See also: Intel 21143 Hardware Reference - * Table 3-66 - * Ignore: Transmit Process stopped due to Buffer Unavailable. - */ -#if 1 - if ((le32_to_cpu(tx_ring[tx_new].status) & TD_ES) && - !(inl(DE4X5_STS) & STS_TU)) -#else - if ((le32_to_cpu(tx_ring[tx_new].status) & TD_ES)) -#endif - { - dc21x4x_log_error(); - status++; - } - - out: - return status; -} - -int eth_rx(void) -{ - s32 status; - int length = 0; - - for ( ; ; ) - { - status = (s32)le32_to_cpu(rx_ring[rx_new].status); - - if (status & R_OWN) - { - break; - } - - if (status & RD_LS) - { - /* Valid frame status. - */ - if (status & RD_ES) - { - /* There was an error. - */ - printf("RX error status = 0x%08X\n", status); - } - else - { - /* A valid frame received. - */ - length = (le32_to_cpu(rx_ring[rx_new].status) >> - 16); - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(NetRxPackets[rx_new], length - 4); - } - - /* Change buffer ownership for this frame, back - * to the adapter. - */ - rx_ring[rx_new].status = cpu_to_le32(R_OWN); - } - - /* Update entry information. - */ - rx_new = (rx_new + 1) % rxRingSize; - } - - return length; -} - -void eth_halt(void) -{ - if(eth_online){ - STOP_DE4X5; - outl(0, DE4X5_SICR); - pci_config_outb(bus, device, func, PCI_CFG_MODE, SLEEP); - eth_online = 0; - } -} - -static void check_hw_addr(bd_t *bis) -{ - unsigned char hw_addr[ETH_ALEN]; - u_short tmp, *p = (short *)(&hw_addr[0]); - int i, j = 0; - - for (i = 0; i < (ETH_ALEN >> 1); i++) - { - tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if ((j == 0) || (j == 0x2fffd)) - { - // printf("Warning: can't read HW address from SROM.\n"); - goto Done; - } - - for (i = 0; i < ETH_ALEN; i++) - { - if (hw_addr[i] != bis->bi_enetaddr[i]) - { - printf("Warning: HW addresses don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - goto Done; - } - } - -Done: - return; -} - -static void send_setup_frame(bd_t *bis) -{ - int i; - char setup_frame[SETUP_FRAME_LEN]; - char * pa = &setup_frame[0]; - - memset(pa, 0xff, SETUP_FRAME_LEN); - - for (i = 0; i < ETH_ALEN; i++) - { - *(pa + (i & 1)) = bis->bi_enetaddr[i]; - if (i & 0x01) - { - pa += 4; - } - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)&setup_frame[0]); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - - if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) - { - printf("Setup Frame TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - } -out: - return; -} - - /* SROM Read. - */ -static short -srom_rd(u_long addr, u_char offset) -{ - sendto_srom(SROM_RD | SROM_SR, addr); - - srom_latch(SROM_RD | SROM_SR | DT_CS, addr); - srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data(SROM_RD | SROM_SR | DT_CS, addr); -} - -static void -srom_latch(u_int command, u_long addr) -{ - sendto_srom(command, addr); - sendto_srom(command | DT_CLK, addr); - sendto_srom(command, addr); - - return; -} - -static void -srom_command(u_int command, u_long addr) -{ - srom_latch(command, addr); - srom_latch(command, addr); - srom_latch((command & 0x0000ff00) | DT_CS, addr); - - return; -} - -static void -srom_address(u_int command, u_long addr, u_char offset) -{ - int i; - signed char a; - - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) { - srom_latch(command | ((a < 0) ? DT_IN : 0), addr); - } - udelay(1); - - i = (getfrom_srom(addr) >> 3) & 0x01; - - return; -} - -static short -srom_data(u_int command, u_long addr) -{ - int i; - short word = 0; - s32 tmp; - - for (i=0; i<16; i++) { - sendto_srom(command | DT_CLK, addr); - tmp = getfrom_srom(addr); - sendto_srom(command, addr); - - word = (word << 1) | ((tmp >> 3) & 0x01); - } - - sendto_srom(command & 0x0000ff00, addr); - - return word; -} - -static void -sendto_srom(u_int command, u_long addr) -{ - outl(command, addr); - udelay(1); - - return; -} - -static int -getfrom_srom(u_long addr) -{ - s32 tmp; - - tmp = inl(addr); - udelay(1); - - return tmp; -} - diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c index f195fe3..f754533 100644 --- a/board/mousse/mousse.c +++ b/board/mousse/mousse.c @@ -92,11 +92,3 @@ int misc_init_f (void) return 0; } - -/* - * Initialize PCI Devices, report devices found. - */ -void pci_init (bd_t *dummy) -{ - pci_dev_init(0); -} diff --git a/board/mousse/ns16550.c b/board/mousse/ns16550.c deleted file mode 100644 index f9e003b..0000000 --- a/board/mousse/ns16550.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * COM1 NS16550 support for the MOUSSE Processor card. - */ -#include -#include "ns16550.h" -#include "mousse.h" - -#define NS16550_FIFO - -#define UART ((void *) 0xffe08080) /* COM1 */ -#define NS16550_CLOCK_SPEED (115200 * 16 * 10) - -/* - * Baud rate conversation table for 16550 - */ -static const -ns16550_baud_rate_table speed_table[] = { - { B50, (unsigned short) (NS16550_CLOCK_SPEED/(16*B50)) }, - { B75, (unsigned short) (NS16550_CLOCK_SPEED/(16*B75)) }, - { B110, (unsigned short) (NS16550_CLOCK_SPEED/(16*B110)) }, - { B150, (unsigned short) (NS16550_CLOCK_SPEED/(16*B150)) }, - { B300, (unsigned short) (NS16550_CLOCK_SPEED/(16*B300)) }, - { B600, (unsigned short) (NS16550_CLOCK_SPEED/(16*B600)) }, - { B1200, (unsigned short) (NS16550_CLOCK_SPEED/(16*B1200)) }, - { B1800, (unsigned short) (NS16550_CLOCK_SPEED/(16*B1800)) }, - { B2000, (unsigned short) (NS16550_CLOCK_SPEED/(16*B2000)) }, - { B2400, (unsigned short) (NS16550_CLOCK_SPEED/(16*B2400)) }, - { B3600, (unsigned short) (NS16550_CLOCK_SPEED/(16*B3600)) }, - { B4800, (unsigned short) (NS16550_CLOCK_SPEED/(16*B4800)) }, - { B7200, (unsigned short) (NS16550_CLOCK_SPEED/(16*B7200)) }, - { B9600, (unsigned short) (NS16550_CLOCK_SPEED/(16*B9600)) }, - { B14400, (unsigned short) (NS16550_CLOCK_SPEED/(16*B14400)) }, - { B19200, (unsigned short) (NS16550_CLOCK_SPEED/(16*B19200)) }, - { B28800, (unsigned short) (NS16550_CLOCK_SPEED/(16*B28800)) }, - { B38400, (unsigned short) (NS16550_CLOCK_SPEED/(16*B38400)) }, - { B56000, (unsigned short) (NS16550_CLOCK_SPEED/(16*B56000)) }, - { B57600, (unsigned short) (NS16550_CLOCK_SPEED/(16*B57600)) }, - { B115200, (unsigned short) (NS16550_CLOCK_SPEED/(16*B115200)) }, - { B128000, (unsigned short) (NS16550_CLOCK_SPEED/(16*B128000)) }, - { 0 ,0 }, -}; - -static void set_speed (unsigned int code) -{ - unsigned char scratch_pad; - volatile ns16550_uart *uart = UART; - - scratch_pad = uart->LCR; - uart->LCR = LCR_DLAB | scratch_pad; - uart->DLL = (unsigned char) (code & 0xff); - uart->DLM = (code >> 8); - uart->LCR = scratch_pad; - - return; -} - -static unsigned short get_speed (void) -{ - volatile ns16550_uart *uart = UART; - unsigned int code; - code = uart->DLL; - return (uart->DLL | (uart->DLM << 8)); -} - -/* - * Given the baud rate, convert the baud rate to a value, that has - * to be loaded into the DLL and DLM register. The caller, can set the - * baud rate once the DLAB bit has been set high, by writing the value - * returned into the DLL and DLM latches. - * - * Returns: - * - a 0, if the baudrate is not one of the known baudrates. - * - a positive number, which can be loaded into the Divisor latch register - * for setting the baudrate. - */ - -static unsigned short -ns16550_baud2code (unsigned int baudrate) -{ - int count = 0; - - for (count = 0; speed_table[count].baudrate > 0; count++) { - if (speed_table[count].baudrate == baudrate) { - return (speed_table[count].value); - } - } - return (0); /* baudrate not found in table */ -} - -static unsigned short -ns16550_code2baud (unsigned int code) -{ - int count = 0; - - for (count = 0; speed_table[count].baudrate > 0; count++) { - if (speed_table[count].value == code) { - return (speed_table[count].baudrate); - } - } - return (0); /* baudrate not found in table */ -} - -/* - * - * This routine will initialize the UART to a known state of speed,stopbits - * etc., - * - * Things to do in this routine : - * ----------------------------- - * - * 2. Reset the TX and RX FIFO's. - * 3. Set default speed. - * 4. Set the data 8 bits / character. - * 5. Set the parity to nothing. - * 6. Set the number of stop bits to 2. - * 7. Set the receive trigger level. - * 8. Enable the Rx and Tx FIFO's. - * 9. Raise the DTR. - * 10. Set the interrupt for Rx, LSR and MSR. Transmit holding register empty - * is generated as and when necessary. - * - * NOTE : The interrupt hadnler must be set in the calling routine for the - * UART ports. - * - */ -void -ns16550_init (int baud) -{ - volatile ns16550_uart *uart = UART; - unsigned char scratch_pad; - - /* Disable all interrupts before setting the interrupt handler. */ - scratch_pad = 0; - uart->IER = scratch_pad; - - /* Clear the FIFO's, set speed to 9600 baud */ - uart->FCR = (FCR_RX_CLR | FCR_TX_CLR); - ns16550_setspeed(baud); - /* - * Set the data bits, stop bits and parity. By Default 8 data bits/char, - * 2 stop bits and no parity. - */ - uart->LCR = ((LCR_8BITS | LCR_2_SB) & ~LCR_PARITY_ENABLE); - -#ifdef NS16550_FIFO - /* - * For now set the trigger level to 14. This we might have to change - * after some initial testing. - */ - uart->FCR = (TRIGGER_ON_14 | FCR_ENABLE | FCR_DMA_MODE); -#endif - - /* - * Raise the DTR & DTR in case of AUX/Console port. - */ - uart->MCR = (MCR_DTR | MCR_RTS); - scratch_pad = uart->IIR; - scratch_pad = uart->MSR; - - scratch_pad = IER_ENABLE_RX_DATA | - IER_ENABLE_RX_LSR | - IER_ENABLE_MODEM_STAT; - uart->IER = scratch_pad; -} - -/* - * Set the speed on the UART. Return the new speed, or zero if one - * cannot be set. If zero is passed in, do not change the speed, - * just return the current speed. - */ -int -ns16550_setspeed (int speed) -{ - int code; - - if (!speed) { - return (ns16550_code2baud (get_speed ())); - } - - /* - * Translate speeds to codes. Change baud rates if codes are good - * and are different from what we were already running with: - */ - code = ns16550_baud2code(speed); - if (!code) { /* Unknown speed being set */ - return(0); - } - - set_speed (code); - - return (speed); -} - -/* - * Read a byte from the console. - */ -int -ns16550_getc (void) -{ - unsigned char ch; - char lsr_stat; - volatile ns16550_uart *uart = UART; - - lsr_stat = uart->LSR; - while ((lsr_stat & LSR_DATAREADY) == 0) { - lsr_stat = uart->LSR; /* Loop for a character */ - } - - ch = uart->RxBuf; /* Get the character */ - - return(ch); -} - - -int -ns16550_tstc(void) -{ - volatile ns16550_uart *uart = UART; - return ((uart->LSR & LSR_DATAREADY) != 0); -} - -/* - * - * Write a byte to the console. - * - */ -unsigned char -ns16550_putc (unsigned char ch) -{ - volatile ns16550_uart *uart = UART; - unsigned char lsr_stat; - - lsr_stat = uart->LSR; - while (((lsr_stat & LSR_THRE) == 0) || ((lsr_stat & LSR_TEMT) == 0)) { - lsr_stat = uart->LSR; /* Wait for transmitter ready */ - } - - uart->TxBuf = ch; /* Store the character */ - return (ch); -} - -/* - * Return TRUE if a break has been recieved, else return FALSE. - * - */ -int -ns16550_check_char (void) -{ - volatile ns16550_uart *uart = UART; - - if (uart->LSR & LSR_DATAREADY) { - return 1; - } - - return 0; -} - -/* - * Return TRUE if a break has been recieved, else return FALSE. - * - */ -int -ns16550_check_break (void) -{ - volatile ns16550_uart *uart = UART; - static int break_recvd = 0; - volatile int i; - - if (uart->LSR & LSR_BREAK_INTR) { - while (uart->LSR & LSR_DATAREADY) { - i = uart->RxBuf; - } - break_recvd = 1; - return 1; - } - - if (break_recvd) { - while (uart->LSR & LSR_DATAREADY) { - i = uart->RxBuf; - } - break_recvd = 0; - } - - return 0; -} diff --git a/board/mousse/ns16550.h b/board/mousse/ns16550.h deleted file mode 100644 index 0d98faf..0000000 --- a/board/mousse/ns16550.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __NS16552_H -#define __NS16552_H - -/* - * NS16552D Serial Port - */ - -typedef struct ns16550_uart_ { - -/* - * The register is selected by - * 1. If the DLAB bit is set to 1, then the Divisor_Latch_LSB will be active. - * 2. If the DLAB bit is reset, then - * a. A read is performed from the Rx_Buffer_Register. - * b. A write to is performed on the Tx_Holding_Register. - */ - union - { - volatile unsigned char Rx_Buffer; /* Rx buffer ready reg RD only */ - volatile unsigned char Tx_Holding; /* Tx holding register WR only */ - volatile unsigned char DLL; /* Divisor latch LS Byte */ - } RBS_THR_DLAB1; -#define RxBuf RBS_THR_DLAB1.Rx_Buffer -#define TxBuf RBS_THR_DLAB1.Tx_Holding -#define DLL RBS_THR_DLAB1.DLL -/* - * The register is selected by - * - * If the DLAB bit is set to 1, then the Divisor_Latch_LSB will be active, else - * Interrupt enable register is active. - */ - union - { - volatile unsigned char DLM; /* Divisor latch MS Byte */ - volatile unsigned char IER; /* Intr. enable register */ - } IER_DLAB2; -#define DLM IER_DLAB2.DLM -#define IER IER_DLAB2.IER - -/* - * If the DLAB bit is 1, then Alternate function register is selected. - * If the DLAB bit is 0, then - * 1. A read is always performed from the Interrupt Indentification register. - * 2. A write is always performed on the FIFO control register. - */ - union{ - volatile unsigned char IIR; /* Intr. identification RD */ - volatile unsigned char FCR; /* FIFO control WR only */ - volatile unsigned char AFR; /* When DLAB is 1 */ - } IIR_FCR_AFR; -#define IIR IIR_FCR_AFR.IIR -#define FCR IIR_FCR_AFR.FCR -#define AFR IIR_FCR_AFR.AFR - volatile unsigned char LCR; /* Line Control register */ - volatile unsigned char MCR; /* Modem Control register */ - volatile unsigned char LSR; /* Line Status register */ - volatile unsigned char MSR; /* Modem Status register */ - volatile unsigned char SR; /* Scratch pad register */ -} ns16550_uart; - - - -/* NSC 16550 Interrupt Enable register definitions */ -#define IER_ENABLE_RX_DATA 0x01 /* Enable Recevied Data available intr*/ -#define IER_ENABLE_THRE 0x02 /* Enable Tx holding reg empty intr */ -#define IER_ENABLE_RX_LSR 0x04 /* Enable receiver Line status intr */ -#define IER_ENABLE_MODEM_STAT 0x08 /* Enable receiver Modem status intr*/ - -/* NSC 16550 Interrupt Identification register bit settings */ -#define IIR_MSTAT 0x00 /* Modem changed status indication */ -#define IIR_NOPENDING_INTR 0x01 /* Interrupt not pending, indication */ -#define IIR_THRE 0x02 /* Tx holding reg empty indication */ -#define IIR_CHAR_TIMEOUT 0x0c /* Character timeout indication */ -#define IIR_RX_DATA_AVAIL 0x04 /* Received data available indication */ -#define IIR_RLS 0x06 /* Receiver line status (either OE, PE, - FE or BI received) */ - -/* NSC 16550 FIFO Control register bit settings */ -#define FCR_ENABLE 0x01 /* Rx and Tx FIFO's enabler */ -#define FCR_RX_CLR 0x02 /* Clear the Rx FIFO and set offset to 0 */ -#define FCR_TX_CLR 0x04 /* Clear the Rx FIFO and set offset to 0 */ -#define FCR_DMA_MODE 0x08 /* Will enable DMA transfers for Rx and Tx */ - -/* - * Receiver FIFO trigger level, is the number characters needed to be in the - * FIFO, before an interrupt is generated. Bits ( 7 & 8 ) of the above - * register. - */ -#define TRIGGER_ON_1 0x00 /* Trigger after receiving 1 byte */ -#define TRIGGER_ON_4 0x01 /* Trigger after receiving 4 byte */ -#define TRIGGER_ON_8 0x02 /* Trigger after receiving 8 byte */ -#define TRIGGER_ON_14 0x03 /* Trigger after receiving 14 byte */ -#define FIFO_COUNT 16 /* 16 byte deep FIFO */ - -/* NSC 16550 Line control register bit settings */ -/* - * Bits - * 0 1 - Character length - * 2 - Stops bit length (used along with the bits 0 & 1) - * 3 - Parity enable bit - * 4 - Even parity select bit (only active when parity is enabled. - * = 0, Odd parity - * = 1, Even Parity - * 5 - Sticky bit parity. - * 6 - Break control bit, causes break condition to be transmitted - * 7 - Divisor latch access bit for setting the baud rate divisor - */ -#define LCR_5BITS 0x00 /* Character length is 5 bits */ -#define LCR_6BITS 0x01 /* Character length is 6 bits */ -#define LCR_7BITS 0x02 /* Character length is 7 bits */ -#define LCR_8BITS 0x03 /* Character length is 8 bits */ -#define LCR_1_SB 0x00 /* Bit 2 should be 0, for 1 stop bit */ -#define LCR_15_SB 0x04 /* Bit 2 should be 1 and LCR_5BITS - must be selected for 1.5 bits */ -#define LCR_2_SB 0x04 /* When character length is 6,7 or 8 */ -#define LCR_PARITY_ENABLE 0x08 /* Enable parity on Rx and Tx */ -#define LCR_EVEN_PARITY 0x10 /* When parity enabled */ -#define LCR_STICKY_PARITY 0x20 /* Sticky parity enable */ -#define LCR_BREAK_CTRL 0x40 /* Break control bit */ -#define LCR_DLAB 0x80 /* Divisor latch access bit */ - -/* NSC 16550 Modem Control register bit definitions */ -#define MCR_DTR 0x01 /* Data terminal ready */ -#define MCR_RTS 0x02 /* Request to send */ -#define MCR_OUT1 0x04 /* Out1 */ -#define MCR_OUT2 0x08 /* Out1 */ -#define MCR_LOOP 0x10 /* Set loop mode */ - -/* NSC 16550 Line status register bit definitions */ -#define LSR_DATAREADY 0x01 /* Data ready */ -#define LSR_OVERRUN_ERR 0x02 /* Overrun Error */ -#define LSR_PARITY_ERR 0x04 /* Parity Error */ -#define LSR_FRAME_ERR 0x08 /* Framing Error */ -#define LSR_BREAK_INTR 0x10 /* Break Interrupt */ -#define LSR_THRE 0x20 /* Transmit holding register empty */ -#define LSR_TEMT 0x40 /* Transmiter empty */ -#define LSR_RX_FIFO_ERR 0x80 /* Error on Receiver FIFO */ - -/* NSC 16550 Modem status register bit definitions */ -#define MSR_DELTA_CTS 0x01 /* Delta CTS */ -#define MSR_DELTA_DSR 0x02 /* Delta DSR */ -#define MSR_TERI 0x04 /* Trailing Edge ring indicator */ -#define MSR_DELTA_DCD 0x08 /* Delta DCD */ -#define MSR_CTS 0x10 /* CTS */ -#define MSR_DSR 0x20 /* DSR */ -#define MSR_RI 0x40 /* RI */ -#define MSR_DCD 0x80 /* DCD */ - -#define HIGH_WATER_MARK 1664 /* High water mark, at which the h/w flow control - will take affect */ - -/* Baud Rate settings */ -/* - * This particular chip can set the baud rate by writing to the Divisor latch. - * This divisor latch is a 16 bit latch and can be written only when DLAB bit - * is set. The baud rate depends on the input clock frequency. - * - * To calculate the number to be loaded into the latch use the following - * formula - * - * Divisor # = (Clock Freq) / (16 * Speed in bauds). - * Eg. On a 18.432 MHz to get a baud rate of 115.2kbps ... - * Divisor # = (18432000)/(115200*16) - * Divisor # = 10 - * - * NOTE: If the clock frequency is changed new values for these variables have - * to be calculated. - */ - -#define B50 50 -#define B75 75 -#define B110 110 -#define B150 150 -#define B300 300 -#define B600 600 -#define B1200 1200 -#define B1800 1800 -#define B2000 2000 -#define B2400 2400 -#define B3600 3600 -#define B4800 4800 -#define B7200 7200 -#define B9600 9600 -#define B14400 14400 -#define B19200 19200 -#define B28800 28800 -#define B38400 38400 -#define B56000 56000 -#define B57600 57600 -#define B115200 115200 -#define B128000 128000 -/* - * Possible only with a 24 MHz crystal clock input. - */ -#define B250k 250000 -#define B300k 300000 -#define B375k 375000 -#define B500k 500000 -#define B750k 750000 -#define B1500k 1500000 - -typedef struct ns16550_baud_rate_table_ { - int baudrate; - unsigned short value; -} ns16550_baud_rate_table; - - -int ns16550_check_break (void); -int ns16550_check_char (void); -unsigned char ns16550_putc (unsigned char ch); -int ns16550_getc (void); -int ns16550_setspeed (int speed); -void ns16550_init (int baud); -int ns16550_tstc(void); - - -#endif /* __NS16552_H */ diff --git a/board/mousse/pci.c b/board/mousse/pci.c index 4c13809..c1cddf6 100644 --- a/board/mousse/pci.c +++ b/board/mousse/pci.c @@ -29,516 +29,10 @@ * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge */ #include -#include "mpc824x.h" -#include "pci.h" -#include "mousse.h" - -int numPciBus = 1; /* One bus: MPC107 Internal bridge */ - -/* - * - * pci_dev_find - find the nth device with the given device & vendor ID - * - */ -int pci_dev_find(int vendorId, /* vendor ID */ - int deviceId, /* device ID */ - int index, /* desired instance of device */ - int* pBusNo, /* bus number */ - int* pDeviceNo, /* device number */ - int* pFuncNo) /* function number */ -{ - int status = ERROR; - int cont = TRUE; - int busNo; - int deviceNo; - int funcNo; - uint32 device; - uint32 vendor; - char header; - - for (busNo = 0; cont == TRUE && busNo <= numPciBus; busNo++) - for (deviceNo = 0; - ((cont == TRUE) && (deviceNo < PCI_MAX_DEV)); - ++deviceNo) - for (funcNo = 0; cont == TRUE && funcNo < PCI_MAX_FUNC; funcNo++){ - /* avoid a special bus cycle */ - - if ((deviceNo == 0x1f) && (funcNo == 0x07)) - continue; - - pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, - &vendor); - - /* - * If nonexistent device, skip to next, only look at - * vendor ID field for existence check - */ - if (((vendor & 0x0000ffff) == 0x0000FFFF) && (funcNo == 0)) - break; - device = vendor >> 16; - device &= 0x0000FFFF; - vendor &= 0x0000FFFF; - if ((vendor == (uint32)vendorId) && - (device == (uint32)deviceId) && - (index-- == 0)){ - *pBusNo = busNo; - *pDeviceNo = deviceNo; - *pFuncNo = funcNo; - status = OK; - cont = FALSE; /* terminate all loops */ - continue; - } - - /* goto next if current device is single function */ - - pci_config_inb (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, - &header); - if ((header & PCI_HEADER_MULTI_FUNC) != - PCI_HEADER_MULTI_FUNC && funcNo == 0) - break; - } - - return status; -} - -/* - * - * pci_class_find - find the nth occurence of a device by PCI class code. - * - * RETURNS: - * OK, or ERROR if the class didn't match. - */ - -int pci_class_find(int classCode, /* 24-bit class code */ - int index, /* desired instance of device */ - int * pBusNo, /* bus number */ - int * pDeviceNo, /* device number */ - int * pFuncNo) /* function number */ -{ - int status = ERROR; - int cont = TRUE; - int busNo; - int deviceNo; - int funcNo; - int classCodeReg; - int vendor; - char header; - - - for (busNo = 0; cont == TRUE && busNo <= numPciBus; busNo++) - for (deviceNo = 0; - ((cont == TRUE) && (deviceNo < PCI_MAX_DEV)); - ++deviceNo) - for (funcNo = 0; cont == TRUE && funcNo < PCI_MAX_FUNC; funcNo++){ - - /* avoid a special bus cycle */ - if ((deviceNo == 0x1f) && (funcNo == 0x07)) - continue; - - pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, - &vendor); - - /* - * If nonexistent device, skip to next, only look at - * vendor ID field for existence check - */ - if (((vendor & 0x0000ffff) == 0x0000FFFF) && (funcNo == 0)) - break; - - pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_REVISION, - &classCodeReg); - - if ((((classCodeReg >> 8) & 0x00ffffff) == classCode) && - (index-- == 0)) - { - *pBusNo = busNo; - *pDeviceNo = deviceNo; - *pFuncNo = funcNo; - status = OK; - cont = FALSE; /* terminate all loops */ - continue; - } - - /* goto next if current device is single function */ - - pci_config_inb (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, - &header); - if ((header & PCI_HEADER_MULTI_FUNC) != - PCI_HEADER_MULTI_FUNC && funcNo == 0) - break; - } - return status; -} - - -/* - * - * pci_dev_config - configure a device on a PCI bus - * - * This routine configures a device that is on a Peripheral Component - * Interconnect (PCI) bus by writing to the configuration header of the - * selected device. - * - * It first disables the device by clearing the command register in the - * configuration header. It then sets the I/O and/or memory space base - * address registers, the latency timer value and the cache line size. - * Finally, it re-enables the device by loading the command register with - * the specified command. - * - * NOTE: This routine is designed for Type 0 PCI Configuration Headers ONLY. - * It is NOT usable for configuring, for example, a PCI-to-PCI bridge. - * - * RETURNS: OK always. - */ -int pci_dev_config(int pciBusNo, /* PCI bus number */ - int pciDevNo, /* PCI device number */ - int pciFuncNo, /* PCI function number */ - uint32 devIoBaseAdrs, /* device IO base address */ - uint32 devMemBaseAdrs, /* device memory base address */ - uint32 command) /* command to issue */ -{ - int ix; - uint32 tmp32; - - /* - * Disable device by clearing its command register field in its - * configuration header. Write 0 clears command and preserves status. - */ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0x0); - - for (ix = PCI_CFG_BASE_ADDRESS_0; ix <= PCI_CFG_BASE_ADDRESS_5; ix+=4){ - - /* Write all f's and read back value */ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, 0xffffffff); - pci_config_inl (pciBusNo, pciDevNo, pciFuncNo, ix, &tmp32); - - if (tmp32 == 0){ - /* No bar */ - break; - } - - /* I/O space requested */ - if (tmp32 & 0x1){ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, - devIoBaseAdrs | 0x1); - } else{ - /* Memory space required, set specified base address */ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, - devMemBaseAdrs & ~0x1); - } - } - - /* Configure Cache Line Size Register */ - pci_config_outb (pciBusNo, pciDevNo, pciFuncNo, - PCI_CFG_CACHE_LINE_SIZE, - PCI_CACHE_LINE_SIZE); - - /* Configure Latency Timer */ - pci_config_outb (pciBusNo, pciDevNo, pciFuncNo, - PCI_CFG_LATENCY_TIMER, - PCI_LATENCY_TIMER); - - /* - * Enable the device's capabilities as specified, do not - * reset any status bits in doing so. - */ - pci_config_modl (pciBusNo, pciDevNo, pciFuncNo, - PCI_CFG_COMMAND, - (PCI_CMD_MASK | command), command); - - return OK; -} - - -/* - * - * pci_config_bdf_pack - pack parameters for the Configuration Address Register - * - * This routine packs three parameters into one integer for accessing the - * Configuration Address Register - * - */ - -int pci_config_bdf_pack(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo) /* function number */ -{ - return (((busNo << 16) & 0x00ff0000) | - ((deviceNo << 11) & 0x0000f800) | - ((funcNo << 8) & 0x00000700)); -} - -/* - * pci_config_inb - read one byte from the PCI configuration space - * - * This routine reads one byte from the PCI configuration space - * - */ -int pci_config_inb(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint8 * pData) /* data read from the offset */ -{ - uint8 retval = 0; - int retStat = ERROR; - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - retval = mpc824x_mpc107_read8 (CHRP_REG_DATA + (offset & 0x3)); - retStat = OK; - - *pData = retval; - - return retStat; -} - -/* - * - * pci_config_inw - read one word from the PCI configuration space - * - * This routine reads one word from the PCI configuration space - * - */ -int pci_config_inw(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint16 * pData) /* data read from the offset */ -{ - int retStat = ERROR; - uint16 retval = 0; - - if (((offset & (int)0x1) > 0) ) { - return (retStat); - } - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - retval = mpc824x_mpc107_read16 (CHRP_REG_DATA + (offset & 0x2)); - retStat = OK; - *pData = retval; - - return retStat; -} - -/* - * - * pci_config_inl - read one longword from the PCI configuration space - * - * This routine reads one longword from the PCI configuration space - * - */ -int pci_config_inl(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint32 * pData) /* data read from the offset */ -{ - int retStat = ERROR; - uint32 retval = 0; - - if (((offset & (int)0x3) > 0) ) { - return (retStat); - } - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - retval = mpc824x_mpc107_read32 (CHRP_REG_DATA); - asm volatile ("eieio"); - retStat = OK; - *pData = retval; - return retStat; -} - -/* - * pci_config_outb - write one byte to the PCI configuration space - * - * This routine writes one byte to the PCI configuration space. - * - */ -int pci_config_outb(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint8 data) /* data written to the offset */ -{ - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - mpc824x_mpc107_write8 ((CHRP_REG_DATA + (offset & 0x3)), data); - return OK; -} - -/* - * pci_config_outw - write one 16-bit word to the PCI configuration space - * - * This routine writes one 16-bit word to the PCI configuration space. - * - * RETURNS: OK, or ERROR if this library is not initialized - */ -int pci_config_outw(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint16 data) /* data written to the offset */ -{ - if (((offset & (int)0x1) > 0) ){ - return (ERROR); - } - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - mpc824x_mpc107_write16 ((CHRP_REG_DATA + (offset & 0x2)), data); - return OK; -} - - -/* - * - * pci_config_outl - write one longword to the PCI configuration space - * - * This routine writes one longword to the PCI configuration space. - * - */ -int pci_config_outl(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint32 data) /* data written to the offset */ -{ - if (((offset & (int)0x3) > 0) ){ - return (ERROR); - } - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - mpc824x_mpc107_write32 (CHRP_REG_DATA, data); - asm volatile ("eieio"); - return OK; -} - - -/* - * - * pci_config_modl - Perform a masked longword register update - * - * This function writes a field into a PCI configuration header without - * altering any bits not present in the field. It does this by first - * doing a PCI configuration read (into a temporary location) of the PCI - * configuration header word which contains the field to be altered. - * It then alters the bits in the temporary location to match the desired - * value of the field. It then writes back the temporary location with - * a configuration write. All configuration accesses are long and the - * field to alter is specified by the "1" bits in the 'bitMask' parameter. - * - */ - -int pci_config_modl(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint32 bitMask, /* Mask of bits to alter */ - uint32 data) /* data written to the offset */ - -{ - uint32 temp; - int stat; - - if (((offset & (int)0x3) > 0) ){ - return (ERROR); - } - - stat = pci_config_inl (busNo, deviceNo, funcNo, offset, &temp); - if (stat == OK){ - temp = (temp & ~bitMask) | (data & bitMask); - stat = pci_config_outl (busNo, deviceNo, funcNo, offset, temp); - } - return stat; -} - - -/* - * - * pci_config_modw - Perform a masked short register update - * - */ -int pci_config_modw(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint16 bitMask, /* Mask of bits to alter */ - uint16 data) /* data written to the offset */ -{ - uint16 temp; - int stat; - if (((offset & (int)0x1) > 0) ){ - return (ERROR); - } - stat = pci_config_inw (busNo, deviceNo, funcNo, offset, &temp); - if (stat == OK){ - temp = (temp & ~bitMask) | (data & bitMask); - stat = pci_config_outw (busNo, deviceNo, funcNo, offset, temp); - } - return stat; -} - - - -/* - * pci_config_modb - Perform a masked byte register update - * - */ -int pci_config_modb(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint8 bitMask, /* Mask of bits to alter */ - uint8 data) /* data written to the offset */ -{ - uint8 temp; - int stat; - stat = pci_config_inb (busNo, deviceNo, funcNo, offset, &temp); - if (stat == OK){ - temp = (temp & ~bitMask) | (data & bitMask); - stat = pci_config_outb (busNo, deviceNo, funcNo, offset, temp); - } - return stat; -} - -/* - * pci_special_cycle - generate a special cycle with a message - */ -int -pci_special_cycle(int busNo, /* bus number */ - uint32 message) /* data driven onto AD[31:0] */ -{ - int deviceNo = 0x0000001f; - int funcNo = 0x00000007; - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - 0x80000000); - mpc824x_mpc107_write32 (CHRP_REG_DATA, message); - return OK; -} - - -/* - * Find the extent of a PCI decode.. - */ -unsigned int -pci_size_bar(unsigned int base, unsigned long mask) -{ - uint32 size = mask & base; /* Find the significant bits */ - size = size & ~(size-1); /* Get the lowest of them to find the decode size */ - return size-1; /* extent = size - 1 */ -} +#include +#include +#include "mousse.h" /* * Promise ATA/66 support. @@ -621,8 +115,7 @@ pdc202xx_decode_registers (unsigned char registers, unsigned char value) * Promise ATA/66 Support: configure Promise ATA66 card in specified mode. */ int -pdc202xx_tune_chipset (int bus, int dev, int func, - int drive, unsigned char speed) +pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed) { unsigned short drive_conf; int err = 0; @@ -637,28 +130,28 @@ pdc202xx_tune_chipset (int bus, int dev, int func, default: return -1; } - pci_config_inw(bus,dev,func, drive_pci, &drive_conf); - pci_config_inb(bus,dev,func, (drive_pci), &AP); - pci_config_inb(bus,dev,func, (drive_pci)|0x01, &BP); - pci_config_inb(bus,dev,func, (drive_pci)|0x02, &CP); - pci_config_inb(bus,dev,func, (drive_pci)|0x03, &DP); + pci_read_config_word(dev, drive_pci, &drive_conf); + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci)|0x02, &CP); + pci_read_config_byte(dev, (drive_pci)|0x03, &DP); if ((AP & 0x0F) || (BP & 0x07)) { /* clear PIO modes of lower 8421 bits of A Register */ - pci_config_outb(bus,dev,func, (drive_pci), AP & ~0x0F); - pci_config_inb(bus,dev,func, (drive_pci), &AP); + pci_write_config_byte(dev, (drive_pci), AP & ~0x0F); + pci_read_config_byte(dev, (drive_pci), &AP); /* clear PIO modes of lower 421 bits of B Register */ - pci_config_outb(bus,dev,func, (drive_pci)|0x01, BP & ~0x07); - pci_config_inb(bus,dev,func, (drive_pci)|0x01, &BP); + pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_config_inb(bus,dev,func, (drive_pci), &AP); - pci_config_inb(bus,dev,func, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); } - pci_config_inb(bus,dev,func, (drive_pci), &AP); - pci_config_inb(bus,dev,func, (drive_pci)|0x01, &BP); - pci_config_inb(bus,dev,func, (drive_pci)|0x02, &CP); + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci)|0x02, &CP); switch(speed) { case XFER_PIO_4: TA = 0x01; TB = 0x04; break; @@ -669,13 +162,13 @@ pdc202xx_tune_chipset (int bus, int dev, int func, default: TA = 0x09; TB = 0x13; break; } - pci_config_outb(bus,dev,func, (drive_pci), AP|TA); - pci_config_outb(bus,dev,func, (drive_pci)|0x01, BP|TB); + pci_write_config_byte(dev, (drive_pci), AP|TA); + pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB); - pci_config_inb(bus,dev,func, (drive_pci), &AP); - pci_config_inb(bus,dev,func, (drive_pci)|0x01, &BP); - pci_config_inb(bus,dev,func, (drive_pci)|0x02, &CP); - pci_config_inb(bus,dev,func, (drive_pci)|0x03, &DP); + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci)|0x02, &CP); + pci_read_config_byte(dev, (drive_pci)|0x03, &DP); #ifdef PDC202XX_DEBUG @@ -686,166 +179,105 @@ pdc202xx_tune_chipset (int bus, int dev, int func, #endif return err; } - - /* * Show/Init PCI devices on the specified bus number. */ -int pci_dev_init(int busNo) + +void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - int deviceNo, a; - uint32 cmd, bar; - int devices; - uint16 vendorId; - uint16 deviceId; - uint32 mbar0; - uint32 mbar1; - uint32 revId; - uint32 iline,ipin; - - union { - int classCode; - char array[4]; - } u; - - printf("PCI: scanning bus%d ...\n", busNo); - printf(" bus dev fn venID devID class" - " rev MBAR0 MBAR1 IPIN ILINE\n"); - - devices = 0x1f; - for (deviceNo=0; deviceNo < devices; deviceNo++) { - - /* Get device and vendor ID */ - pci_config_inw (busNo, deviceNo, 0, PCI_CFG_VENDOR_ID, &vendorId); - pci_config_inw (busNo, deviceNo, 0, PCI_CFG_DEVICE_ID, &deviceId); - - /* MPC107 Bridge */ - if( deviceNo == 0x0){ - /* Don't do anything */ - } - - /* Make sure IRQ's on PCI devices get configured correctly */ - if( deviceNo == 0x0d){ - /* Onboard */ - pci_dev_config(busNo, deviceNo, 0, - PCI_ENET_IOADDR, - PCI_ENET_MEMADDR, - PCI_CMD_MEM_ENABLE | - PCI_CMD_MEM_ENABLE | - PCI_CMD_MASTER_ENABLE); - /* DEC get's IRQ=1 */ - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, 0x00000101); - } /* PCI Slot */ - else if (deviceNo == 0x0e){ - - if(vendorId == PCI_VENDOR_ID_PROMISE|| - vendorId == 0x1095){ - /* PDC 202xx card is handled differently, it is a bootable - * device and needs all 5 MBAR's configured - */ - for(bar = 0; bar < 5; bar++){ - pci_config_inl(busNo, deviceNo, 0, - PCI_CFG_BASE_ADDRESS_0+bar*4, - &mbar0); - pci_config_outl(busNo, deviceNo, 0, - PCI_CFG_BASE_ADDRESS_0+bar*4, - ~0); - pci_config_inl(busNo, deviceNo, 0, - PCI_CFG_BASE_ADDRESS_0+bar*4, - &mbar0); - /* printf(" ATA_bar[%d] = %dbytes\n", - bar,pci_size(mbar0,PCI_BASE_ADDRESS_MEM_MASK)); */ + unsigned int line; + + switch(PCI_DEV(dev)) { + case 0x0d: + line = 0x00000101; + break; + + case 0x0e: + default: + line = 0x00000303; + break; } - /* Program all BAR's */ - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_0, - PROMISE_MBAR0); - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_1, - PROMISE_MBAR1); - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_2, - PROMISE_MBAR2); - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_3, - PROMISE_MBAR3); - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_4, - PROMISE_MBAR4); - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_5, - PROMISE_MBAR5); - for(bar = 0; bar < 5; bar++){ - - pci_config_inl(busNo, deviceNo, 0, - PCI_CFG_BASE_ADDRESS_0+bar*4, - &mbar0); - /* printf(" ATA_bar[%d]@0x%x\n", bar,mbar0);*/ + pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line); +} + +void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *_) +{ + unsigned short vendorId; + unsigned int mbar0, cmd; + int bar, a; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId); + + if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){ + /* PDC 202xx card is handled differently, it is a bootable + * device and needs all 5 MBAR's configured + */ + for(bar = 0; bar < 5; bar++){ + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); +#ifdef DEBUG + printf(" ATA_bar[%d] = %dbytes\n", bar, + ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1); +#endif + } + + /* Program all BAR's */ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5); + + for(bar = 0; bar < 5; bar++){ + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); +#ifdef DEBUG + printf(" ATA_bar[%d]@0x%x\n", bar, mbar0); +#endif + } + + /* Enable ROM Expansion base */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1); + + /* Io enable, Memory enable, master enable */ + pci_read_config_dword(dev, PCI_COMMAND, &cmd); + cmd &= ~0xffff0000; + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config_dword(dev, PCI_COMMAND, cmd); + + /* Breath some life into the controller */ + for( a = 0; a < 4; a++) + pdc202xx_tune_chipset(dev, a, XFER_PIO_0); } - /* Enable ROM Expansion base */ - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_ROM_BASE, - PROMISE_MBAR5|1); - - /* IRQ 3 */ - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, - 0x00000303); - - /* Io enable, Memory enable, master enable */ - cmd = PCI_CMD_MASTER_ENABLE | PCI_CMD_MEM_ENABLE|PCI_CMD_IO_ENABLE; - pci_config_modl (busNo, deviceNo, 0, PCI_CFG_COMMAND, - (PCI_CMD_MASK | cmd),cmd); - - /* Breath some life into the controller */ - for( a = 0; a < 4; a++) - pdc202xx_tune_chipset(busNo,deviceNo, 0, a, XFER_PIO_0); - - } else { - /* Other PCI Devices */ - - pci_dev_config(busNo, deviceNo, 0, - PCI_SLOT_IOADDR, - PCI_SLOT_MEMADDR, - PCI_CMD_MEM_ENABLE | - PCI_CMD_MEM_ENABLE | - PCI_CMD_MASTER_ENABLE); - /* PCI slot get's IRQ=3 */ - pci_config_outl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, 0x00000303); - pci_config_outl(busNo, deviceNo, 0, PCI_LATENCY_TIMER, 127); - } - - - } - - pci_config_inb (busNo, deviceNo, 0, PCI_CFG_PROGRAMMING_IF, - &u.array[3]); - pci_config_inb (busNo, deviceNo, 0, PCI_CFG_SUBCLASS, &u.array[2]); - pci_config_inb (busNo, deviceNo, 0, PCI_CFG_CLASS, &u.array[1]); - u.array[0] = 0; - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_0, &mbar0); - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_1, &mbar1); - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_REVISION, &revId); - revId &= 0x000000ff; - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &iline); - iline &= 0x000000ff; - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &ipin); - ipin &= 0x0000ff00; - ipin >>= 8; - - - /* There are two ways to find out an empty device. - * 1. check Master Abort bit after the access. - * 2. check whether the read value is 0xffff. - * Since I didn't see the Master Abort bit of the host/PCI bridge - * changing, I use the second method. - */ - if (vendorId != 0xffff) - - printf(" %02x %02x %02x %04x %04x " - "%06x %02x %08x %08x %02x %02x\n", - busNo, deviceNo, 0, - vendorId, deviceId, u.classCode, revId, - mbar0, mbar1, ipin, iline); - } - return OK; } +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00, + pci_mousse_setup_pdc202xx }, +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00, + pci_cfgfunc_config_device, {PCI_ENET_IOADDR, + PCI_ENET_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_SLOT_IOADDR, + PCI_SLOT_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, +#endif + { } +}; + +struct pci_controller hose = { + config_table: pci_sandpoint_config_table, + fixup_irq: pci_mousse_fixup_irq, +}; +void pci_init(bd_t *bd) +{ + pci_mpc824x_init(bd, &hose); +} diff --git a/board/mousse/pci.h b/board/mousse/pci.h deleted file mode 100644 index f23fd9d..0000000 --- a/board/mousse/pci.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __MPC824X_PCI -#define __MPC824X_PCI - -/* - * PCI Configuration space Library and constants for MPC824x based - * systems. - */ - -typedef unsigned char uint8; -typedef unsigned int uint32; -typedef unsigned short uint16; -typedef int INT32; -#define LOCAL static -#define IMPORT extern - -#ifndef NULL -#define NULL 0 -#endif - -#define OK 1 -#define NONE 0 -#define ERROR -1 -#define TRUE 1 -#define FALSE (!TRUE) - - -#define PCI_MAX_BUS 255 -#define PCI_MAX_DEV 32 -#define PCI_MAX_FUNC 8 - - -/* PCI Configuration I/O Addresses */ -#define PCI_CONFIG_ADDR 0x0cf8 /* write 32 bits to set address */ -#define PCI_CONFIG_DATA 0x0cfc /* 8, 16, or 32 bit accesses */ -#define PCI_CONFIG_CSE 0x0cf8 /* CSE register */ -#define PCI_CONFIG_FORWARD 0x0cfa /* forward register */ -#define PCI_CONFIG_BASE 0xc000 /* base register */ - -/* PCI command bits */ -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ - -/* PCI base address mask bits */ - -#define PCI_MEMBASE_MASK ~0xf /* mask for memory base address */ -#define PCI_IOBASE_MASK ~0x3 /* mask for IO base address */ -#define PCI_BASE_IO 0x1 /* IO space indicator */ -#define PCI_BASE_BELOW_1M 0x2 /* memory locate below 1MB */ -#define PCI_BASE_IN_64BITS 0x4 /* memory locate anywhere in 64 bits */ -#define PCI_BASE_PREFETCH 0x8 /* memory prefetchable */ - -/* Base Address Register Memory/IO Attribute bits */ - -#define PCI_BAR_SPACE_MASK (0x01) -#define PCI_BAR_SPACE_IO (0x01) -#define PCI_BAR_SPACE_MEM (0x00) - -#define PCI_BAR_MEM_TYPE_MASK (0x06) -#define PCI_BAR_MEM_ADDR32 (0x00) -#define PCI_BAR_MEM_BELOW_1MB (0x02) -#define PCI_BAR_MEM_ADDR64 (0x04) -#define PCI_BAR_MEM_RESERVED (0x06) - -#define PCI_BAR_MEM_PREF_MASK (0x08) -#define PCI_BAR_MEM_PREFETCH (0x08) -#define PCI_BAR_MEM_NON_PREF (0x00) - -#define PCI_BAR_ALL_MASK (PCI_BAR_SPACE_MASK | \ - PCI_BAR_MEM_TYPE_MASK | \ - PCI_BAR_MEM_PREF_MASK) - -/* PCI header type bits */ - -#define PCI_HEADER_TYPE_MASK 0x7f /* mask for header type */ -#define PCI_HEADER_PCI_PCI 0x01 /* PCI to PCI bridge */ -#define PCI_HEADER_TYPE0 0x00 /* normal device header */ -#define PCI_HEADER_MULTI_FUNC 0x80 /* multi function device */ - -/* PCI configuration device and driver */ - -#define SNOOZE_MODE 0x40 /* snooze mode */ -#define SLEEP_MODE_DIS 0x00 /* sleep mode disable */ - -/* Standard device configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDER_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - - -/* PCI-to-PCI bridge configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_PRIMARY_BUS 0x18 -#define PCI_CFG_SECONDARY_BUS 0x19 -#define PCI_CFG_SUBORDINATE_BUS 0x1a -#define PCI_CFG_SEC_LATENCY 0x1b -#define PCI_CFG_IO_BASE 0x1c -#define PCI_CFG_IO_LIMIT 0x1d -#define PCI_CFG_SEC_STATUS 0x1e -#define PCI_CFG_MEM_BASE 0x20 -#define PCI_CFG_MEM_LIMIT 0x22 -#define PCI_CFG_PRE_MEM_BASE 0x24 -#define PCI_CFG_PRE_MEM_LIMIT 0x26 -#define PCI_CFG_PRE_MEM_BASE_U 0x28 -#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c -#define PCI_CFG_IO_BASE_U 0x30 -#define PCI_CFG_IO_LIMIT_U 0x32 -#define PCI_CFG_ROM_BASE 0x38 -#define PCI_CFG_BRG_INT_LINE 0x3c -#define PCI_CFG_BRG_INT_PIN 0x3d -#define PCI_CFG_BRIDGE_CONTROL 0x3e - -/* PCI Class definitions for find by class function */ - -#define PCI_CLASS_PRE_PCI20 0x00 -#define PCI_CLASS_MASS_STORAGE 0x01 -#define PCI_CLASS_NETWORK_CTLR 0x02 -#define PCI_CLASS_DISPLAY_CTLR 0x03 -#define PCI_CLASS_MMEDIA_DEVICE 0x04 -#define PCI_CLASS_MEM_CTLR 0x05 -#define PCI_CLASS_BRIDGE_CTLR 0x06 -#define PCI_CLASS_COMM_CTLR 0x07 -#define PCI_CLASS_BASE_PERIPH 0x08 -#define PCI_CLASS_INPUT_DEVICE 0x09 -#define PCI_CLASS_DOCK_DEVICE 0x0A -#define PCI_CLASS_PROCESSOR 0x0B -#define PCI_CLASS_SERIAL_BUS 0x0C -#define PCI_CLASS_UNDEFINED 0xFF - -/* PCI Subclass definitions */ - -#define PCI_SUBCLASS_00 0x00 -#define PCI_SUBCLASS_01 0x01 -#define PCI_SUBCLASS_02 0x02 -#define PCI_SUBCLASS_03 0x03 -#define PCI_SUBCLASS_04 0x04 -#define PCI_SUBCLASS_05 0x05 -#define PCI_SUBCLASS_06 0x06 -#define PCI_SUBCLASS_07 0x07 -#define PCI_SUBCLASS_10 0x10 -#define PCI_SUBCLASS_20 0x20 -#define PCI_SUBCLASS_80 0x80 - -/* Bridge Device subclasses */ - -#define PCI_SUBCLASS_HOST_PCI_BRIDGE (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_ISA_BRIDGE (PCI_SUBCLASS_01) -#define PCI_SUBCLASS_P2P_BRIDGE (PCI_SUBCLASS_04) -#define PCI_SUBCLASS_PCMCIA_BRIDGE (PCI_SUBCLASS_05) -#define PCI_SUBCLASS_CARDBUS_BRIDGE (PCI_SUBCLASS_07) - -/* Processor subclasses */ - -#define PCI_SUBCLASS_PROCESSOR_386 (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_PROCESSOR_486 (PCI_SUBCLASS_01) -#define PCI_SUBCLASS_PROCESSOR_PENTIUM (PCI_SUBCLASS_02) -#define PCI_SUBCLASS_PROCESSOR_ALPHA (PCI_SUBCLASS_10) -#define PCI_SUBCLASS_PROCESSOR_POWERPC (PCI_SUBCLASS_20) - -/* Serial bus subclasses */ - -#define PCI_SUBCLASS_SERBUS_FIREWIRE (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_SERBUS_USB (PCI_SUBCLASS_03) - -/* Network subclasses */ - -#define PCI_SUBCLASS_NET_ETHERNET (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_NET_TOKEN_RING (PCI_SUBCLASS_01) -#define PCI_SUBCLASS_NET_FDDI (PCI_SUBCLASS_02) -#define PCI_SUBCLASS_NET_ATM (PCI_SUBCLASS_03) - -/* Conditional defines for new configuration definitions */ - -#define PCI_CMD_MASK 0xffff0000 -#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) -#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) - -/* Vendor and Device ID's */ - -/* Promise ATA */ -#define PCI_VENDOR_ID_PROMISE 0x105a -#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 -#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 -#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 -#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 -#define PCI_DEVICE_ID_PROMISE_5300 0x5300 - -/* DEC Ethernet */ -#define PCI_VENDOR_ID_DEC 0x1011 -#define PCI_DEVICE_ID_DEC_BRD 0x0001 -#define PCI_DEVICE_ID_DEC_TULIP 0x0002 -#define PCI_DEVICE_ID_DEC_TGA 0x0004 -#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 -#define PCI_DEVICE_ID_DEC_TGA2 0x000D -#define PCI_DEVICE_ID_DEC_FDDI 0x000F -#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 -#define PCI_DEVICE_ID_DEC_21142 0x0019 -#define PCI_DEVICE_ID_DEC_21052 0x0021 -#define PCI_DEVICE_ID_DEC_21150 0x0022 -#define PCI_DEVICE_ID_DEC_21152 0x0024 -#define PCI_DEVICE_ID_DEC_21153 0x0025 -#define PCI_DEVICE_ID_DEC_21154 0x0026 -#define PCI_DEVICE_ID_DEC_21285 0x1065 -#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 - - - -/* Cache Line Size - 32 32-bit value = 128 bytes */ -#ifndef PCI_CACHE_LINE_SIZE -#define PCI_CACHE_LINE_SIZE 0x20 -#endif /* PCI_CACHE_LINE_SIZE */ - -/* Latency Timer value - 255 PCI clocks */ -#ifndef PCI_LATENCY_TIMER -#define PCI_LATENCY_TIMER 0xff -#endif /* PCI_LATENCY_TIMER */ - -#ifndef _ASMLANGUAGE -int pci_dev_init(int b); -int pci_dev_find(int vid, int devId, int idx,int *bus, int* dev, int* func); -int pci_class_find(int class, int idx, int* bus, int* dev, int *func); -int pci_config_inb(int b, int d, int f, int address, uint8 * pData); -int pci_config_inw(int b, int d, int f, int address, uint16 * pData); -int pci_config_inl(int b, int d, int f, int address, uint32 * pData); -int pci_config_outb(int b, int d, int f, int address, uint8 data); -int pci_config_outw(int b, int d, int f, int address, uint16 data); -int pci_config_outl(int b, int d, int f, int address, uint32 data); -int pci_special_cycle(int b, uint32 message); -int pci_config_bdf_pack(int b, int d, int f); -int pci_dev_config(int b, int d, int f, uint32 iobar, uint32 mbar, uint32 cm ); -int pci_config_modl(int b, int d, int f, int offset, - uint32 bitMask, uint32 data ); -int pci_config_modw(int b, int d, int f, int off, - uint16 bitMask, uint16 data ); -int pci_config_modb(int b, int d, int f, int offset, - uint8 bitMask, uint8 data ); -unsigned int pci_size_bar(unsigned int, unsigned long mask); -#endif /* _ASMLANGUAGE */ - -#endif /* __MPC824X_PCI */ diff --git a/board/mousse/serial.c b/board/mousse/serial.c deleted file mode 100644 index 7d6f9b1..0000000 --- a/board/mousse/serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2000 - * James Dougherty, jfd@cs.stanford.edu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "ns16550.h" - -volatile struct NS16550 *console; - -void -serial_init (unsigned long dummy, int baudrate) -{ - ns16550_init(baudrate); -} - -void -serial_putc(const char c) -{ - if (c == '\n') - { - serial_putc ('\r'); - } - ns16550_putc((unsigned char)c); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - return ns16550_getc(); -} - -int -serial_tstc(void) -{ - return ns16550_tstc(); -} - -void -serial_setbrg (unsigned long dummy, int baudrate) -{ - ns16550_init(baudrate); -} - diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c index db36348..bd4ac2f 100644 --- a/board/mpl/common/isa.c +++ b/board/mpl/common/isa.c @@ -28,7 +28,7 @@ #include #include #include "isa.h" -#include "pci.h" +#include "piix4_pci.h" #include "kbd.h" #include "video.h" diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index 1d10aaa..4dd3d96 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -26,1386 +26,53 @@ */ #include -#include -#include -#include "pci.h" -#include +#include #include "isa.h" - -void pciinfo(int bus_no); #ifdef CONFIG_405GP - #ifdef CONFIG_PCI -#undef PCI_DEBUG - -/*------------------------------------------------------------------------ -| These are the lowest addresses allowed for PCI configuration. -| They correspond to lowest available I/O and Memory addresses. -| In the case where where multiple PMM regs are being used to map -| different PLB to PCI regions, each region should have it's own -| minimum address. -+-----------------------------------------------------------------------*/ -unsigned long LowestMemAddr1 = MIN_PCI_MEMADDR1; -unsigned long LowestMemAddr2 = MIN_PCI_MEMADDR2; -unsigned long LowestIOAddr = MIN_PCI_PCI_IOADDR1; - -unsigned long MaxBusNum = 0; - - - -/*-----------------------------------------------------------------------------+ -| pci_init. Initializes the 405GP PCI Configuration regs. -+-----------------------------------------------------------------------------*/ -void pci_init(bd_t *dummy) -{ - unsigned short temp_short; - -#ifdef CONFIG_PCI_HOST - /*--------------------------------------------------------------------------+ - | 405GP PCI Master configuration. - | Map one 512 MB range of PLB/processor addresses to PCI memory space. - | PLB address 0x80000000-0x9FFFFFFF ==> PCI address 0x80000000-0x9FFFFFFF - | Use byte reversed out routines to handle endianess. - +--------------------------------------------------------------------------*/ - out32r(PMM0MA, 0x00000000); /* ensure disabled b4 setting PMM0LA */ - out32r(PMM0LA, PCI_M0_LOCAL_ADDR); - out32r(PMM0PCILA, PCI_M0_PCI_LOW_ADDR); - out32r(PMM0PCIHA, PCI_M0_PCI_HIGH_ADDR); - out32r(PMM0MA, PCI_M0_MASK_ATTRIB); /* no prefetching, and enable region */ - /*--------------------------------------------------------------------------+ - | Map one 512 MB range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xBFFFFFFF ==> PCI address 0x00000000-0x1FFFFFFF - | Use byte reversed out routines to handle endianess. - | This space is for the VGA card. - +--------------------------------------------------------------------------*/ - out32r(PMM1MA, 0x00000000); /* ensure disabled b4 setting PMM1LA */ - out32r(PMM1LA, PCI_M1_LOCAL_ADDR); - out32r(PMM1PCILA, PCI_M1_PCI_LOW_ADDR); - out32r(PMM1PCIHA, PCI_M1_PCI_HIGH_ADDR); - out32r(PMM1MA, PCI_M1_MASK_ATTRIB); /* no prefetching, and enable region */ - /*--------------------------------------------------------------------------+ - | PMM2 is not used. Initialize them to zero. - +--------------------------------------------------------------------------*/ - out32r(PMM2MA, 0x00000000); /* ensure disabled b4 setting PMM2LA */ - out32r(PMM2LA, PCI_M2_LOCAL_ADDR); - out32r(PMM2PCILA, PCI_M2_PCI_LOW_ADDR); - out32r(PMM2PCIHA, PCI_M2_PCI_HIGH_ADDR); - out32r(PMM2MA, PCI_M2_MASK_ATTRIB); /* not enabled */ -#endif - - /*--------------------------------------------------------------------------+ - | 405GP PCI Target configuration. (PTM1) - | Note: PTM1MS is hardwire enabled but we set the enable bit anyway. - +--------------------------------------------------------------------------*/ - out32r(PTM1LA, CFG_PCI_PTM1LA); /* insert address */ - out32r(PTM1MS, CFG_PCI_PTM1MS); /* insert size, enable bit is 1 */ - - /*--------------------------------------------------------------------------+ - | 405GP PCI Target configuration. (PTM2) - +--------------------------------------------------------------------------*/ - out32r(PTM2LA, CFG_PCI_PTM2LA); /* insert address */ - if (CFG_PCI_PTM2MS == 0) - { - out32r(PTM2MS, 0x00000001); /* set enable bit */ - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCIBASEADDR2, 0x00000000, 4); - out32r(PTM2MS, 0x00000000); /* disable */ - } - else - out32r(PTM2MS, CFG_PCI_PTM2MS); /* insert size, enable bit is 1 */ - - /* - * Insert Subsystem Vendor and Device ID - */ - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSVENDORID, CFG_PCI_SUBSYS_VENDORID, 2); - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSDEVICEID, CFG_PCI_SUBSYS_DEVICEID, 2); - -#ifdef CONFIG_PCI_HOST - /*--------------------------------------------------------------------------+ - | Write the 405GP PCI Configuration regs. - | Enable 405GP to be a master on the PCI bus (PMM). - | Enable 405GP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - temp_short = PCI_Read_CFG_Reg(PCIDEVID_405GP, PCICMD, 2); - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCICMD, temp_short | BM_EN | MEM_EN, 2); -#endif - - - /* - * Set HCE bit (Host Configuration Enabled) - */ - temp_short = PCI_Read_CFG_Reg(PCIDEVID_405GP, PCIBRDGOPT2, 2); - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCIBRDGOPT2,(temp_short | 0x0001), 2); - -#ifdef CONFIG_PCI_PNP - /*--------------------------------------------------------------------------+ - | Scan the PCI bus and configure devices found. - +--------------------------------------------------------------------------*/ - PCI_Scan(0); -#endif /* CONFIG_PCI_PNP */ - -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Read_CFG_Reg -| Description: Read a PCI configuration register -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Width Number of bytes to read (1, 2, or 4) -| Return value: -| (unsigned int) Value of the configuration register read. -| For reads shorter than 4 bytes, return value -| is LSB-justified -+-----------------------------------------------------------------------------*/ -unsigned long PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width) -{ - unsigned int RegAddr; - - /*--------------------------------------------------------------------------+ - | bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) - +--------------------------------------------------------------------------*/ - RegAddr = 0x80000000 | ((Reg|BusDevFunc) & 0xFFFFFFFC); - - /*--------------------------------------------------------------------------+ - | Write reg to PCI Config Address - +--------------------------------------------------------------------------*/ - out32r(PCICFGADR, RegAddr); - - /*--------------------------------------------------------------------------+ - | Read reg value from PCI Config Data - +--------------------------------------------------------------------------*/ - switch (Width) - { - case 1: return ((unsigned int) in8(PCICFGDATA | (Reg & 0x3))); - case 2: return ((unsigned int) in16r(PCICFGDATA | (Reg & 0x3))); - case 4: return (in32r(PCICFGDATA | (Reg & 0x3))); - } - - return 0; /* not reached: just to satisfy the compiler */ -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Write_CFG_Reg -| Description: Write a PCI configuration register. -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Value Configuration register value -| Width Number of bytes to write (1, 2, or 4) -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned long Value, int Width) -{ - unsigned int RegAddr; - unsigned int msr; - - /*--------------------------------------------------------------------------+ - | Ensure interrupts disabled for pass2 errata #6. - +--------------------------------------------------------------------------*/ - msr = mfmsr(); - mtmsr(msr & ~(MSR_EE|MSR_CE)); - - /*--------------------------------------------------------------------------+ - | bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) - +--------------------------------------------------------------------------*/ - RegAddr = 0x80000000 | ((Reg|BusDevFunc) & 0xFFFFFFFC); - /*--------------------------------------------------------------------------+ - | Write reg to PCI Config Address - +--------------------------------------------------------------------------*/ - out32r(PCICFGADR, RegAddr); - - /*--------------------------------------------------------------------------+ - | Write reg value to PCI Config Data - +--------------------------------------------------------------------------*/ - switch (Width) - { - case 1: out8(PCICFGDATA | (Reg & 0x3), (unsigned char)(Value & 0xFF)); - break; - case 2: out16r(PCICFGDATA | (Reg & 0x3),(unsigned short)(Value & 0xFFFF)); - break; - case 4: out32r(PCICFGDATA | (Reg & 0x3), Value); - break; - } - - /*--------------------------------------------------------------------------+ - | Write PCI Config Address after writing PCICFGDATA for pass2 errata #6. - +--------------------------------------------------------------------------*/ - out32r(PCICFGADR, 0x00000000); - - /*--------------------------------------------------------------------------+ - | Restore msr (for pass2 errata #6). - +--------------------------------------------------------------------------*/ - mtmsr(msr); - - return (0); -} +#undef DEBUG +#include "piix4_pci.h" #include "pci_parts.h" -/* - * Returns the pointer to the func config table, or NULL, if it not available - * if the revision is ff in the table, it will not be chcked - */ - -PCI_DEV_CFG_TABLE *PCI_Get_Func_Table(unsigned short vend_id,unsigned short dev_id,unsigned char revision,unsigned char func) +void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) { + struct pci_pip405_config_entry *table; int i; - i=0; - while(pcidevtbl[i].vendorID!=0xffff) { - if((pcidevtbl[i].vendorID == vend_id) && - (pcidevtbl[i].deviceID == dev_id) && - (pcidevtbl[i].func == func) && - ((pcidevtbl[i].revision == 0xff) || (pcidevtbl[i].revision == revision))) { -#ifdef PCI_DEBUG - printf("Table found for 0x%04X 0x%04X\n",vend_id,dev_id); -#endif - return &pcidevtbl[i]; - } - i++; /* proceed all entries */ - } -#ifdef PCI_DEBUG - printf("No Table found for 0x%04X 0x%04X\n",vend_id,dev_id); -#endif - return NULL; -} - - -/*----------------------------------------------------------------------- -| -| Subroutine: PCI_Scan -| -| Prototype: void PCI_Scan(int BusNum) -| -| Description: Scan through all 16 allowable PCI IDs and configure -| those for which the vendor ID indicates there is a -| device present. -| -| Inputs: -| BusNum Bus number where scanning begins -| -| Return value: -| None -| -+----------------------------------------------------------------------*/ -void PCI_Scan(int bus_no) -{ - int device_no,i; - int BusDevFunc; - unsigned short vend_id,dev_id; - unsigned char revision,func,header; - PCI_DEV_CFG_TABLE *pci_dev_table=NULL; - /*--------------------------------------------------------------------------+ - | Start with device 1, the 405GP is device 0. MCG 01/04/99 - +--------------------------------------------------------------------------*/ - /* init all known (on Board devices) first */ - for (device_no = 1; device_no < MAX_PCI_DEVICES; device_no++) - { - BusDevFunc = (bus_no << 16) | (device_no << 11); - if((unsigned short)PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2) != 0xffff) { - header = (unsigned char)PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - for(func=0;funcfcntable[i].width!=0) { - PCI_Write_CFG_Reg(BusDevFunc,pci_dev_table->fcntable[i].index, - pci_dev_table->fcntable[i].val,pci_dev_table->fcntable[i].width); - #ifdef PCI_DEBUG - printf(" Reg 0x%02X Value 0x%08lX Width %02d written\n",pci_dev_table->fcntable[i].index, - pci_dev_table->fcntable[i].val,pci_dev_table->fcntable[i].width); - #endif - i++; - } - if((header & 0x80)==0) - break; /* no more functions */ - } /* next function */ - } /* if device available */ - } /* all devices */ -#if 0 - /*************************************************************************** - * Since the IO and Memory Area of the ISA Bridge is not relocable, config it - * first. - ****************************************************************************/ - isabridgeDev=0; - for (Device = 1; Device < MAX_PCI_DEVICES; Device++) - { - BusDevFunc = (BusNum << 16) | (Device << 11); - if (PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID,2) != 0xFFFF) - { - if(PCI_Read_CFG_Reg(BusDevFunc, PCICLASSCODE,2) == 0x0601) - { - isabridgeDev=Device; - PCI_Config_ISABridge(BusDevFunc); - break; /* do not scan further */ - } - } - } - - for (Device = 1; Device < MAX_PCI_DEVICES; Device++) - { - if(Device==isabridgeDev) - continue; /* skip ISA Bridge */ - - BusDevFunc = (BusNum << 16) | (Device << 11); - - if (PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID,2) != 0xFFFF) - { -#ifdef PCI_DEBUG - printf("Device %d is present\n",Device); -#endif - switch( PCI_Read_CFG_Reg(BusDevFunc, PCICLASSCODE, 2) ) - { - case 0x0604: /* PCI-PCI Bridge */ -#ifdef PCI_DEBUG - printf("Device %d is PCI Bridge\n",Device); -#endif - PCI_Config_Device(BusDevFunc, 2); - PCI_Config_Bridge(BusDevFunc); - break; - case 0x0100: /* PCI-PCI Bridge */ -#ifdef PCI_DEBUG - printf("Device %d is SCSI Controller\n",Device); -#endif - PCI_Config_SCSI_contrl(BusDevFunc); - break; + table = (struct pci_pip405_config_entry*) entry->priv[0]; - case 0x0300: /* VGA Display controller */ - case 0x0001: /* VGA Display controller (pre PCI rev 2.0)*/ -#ifdef PCI_DEBUG - printf("Device %d is VGA\n",Device); -#endif - PCI_Config_VGA_contrl(BusDevFunc); - break; - - default: -#ifdef PCI_DEBUG - printf("Device %d is a 0x%04X\n",Device,PCI_Read_CFG_Reg(BusDevFunc, PCICLASSCODE, 2)); -#endif -/* PCI_Config_Device(BusDevFunc, 6); */ - } - } - else - { + for (i=0; table[i].width; i++) + { #ifdef DEBUG - printf("Device %d not present\n",Device); -#endif - } - } -#endif - -} - - -/*----------------------------------------------------------------------- -| Subroutine: PCI_Config_Device -| -| Description: Configure a PCI device by examining its I/O and memory -| address space needs and allocating address space to it by -| programming the address decoders in the Base Address Registers. -| -| Inputs: -| BusDevFunc Bus+Device+Function number -| NumBaseAddr Number of base address registers to -| configure -| Return value: -| None -+----------------------------------------------------------------------*/ -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) -{ - int AddrSlot, i; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val, int_line = 0; - - for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) - { - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 0xFFFFFFFF,4); - - AddrDesc = PCI_Read_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 4); - - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; /* 01/04/99 MCG */ - -#ifdef PCI_DEBUG - printf("Read Base Addr Reg %d = 0x%08lx\n",AddrSlot,AddrDesc); + printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", + table[i].index, table[i].val, table[i].width); #endif - if ((AddrDesc & 1) == 0) /* Memory */ - { - AddrDesc &= 0xFFFFFFF0; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; - - if ((unsigned long)AddrDesc < 4096) - AddrDesc = 4096; -#ifdef PCI_DEBUG - printf(" PCI Memory space = 0x%lx bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_MEMADDR1; AddrProg < LowestMemAddr1; AddrProg += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestMemAddr1 = AddrProg + AddrDesc; - } - else /* I/O */ - { - AddrDesc &= 0xFFFFFFFC; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; -#ifdef PCI_DEBUG - printf(" PCI I/O space = 0x%lx bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_PCI_IOADDR2; AddrProg < LowestIOAddr; AddrProg += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestIOAddr = AddrProg + AddrDesc; - } - - } - - Min_Gnt_Val = 0x80; - PCI_Write_CFG_Reg(BusDevFunc, PCILATENCYTIM, Min_Gnt_Val, 1); - - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch ((BusDevFunc >> 11) & 0x03) - { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } - PCI_Write_CFG_Reg(BusDevFunc, PCIINTLINE, int_line, 1); - - /* - * Enable i/o space, memory space and master on this device - */ - PCI_Write_CFG_Reg(BusDevFunc, PCICMD, 7, 2); - -} - -/*----------------------------------------------------------------------- -| Subroutine: PCI_Config_VGA_Device -| -| Description: Configure a PCI VGA device by examining its I/O and memory -| address space needs and allocating address space to it by -| programming the address decoders in the Base Address Registers. -| -| Inputs: -| BusDevFunc Bus+Device+Function number -| NumBaseAddr Number of base address registers to -| configure -| Return value: -| None -+----------------------------------------------------------------------*/ -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr) -{ - int AddrSlot, i; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val; - - for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) - { - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 0xFFFFFFFF,4); - - AddrDesc = PCI_Read_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 4); - - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; /* 01/04/99 MCG */ - -#ifdef PCI_DEBUG - printf("VGA Device Read Base Addr Reg %d = 0x%08lx\n",AddrSlot,AddrDesc); -#endif - - if ((AddrDesc & 1) == 0) /* Memory */ - { - AddrDesc &= 0xFFFFFFF0; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; - - if ((unsigned long)AddrDesc < 4096) - AddrDesc = 4096; -#ifdef PCI_DEBUG - printf(" PCI Memory space = 0x%lx bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_MEMADDR2; AddrProg < LowestMemAddr2; AddrProg += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestMemAddr2 = AddrProg + AddrDesc; - } - else /* I/O */ - { - AddrDesc &= 0xFFFFFFFC; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; -#ifdef PCI_DEBUG - printf(" PCI I/O space = 0x%lx bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_PCI_IOADDR2; AddrProg < LowestIOAddr; AddrProg -+= AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestIOAddr = AddrProg + AddrDesc; - } - - } - - Min_Gnt_Val = 0x80; - PCI_Write_CFG_Reg(BusDevFunc, PCILATENCYTIM, Min_Gnt_Val, 1); -} - -/*----------------------------------------------------------------------- -| -| Subroutine: PCI_Config_Bridge -| -| Prototype: void PCI_Config_Bridge(int BusDevFunc) -| -| Description: Configure a PCI-PCI bridge -| -| Inputs: -| BusDevFunc Bus+Device+Function number -| -| Return value: -| None -| -+----------------------------------------------------------------------*/ -void PCI_Config_Bridge(int BusDevFunc) -{ - int SecondaryBus; - int PrimaryBus; - int CommandReg_Val; - int InitialLowestIOAddr, InitialLowestMemAddr; - int IOBase, MemBase; - int IOLimit, MemLimit; - - InitialLowestIOAddr = LowestIOAddr; - InitialLowestMemAddr = LowestMemAddr1; - - CommandReg_Val = (unsigned short)PCI_Read_CFG_Reg(BusDevFunc, PCICMD, 2); - - /* Configure bridge's base address registers */ - - PCI_Config_Device(BusDevFunc, 2); - - if ( LowestIOAddr > InitialLowestIOAddr ) /* bridge uses IO space? */ - CommandReg_Val |= 0x01; /* enable I/O Space */ - - if ( LowestMemAddr1 > InitialLowestMemAddr ) /* bridge uses memory space? */ - CommandReg_Val |= 0x02; /* enable Memory Space */ - - PrimaryBus = (BusDevFunc >> 16) & 0xFF; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_PRIMARYBUS, PrimaryBus, 1); - - SecondaryBus = ++MaxBusNum; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SECONDARYBUS, SecondaryBus, 1); - - /* Start with max. possible value for subordinate bus number */ - /* Later, after any additional child busses are found, we'll update this */ - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, 0xFF, 1); - - /* IO Base must be on 4Kb boundary. Adjust if needed */ - - if ((LowestIOAddr % 4096) != 0) - LowestIOAddr += 4096 - (LowestIOAddr % 4096); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOBASE, (LowestIOAddr>>8) & 0xF0, 1); - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOBASEUPPER16, (LowestIOAddr>>16) & 0xFFFF, 2); - - IOBase = LowestIOAddr; - - /* Mem Base must be on 1 MB boundary. adjust if needed */ - if ((LowestMemAddr1 % 0x100000) != 0) - LowestMemAddr1 += 0x100000 - (LowestMemAddr1 % 0x100000); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_MEMBASE, (LowestMemAddr1>>16) & 0xFFF0, 2); - MemBase = LowestMemAddr1; - - PCI_Scan(SecondaryBus); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, MaxBusNum, 1); - - IOLimit = LowestIOAddr; - if (LowestIOAddr > IOBase) /* IO space used on secondary bus? */ - { - CommandReg_Val |= 0x01; /* enable IO Space */ - IOLimit--; /* IOLimit is highest used address */ - } - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOLIMIT, ((IOLimit)>>8) & 0xF0, 1); - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOLIMITUPPER16, ((IOLimit)>>16) & 0xFFFF, 2); - - /* IOLIMIT is the starting address of a 4K block forwarded by the bridge. */ - /* Round LowestIOAddr up to the next 4K boundary if IO space is enabled. */ - - if ((CommandReg_Val & 0x01) == 0x01) - LowestIOAddr = (IOLimit | 0xFFF) + 1; - - MemLimit = LowestMemAddr1; - if ( LowestMemAddr1 > MemBase ) /* mem. space is used on secondary bus? */ - { - CommandReg_Val |= 0x02; /* enable Memory Space */ - MemLimit--; /* MemLimit is highest used address */ - } - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_MEMLIMIT, ((MemLimit)>>16) & 0xFFF0, 2); - - /* MEMLIMIT is the starting address of a 1M block forwarded by the bridge. */ - /* Round LowestMemAddr up to the next 1M boundary if Memory space is enabled. */ - - if ( (CommandReg_Val & 0x02) == 0x02 ) - LowestMemAddr1 = (MemLimit | 0xFFFFF) + 1; - - /* Enable Bus Master on secondary bus */ - CommandReg_Val |= 0x04; - - PCI_Write_CFG_Reg(BusDevFunc, PCICMD, CommandReg_Val, 2); - -} - -/*----------------------------------------------------------------------- -| Subroutine: PCI_Find_Device -| -| Prototype: int PCI_Find_Device(hword VendorID, hword DeviceID); -| -| Description: -| Locate a PCI device by vendor and device number -| -| Inputs: -| VendorID Value of the device's Vendor ID field -| DeviceID Value of the device's Device ID field -| -| Return value: -| < 0 Device not found -| (int) PCI Bus+Device+Function number -+----------------------------------------------------------------------*/ -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID) -{ - int Device; - int BusDevFunc; - int BusNum; - int Funct; - - for (BusNum = MaxBusNum; BusNum >= 0; BusNum--) - for (Device = 0; Device < MAX_PCI_DEVICES; Device++) - { - for(Funct=0;FunctheaderType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - - if (pD->headerType & 0x01) /* PCI-to-PCI bridge */ - { - pB->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pB->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pB->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pB->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 2); - pB->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pB->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pB->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pB->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pB->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pB->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pB->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pB->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pB->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pB->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pB->priBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRIMARY_BUS, 1); - pB->secBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SECONDARY_BUS, 1); - pB->subBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBORDINATE_BUS, 1); - pB->secLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_LATENCY, 1); - pB->ioBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE, 1); - pB->ioLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT, 1); - pB->secStatus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_STATUS, 2); - pB->memBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_BASE, 2); - pB->memLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_LIMIT, 2); - pB->preBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE, 2); - pB->preLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT, 2); - pB->preBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE_U, 4); - pB->preLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT_U, 4); - pB->ioBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE_U, 2); - pB->ioLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT_U, 2); - pB->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_ROM_BASE, 4); - pB->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_LINE, 1); - pB->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_PIN, 1); - pB->control = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRIDGE_CONTROL, 2); - pciBheaderPrint(pB); - } - else /* PCI device */ - { - pD->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pD->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pD->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pD->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 1); - pD->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pD->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pD->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pD->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pD->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pD->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pD->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pD->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pD->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pD->base2 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_2, 4); - pD->base3 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_3, 4); - pD->base4 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_4, 4); - pD->base5 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_5, 4); - pD->cis = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CIS, 4); - pD->subVendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_VENDER_ID, 2); - pD->subSystemId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_SYSTEM_ID, 2); - pD->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - pD->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 1); - pD->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1); - pD->minGrant = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MIN_GRANT, 1); - pD->maxLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MAX_LATENCY, 1); - pciDheaderPrint(pD); - } -} - -/******************************************************************************* -* -* pciDheaderPrint - print a PCI device header -* -* This routine prints a PCI device header. -* -*/ -void -pciDheaderPrint(PCI_HEADER_DEVICE * pD) -{ - printf (" vendor ID = 0x%.4x\n", (ushort)pD->vendorId); - printf (" device ID = 0x%.4x\n", (ushort)pD->deviceId); - printf (" command register = 0x%.4x\n", (ushort)pD->command); - printf (" status register = 0x%.4x\n", (ushort)pD->status); - printf (" revision ID = 0x%.2x\n", (uchar)pD->revisionId); - printf (" class code = 0x%.2x\n", (uchar)pD->classCode); - printf (" sub class code = 0x%.2x\n", (uchar)pD->subClass); - printf (" programming interface = 0x%.2x\n", (uchar)pD->progIf); - printf (" cache line = 0x%.2x\n", (uchar)pD->cacheLine); - printf (" latency time = 0x%.2x\n", (uchar)pD->latency); - printf (" header type = 0x%.2x\n", (uchar)pD->headerType); - printf (" BIST = 0x%.2x\n", (uchar)pD->bist); - printf (" base address 0 = 0x%.8x\n", pD->base0); - printf (" base address 1 = 0x%.8x\n", pD->base1); - printf (" base address 2 = 0x%.8x\n", pD->base2); - printf (" base address 3 = 0x%.8x\n", pD->base3); - printf (" base address 4 = 0x%.8x\n", pD->base4); - printf (" base address 5 = 0x%.8x\n", pD->base5); - printf (" cardBus CIS pointer = 0x%.8x\n", pD->cis); - printf (" sub system vendor ID = 0x%.4x\n", (ushort)pD->subVendorId); - printf (" sub system ID = 0x%.4x\n", (ushort)pD->subSystemId); - printf (" expansion ROM base address = 0x%.8x\n", pD->romBase); - printf (" interrupt line = 0x%.2x\n", (uchar)pD->intLine); - printf (" interrupt pin = 0x%.2x\n", (uchar)pD->intPin); - printf (" min Grant = 0x%.2x\n", (uchar)pD->minGrant); - printf (" max Latency = 0x%.2x\n", (uchar)pD->maxLatency); -} - -/******************************************************************************* -* -* pciBheaderPrint - print a PCI-to-PCI bridge header -* -* This routine prints a PCI-to-PCI bridge header. -* -*/ -void -pciBheaderPrint(PCI_HEADER_BRIDGE * pB) -{ - printf (" vendor ID = 0x%.4x\n", (ushort)pB->vendorId); - printf (" device ID = 0x%.4x\n", (ushort)pB->deviceId); - printf (" command register = 0x%.4x\n", (ushort)pB->command); - printf (" status register = 0x%.4x\n", (ushort)pB->status); - printf (" revision ID = 0x%.2x\n", (uchar)pB->revisionId); - printf (" class code = 0x%.2x\n", (uchar)pB->classCode); - printf (" sub class code = 0x%.2x\n", (uchar)pB->subClass); - printf (" programming interface = 0x%.2x\n", (uchar)pB->progIf); - printf (" cache line = 0x%.2x\n", (uchar)pB->cacheLine); - printf (" latency time = 0x%.2x\n", (uchar)pB->latency); - printf (" header type = 0x%.2x\n", (uchar)pB->headerType); - printf (" BIST = 0x%.2x\n", (uchar)pB->bist); - printf (" base address 0 = 0x%.8x\n", pB->base0); - printf (" base address 1 = 0x%.8x\n", pB->base1); - printf (" primary bus number = 0x%.2x\n", (uchar)pB->priBus); - printf (" secondary bus number = 0x%.2x\n", (uchar)pB->secBus); - printf (" subordinate bus number = 0x%.2x\n", (uchar)pB->subBus); - printf (" secondary latency timer = 0x%.2x\n", (uchar)pB->secLatency); - printf (" IO base = 0x%.2x\n", (uchar)pB->ioBase); - printf (" IO limit = 0x%.2x\n", (uchar)pB->ioLimit); - printf (" secondary status = 0x%.4x\n", (ushort)pB->secStatus); - printf (" memory base = 0x%.4x\n", (ushort)pB->memBase); - printf (" memory limit = 0x%.4x\n", (ushort)pB->memLimit); - printf (" prefetch memory base = 0x%.4x\n", (ushort)pB->preBase); - printf (" prefetch memory limit = 0x%.4x\n", (ushort)pB->preLimit); - printf (" prefetch memory base upper = 0x%.8x\n", pB->preBaseUpper); - printf (" prefetch memory limit upper = 0x%.8x\n", pB->preLimitUpper); - printf (" IO base upper 16 bits = 0x%.4x\n", (ushort)pB->ioBaseUpper); - printf (" IO limit upper 16 bits = 0x%.4x\n", (ushort)pB->ioLimitUpper); - printf (" expansion ROM base address = 0x%.8x\n", pB->romBase); - printf (" interrupt line = 0x%.2x\n", (uchar)pB->intLine); - printf (" interrupt pin = 0x%.2x\n", (uchar)pB->intPin); - printf (" bridge control = 0x%.4x\n", (ushort)pB->control); -} - - - - -/******************************************************************************* -* -* pciGetHeader0 - gets the header of the specified PCI device -* -* only header 0 . -* -*/ - -int pciGetHeader0(PCI_HEADER_DEVICE * pD,int BusDevFunc) -{ - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - - if ((pD->headerType&0x7F)!=0) /* Not a Header 0 type */ - return FALSE; - else /* PCI device */ - { - pD->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pD->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pD->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pD->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 1); - pD->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pD->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pD->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pD->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pD->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pD->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pD->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pD->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pD->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pD->base2 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_2, 4); - pD->base3 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_3, 4); - pD->base4 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_4, 4); - pD->base5 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_5, 4); - pD->cis = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CIS, 4); - pD->subVendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_VENDER_ID, 2); - pD->subSystemId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_SYSTEM_ID, 2); - pD->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - pD->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 1); - pD->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1); - pD->minGrant = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MIN_GRANT, 1); - pD->maxLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MAX_LATENCY, 1); - } - return TRUE; -} - -/******************************************************************************* -* -* pciGetResource - gets the Resource information of the specified PCI device -* -* -* -*/ -int pciGetResource(PCI_RESOURCE_DESC * pR) -{ - PCI_HEADER_DEVICE headerDevice; - int basereg, i; - unsigned long AddrDesc; - - - if(pciGetHeader0(&headerDevice,pR->BusDevFunc)==FALSE) - return FALSE; /* no header 0 type */ - /* fill in read only fields */ - pR->vendorId = headerDevice.vendorId; - pR->deviceId = headerDevice.deviceId; - pR->revisionId = headerDevice.revisionId; - pR->classCode = headerDevice.classCode; - pR->subClass = headerDevice.subClass; - pR->progIf = headerDevice.progIf; - pR->intLine = headerDevice.intLine; - pR->intPin = headerDevice.intPin; - pR->headerType = headerDevice.headerType; - pR->pciInt = 0; /* no Interrupt as default */ - /* calculate the PCI Interrupt if any.. */ - if(pR->intPin!=0) - { - /* interrupts are routed as follows: - - Device 6, INTA# = INTA# - - Device 7, INTA# = INTB# - - Device 8, INTA# = INTC# - - Device 9, INTA# = INTD# - - Device A, INTA# = INTA# - - Device 0 must be INTA# = INTC# */ - i=(pR->BusDevFunc >> 11) & 0x1F; /* max 32 devices (Bus nr not yet implemented) */ - i=i%4; /* dev0 and INTA# = INTC# */ - i+=1; /* Adjust it (first step) */ - i+=pR->intPin; - pR->pciInt=(char)((i%4)+1); /* 2nd step */ - } - /* try to get memory or io descriptions */ - for (basereg = 0; basereg < MAX_PCI_BASE_REG; basereg++) - { - pR->size[basereg]=0; /* delete size */ - pR->attr[basereg]=DESC_IS_NOT_VALID; - PCI_Write_CFG_Reg(pR->BusDevFunc, PCIBASEADDR0 + (4*basereg), 0xFFFFFFFF,4); - AddrDesc = PCI_Read_CFG_Reg(pR->BusDevFunc, PCIBASEADDR0 + (4*basereg), 4); - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; - if ((AddrDesc&0x3)==0x1) /* is IO */ + switch(table[i].width) { - pR->attr[basereg]=DESC_IS_IO; - /* determine size, all bytes which are don't care are 0 */ - AddrDesc&=0xFFFFFFFC; /* delete Atributes */ - AddrDesc=~AddrDesc; - AddrDesc&=0x0000FFFF; /* Mask unused bits */ - pR->size[basereg]=AddrDesc+1; /* size */ - } - else - { - pR->attr[basereg]=DESC_IS_MEM; - switch((AddrDesc&0x6)>>1) - { - case 0x1: - pR->attr[basereg]|=DESC_IS_LOWMEM; /* locate it below 1M */ - break; - case 0x2: - pR->attr[basereg]|=DESC_IS_64BIT; /* dual Address.. increment base reg later */ - break; - case 0x3: - pR->attr[basereg]=DESC_IS_NOT_VALID; /* Error */ - break; - } /* case */ - if((AddrDesc&0x8)==0x8) /* is prefetchable */ - pR->attr[basereg]|=DESC_IS_PREFETCH; - /* 64Bit addressing not implemented */ - if((pR->attr[basereg]&DESC_IS_64BIT)==DESC_IS_64BIT) - { - basereg++; - if(baseregsize[basereg]=0; /* delete size */ - pR->attr[basereg]=DESC_IS_NOT_VALID; - } - continue; - } /* if DESC_IS_64BIT */ - /* determine size */ - AddrDesc&=0xFFFFFFF0;/* delete attributes */ - AddrDesc=~AddrDesc; - pR->size[basereg]=AddrDesc+1; /* size */ - } /* else */ - } /* for basereg */ - return TRUE; -} - -#if 0 -/************************************************************************************* -* pcishowrees -*/ -void pciShowRes(PCI_RESOURCE_DESC *pD) -{ - int i, match; - printf("%02d:%02d:%02d ",(char)(pD->BusDevFunc>>16)&0xFF, - (char)(pD->BusDevFunc>>11)&0x1F,(char)(pD->BusDevFunc>>8)&0x3); - - /* search memory desc */ - match=0; - for(i=0;iattr[i]&DESC_IS_IO)==DESC_IS_IO) - { - printf("%4lX ",pD->size[i]); - match=1; + case 1: pci_write_config_byte(dev, table[i].index, table[i].val); break; + case 2: pci_write_config_word(dev, table[i].index, table[i].val); break; + case 4: pci_write_config_dword(dev, table[i].index, table[i].val); break; } } - if(match==0) - printf(" "); - match=0; - for(i=0;iattr[i]&DESC_IS_MEM)==DESC_IS_MEM) - { - printf("%8lX ",pD->size[i]); - match=1; - } - } - if(match==0) - printf(" "); - if(pD->intPin==0) - printf(" "); - else - printf("INT%c# ",(pD->pciInt + 'A')-1); - switch (pD->classCode) - { - case 0x00: - switch(pD->subClass) - { - case 0: printf("not VGA"); break; - case 1: printf("VGA"); break; - default: printf("unknown"); break; - } - printf("Pre Class: "); - break; - case 0x01: - switch(pD->subClass) - { - case 0x00: printf("SCSI "); break; - case 0x01: printf("IDE "); break; - case 0x02: printf("Floppy "); break; - case 0x03: printf("IPI "); break; - case 0x04: printf("RAID "); break; - case 0x88: printf("other "); break; - default: printf("unknown "); break; - } - printf("Mass Storage "); - break; - case 0x02: - switch(pD->subClass) - { - case 0x00: printf("Ethernet"); break; - case 0x01: printf("Token Ring"); break; - case 0x02: printf("FDDI"); break; - case 0x03: printf("ATM"); break; - case 0x80: printf("other"); break; - default: printf("unknown"); break; - } - printf(" Network Controller "); - break; - case 0x03: - switch(pD->subClass) - { - case 0x00: printf("%s",((pD->progIf&0x1)==0x1)? "8514 comp":"VGA"); break; - case 0x01: printf("XGA"); break; - case 0x80: printf("other"); break; - default: printf("unknown"); break; - } - printf(" Display Cont. "); - break; - case 0x04: - switch(pD->subClass) - { - case 0x00: printf("Video"); break; - case 0x01: printf("Audio"); break; - case 0x80: printf("other"); break; - default: printf("unknown"); break; - } - printf(" Multimedia Device "); - break; - case 0x05: - switch(pD->subClass) - { - case 0x00: printf("RAM"); break; - case 0x01: printf("Flash"); break; - case 0x80: printf("other"); break; - default: printf("unknown"); break; - } - printf(" Memory Device "); - break; - case 0x06: - switch(pD->subClass) - { - case 0x00: printf("HostBridge"); break; - case 0x01: printf("ISA"); break; - case 0x02: printf("EISA"); break; - case 0x03: printf("MCA"); break; - case 0x04: printf("PCI-PCI"); break; - case 0x05: printf("PCMCIA"); break; - case 0x06: printf("NuBus"); break; - case 0x07: printf("CardBus"); break; - case 0x80: printf("other"); break; - default: printf("unknown"); break; - } - printf(" Bridge "); - break; - case 0x07: - switch(pD->subClass) - { - case 0x00: - switch(pD->progIf) - { - case 0: printf("Generic XT Serial Controller ");break; - case 1: printf("16450 Serial Controller ");break; - case 2: printf("16550 Serial Controller ");break; - default: printf("unknown Serial Controller ");break; - } - break; - case 0x01: - switch(pD->progIf) - { - case 0: printf("Paralell Port ");break; - case 1: printf("Bidirectional Paralell Port ");break; - case 2: printf("ECP 1.X Paralell Port ");break; - default: printf("unknown Paralall Port ");break; - } - break; - case 0x80: printf("other Simple Communications Controller "); break; - default: printf("unknown Simple Communications Controller "); break; - } - break; - case 0x08: - switch(pD->subClass) - { - case 0x00: - switch(pD->progIf) - { - case 0: printf("Generic 8259 PIC ");break; - case 1: printf("ISA PIC ");break; - case 2: printf("EISA PIC ");break; - default: printf("unknown PIC ");break; - } - break; - case 0x01: - switch(pD->progIf) - { - case 0: printf("Generic 8237 DMA ");break; - case 1: printf("ISA DMA ");break; - case 2: printf("EISA DMA ");break; - default: printf("unknown DMA ");break; - } - break; - case 0x02: - switch(pD->progIf) - { - case 0: printf("Generic 8254 Timer ");break; - case 1: printf("ISA Timer ");break; - case 2: printf("EISA Timer ");break; - default: printf("unknown Timer ");break; - } - break; - case 0x03: - switch(pD->progIf) - { - case 0: printf("Generic RTC ");break; - case 1: printf("ISA RTC ");break; - default: printf("unknown RTC ");break; - } - break; - case 0x80: printf("other Generic System Peripherals "); break; - default: printf("unknown Generic System Peripherals "); break; - } - break; - case 0x09: - switch(pD->subClass) - { - case 0x00: printf("Keyboard Controller "); break; - case 0x01: printf("Digitizer "); break; - case 0x02: printf("Mouse "); break; - case 0x80: printf("other Input Device "); break; - default: printf("unknown Input Device "); break; - } - break; - case 0x0A: - switch(pD->subClass) - { - case 0x00: printf("Generic Docking Station "); break; - case 0x80: printf("other Docking Device "); break; - default: printf("unknown Docking Device "); break; - } - break; - case 0x0B: - switch(pD->subClass) - { - case 0x00: printf("386 "); break; - case 0x01: printf("486 "); break; - case 0x02: printf("Pentium "); break; - case 0x10: printf("Alpha "); break; - case 0x20: printf("PowerPC "); break; - case 0x40: printf("Co-"); break; - default: printf("unknown "); break; - } - printf("Processor "); - break; - case 0x0C: - switch(pD->subClass) - { - case 0x00: printf("FireWire "); break; - case 0x01: printf("ACCESS.bus "); break; - case 0x02: printf("SSA "); break; - case 0x03: printf("USB "); break; - case 0x04: printf("Fibre Channel "); break; - default: printf("unknown Serial Bus "); break; - } - break; - } /* Switch */ - printf("\n"); } -#endif +extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev); +extern void pci_405gp_init(bd_t* bd, struct pci_controller *hose); -#if 0 -/************************************************************************************** -* pciScanforDevices -*/ +static struct pci_controller hose = { + config_table: pci_pip405_config_table, + fixup_irq: pci_405gp_fixup_irq, +}; -void pciScanForDevices(int BusNum) +void pci_init(bd_t *bd) { - - PCI_RESOURCE_DESC resourcedesc; - int Device,Function,BusDevFunc; - unsigned short vendor_id,vendor_id2; - - printf("PCI IO Memory IRQ Device\n"); - /* 00:00:00 1234 12345678 INTA# DD */ - for (Device = 1; Device < MAX_PCI_DEVICES; Device++) - { - BusDevFunc = (BusNum << 16) | (Device << 11); /* scan only function 0 */ - vendor_id = PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID,2); - if (vendor_id != 0xFFFF) - { - - for(Function=0;Function PCI address 0x80000000-0x9FFFFFFF - * Use byte reversed out routines to handle endianess. - ***********************************************************************/ -#define PCI_M0_LOCAL_ADDR 0x80000000 -#define PCI_M0_PCI_LOW_ADDR 0x80000000 -#define PCI_M0_PCI_HIGH_ADDR 0x00000000 -#define PCI_M0_MASK_ATTRIB 0xE0000001 /* no prefetching, and enable region */ -/************************************************************************** - * Map one 512 MB range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xBFFFFFFF ==> PCI address 0x00000000-0x1FFFFFFF - * This space is for the VGA card. - **************************************************************************/ -#define PCI_M1_LOCAL_ADDR 0xA0000000 -#define PCI_M1_PCI_LOW_ADDR 0x00000000 -#define PCI_M1_PCI_HIGH_ADDR 0x00000000 -#define PCI_M1_MASK_ATTRIB 0xE0000001 /* no prefetching, and enable region */ -/*************************************************************************** - * PMM2 is not used. Initialize them to zero. - *****************************************************************************/ -#define PCI_M2_LOCAL_ADDR 0x00000000 -#define PCI_M2_PCI_LOW_ADDR 0x00000000 -#define PCI_M2_PCI_HIGH_ADDR 0x00000000 -#define PCI_M2_MASK_ATTRIB 0x00000000 /* not enabled */ - -typedef struct pciHeaderDevice -{ - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - int base2; /* base address 2 */ - int base3; /* base address 3 */ - int base4; /* base address 4 */ - int base5; /* base address 5 */ - int cis; /* cardBus CIS pointer */ - short subVendorId; /* sub system vendor ID */ - short subSystemId; /* sub system ID */ - int romBase; /* expansion ROM base address */ - int reserved0; /* reserved */ - int reserved1; /* reserved */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - char minGrant; /* min Grant */ - char maxLatency; /* max Latency */ -} PCI_HEADER_DEVICE; - -typedef struct pciHeaderBridge -{ - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - char priBus; /* primary bus number */ - char secBus; /* secondary bus number */ - char subBus; /* subordinate bus number */ - char secLatency; /* secondary latency timer */ - char ioBase; /* IO base */ - char ioLimit; /* IO limit */ - short secStatus; /* secondary status */ - short memBase; /* memory base */ - short memLimit; /* memory limit */ - short preBase; /* prefetchable memory base */ - short preLimit; /* prefetchable memory limit */ - int preBaseUpper; /* prefetchable memory base upper 32 bits */ - int preLimitUpper; /* prefetchable memory base upper 32 bits */ - short ioBaseUpper; /* IO base upper 16 bits */ - short ioLimitUpper; /* IO limit upper 16 bits */ - int reserved; /* reserved */ - int romBase; /* expansion ROM base address */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - short control; /* bridge control */ - } PCI_HEADER_BRIDGE; - - -typedef struct pciRecourceDesc -{ - unsigned long BusDevFunc; /* location of the device */ - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char headerType; /* header type */ - unsigned long size[MAX_PCI_BASE_REG]; /* memory sizes */ - char attr[MAX_PCI_BASE_REG]; /* memory attributes */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - char pciInt; /* Pci Interrupt Line ( 0 = no, 1 = A...)*/ -} PCI_RESOURCE_DESC; - - -/* table for PCI Initialization */ - -typedef struct { - const int index; - const unsigned long val; - const int with; -} PCI_CFG_TABLE; - - -typedef struct { - int index; /* address */ - unsigned long val; /* value */ - int width; /* data size */ -}PCI_FCN_CFG_TABLE; - -typedef struct { - unsigned short vendorID; /* Vendor ID */ - unsigned short deviceID; /* Device ID */ - unsigned char revision; /* Device ID */ - unsigned char func; /* Function number */ - PCI_FCN_CFG_TABLE fcntable[10]; -}PCI_DEV_CFG_TABLE; - - -unsigned long PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned long Value, int Width); -void PCI_Scan(int BusNum); -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_Bridge(int BusDevFunc); -void PCI_Dump_Device(int BusDevFunc); -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); -void pciHeaderShow(int BusDevFunc); -void pciDheaderPrint(PCI_HEADER_DEVICE * pD); -void pciBheaderPrint(PCI_HEADER_BRIDGE * pB); -void PCI_Config_ISABridge(int BusDevFunc); -void PCI_Config_VGA_contrl(int BusDevFunc); - -void pciScanForDevices(int BusNum); -void pciShowRes(PCI_RESOURCE_DESC *pd); -int pciGetResource(PCI_RESOURCE_DESC * pR); -int pciGetHeader0(PCI_HEADER_DEVICE * pD,int BusDevFunc); - -/*************************************************************************** -* Defines PIIX4 Config Registers -****************************************************************************/ - -/* Function 0 ISA Bridge */ -#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ -#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ -#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ -#define PCI_CFG_PIIX4_SERIRQ 0x64 -#define PCI_CFG_PIIX4_TOM 0x69 -#define PCI_CFG_PIIX4_MSTAT 0x6A -#define PCI_CFG_PIIX4_MBDMA 0x76 -#define PCI_CFG_PIIX4_APICBS 0x80 -#define PCI_CFG_PIIX4_DLC 0x82 -#define PCI_CFG_PIIX4_PDMACFG 0x90 -#define PCI_CFG_PIIX4_DDMABS 0x92 -#define PCI_CFG_PIIX4_GENCFG 0xB0 -#define PCI_CFG_PIIX4_RTCCFG 0xCB - -/* IO Addresses */ -#define PIIX4_ISA_DMA1_CH0BA 0x00 -#define PIIX4_ISA_DMA1_CH0CA 0x01 -#define PIIX4_ISA_DMA1_CH1BA 0x02 -#define PIIX4_ISA_DMA1_CH1CA 0x03 -#define PIIX4_ISA_DMA1_CH2BA 0x04 -#define PIIX4_ISA_DMA1_CH2CA 0x05 -#define PIIX4_ISA_DMA1_CH3BA 0x06 -#define PIIX4_ISA_DMA1_CH3CA 0x07 -#define PIIX4_ISA_DMA1_CMDST 0x08 -#define PIIX4_ISA_DMA1_REQ 0x09 -#define PIIX4_ISA_DMA1_WSBM 0x0A -#define PIIX4_ISA_DMA1_CH_MOD 0x0B -#define PIIX4_ISA_DMA1_CLR_PT 0x0C -#define PIIX4_ISA_DMA1_M_CLR 0x0D -#define PIIX4_ISA_DMA1_CLR_M 0x0E -#define PIIX4_ISA_DMA1_RWAMB 0x0F - -#define PIIX4_ISA_DMA2_CH0BA 0xC0 -#define PIIX4_ISA_DMA2_CH0CA 0xC1 -#define PIIX4_ISA_DMA2_CH1BA 0xC2 -#define PIIX4_ISA_DMA2_CH1CA 0xC3 -#define PIIX4_ISA_DMA2_CH2BA 0xC4 -#define PIIX4_ISA_DMA2_CH2CA 0xC5 -#define PIIX4_ISA_DMA2_CH3BA 0xC6 -#define PIIX4_ISA_DMA2_CH3CA 0xC7 -#define PIIX4_ISA_DMA2_CMDST 0xD0 -#define PIIX4_ISA_DMA2_REQ 0xD2 -#define PIIX4_ISA_DMA2_WSBM 0xD4 -#define PIIX4_ISA_DMA2_CH_MOD 0xD6 -#define PIIX4_ISA_DMA2_CLR_PT 0xD8 -#define PIIX4_ISA_DMA2_M_CLR 0xDA -#define PIIX4_ISA_DMA2_CLR_M 0xDC -#define PIIX4_ISA_DMA2_RWAMB 0xDE - -#define PIIX4_ISA_INT1_ICW1 0x20 -#define PIIX4_ISA_INT1_OCW2 0x20 -#define PIIX4_ISA_INT1_OCW3 0x20 -#define PIIX4_ISA_INT1_ICW2 0x21 -#define PIIX4_ISA_INT1_ICW3 0x21 -#define PIIX4_ISA_INT1_ICW4 0x21 -#define PIIX4_ISA_INT1_OCW1 0x21 - -#define PIIX4_ISA_INT1_ELCR 0x4D0 - -#define PIIX4_ISA_INT2_ICW1 0xA0 -#define PIIX4_ISA_INT2_OCW2 0xA0 -#define PIIX4_ISA_INT2_OCW3 0xA0 -#define PIIX4_ISA_INT2_ICW2 0xA1 -#define PIIX4_ISA_INT2_ICW3 0xA1 -#define PIIX4_ISA_INT2_ICW4 0xA1 -#define PIIX4_ISA_INT2_OCW1 0xA1 -#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ - -#define PIIX4_ISA_INT2_ELCR 0x4D1 - -#define PIIX4_ISA_TMR0_CNT_ST 0x40 -#define PIIX4_ISA_TMR1_CNT_ST 0x41 -#define PIIX4_ISA_TMR2_CNT_ST 0x42 -#define PIIX4_ISA_TMR_TCW 0x43 - -#define PIIX4_ISA_RST_XBUS 0x60 - -#define PIIX4_ISA_NMI_CNT_ST 0x61 -#define PIIX4_ISA_NMI_ENABLE 0x70 - -#define PIIX4_ISA_RTC_INDEX 0x70 -#define PIIX4_ISA_RTC_DATA 0x71 -#define PIIX4_ISA_RTCEXT_IND 0x70 -#define PIIX4_ISA_RTCEXT_DATA 0x71 - -#define PIIX4_ISA_DMA1_CH2LPG 0x81 -#define PIIX4_ISA_DMA1_CH3LPG 0x82 -#define PIIX4_ISA_DMA1_CH1LPG 0x83 -#define PIIX4_ISA_DMA1_CH0LPG 0x87 -#define PIIX4_ISA_DMA2_CH2LPG 0x89 -#define PIIX4_ISA_DMA2_CH3LPG 0x8A -#define PIIX4_ISA_DMA2_CH1LPG 0x8B -#define PIIX4_ISA_DMA2_LPGRFR 0x8F - -#define PIIX4_ISA_PORT_92 0x92 - -#define PIIX4_ISA_APM_CONTRL 0xB2 -#define PIIX4_ISA_APM_STATUS 0xB3 - -#define PIIX4_ISA_COCPU_ERROR 0xF0 - -/* Function 1 IDE Controller */ -#define PCI_CFG_PIIX4_BMIBA 0x20 -#define PCI_CFG_PIIX4_IDETIM 0x40 -#define PCI_CFG_PIIX4_SIDETIM 0x44 -#define PCI_CFG_PIIX4_UDMACTL 0x48 -#define PCI_CFG_PIIX4_UDMATIM 0x4A - -/* Function 2 USB Controller */ -#define PCI_CFG_PIIX4_SBRNUM 0x60 -#define PCI_CFG_PIIX4_LEGSUP 0xC0 - -/* Function 3 Power Management */ -#define PCI_CFG_PIIX4_PMAB 0x40 -#define PCI_CFG_PIIX4_CNTA 0x44 -#define PCI_CFG_PIIX4_CNTB 0x48 -#define PCI_CFG_PIIX4_GPICTL 0x4C -#define PCI_CFG_PIIX4_DEVRESD 0x50 -#define PCI_CFG_PIIX4_DEVACTA 0x54 -#define PCI_CFG_PIIX4_DEVACTB 0x58 -#define PCI_CFG_PIIX4_DEVRESA 0x5C -#define PCI_CFG_PIIX4_DEVRESB 0x60 -#define PCI_CFG_PIIX4_DEVRESC 0x64 -#define PCI_CFG_PIIX4_DEVRESE 0x68 -#define PCI_CFG_PIIX4_DEVRESF 0x6C -#define PCI_CFG_PIIX4_DEVRESG 0x70 -#define PCI_CFG_PIIX4_DEVRESH 0x74 -#define PCI_CFG_PIIX4_DEVRESI 0x78 - - -#endif diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h index 5fb884e..6eb79b2 100644 --- a/board/mpl/common/pci_parts.h +++ b/board/mpl/common/pci_parts.h @@ -78,50 +78,107 @@ * +-------------+------------+------------+--------------------------------+ */ -static PCI_DEV_CFG_TABLE pcidevtbl[]={ +struct pci_pip405_config_entry { + int index; /* address */ + unsigned long val; /* value */ + int width; /* data size */ +}; + +extern void pci_pip405_write_regs(struct pci_controller *, + pci_dev_t, + struct pci_config_table *); + /* PIIX4 ISA Bridge Function 0 */ -{0x8086,0x7110, 0xff,0, { - {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1},/* enable Continous SERIRQ Pin */ - {PCI_CFG_PIIX4_GENCFG, 0x00010000, 4},/* enable SERIRQs */ - {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ - {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ - {0xFFFF, 0,0}} /* end of device table */ -}, +static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = { + {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */ + {PCI_CFG_PIIX4_GENCFG, 0x00010000, 4}, /* enable SERIRQs */ + {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ + {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ + { } /* end of device table */ +}; + /* PIIX4 IDE Controller Function 1 */ -{0x8086,0x7111,0xff,1,{ - {PCI_CFG_COMMAND, 0x0001, 2},/* enable IO access */ - {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4},/* enable Both IDE channels */ - {0xFFFF, 0,0}} /* end of device table */ -}, +static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = { + {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ + {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */ + { } /* end of device table */ +}; + /* PIIX4 USB Controller Function 2 */ -{0x8086,0x7112,0xff,2,{ - {PCI_CFG_DEV_INT_LINE, 31, 1},/* Int vector = 31 */ - {PCI_CFG_BASE_ADDRESS_4, 0x0000E001, 4},/* Set IO Address to 0xe000 to 0xe01F */ - {PCI_CFG_LATENCY_TIMER, 0x80, 1},/* Latency Timer 0x80 */ - {0xC0, 0x2000, 2}, /* Legacy support */ - {PCI_CFG_COMMAND, 0x0005, 2},/* enable IO access and Master */ - {0xFFFF, 0,0}} /* end of device table */ -}, +static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = { + {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ + {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */ + {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ + {0xC0, 0x2000, 2}, /* Legacy support */ + {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */ + { } /* end of device table */ +}; + /* VGA Controller ct69000 (logical device 0) */ -{0x102C,0x00C0,0xff,0,{ - {PCI_CFG_BASE_ADDRESS_0, 0x80000000, 4},/* Frame buffer access */ - {PCI_CFG_EXPANSION_ROM, 0x00000000, 4},/* disable ROM */ - {PCI_CFG_DEV_INT_LINE, 29, 1},/* Int vector = 29 */ - {PCI_CFG_COMMAND, 0x0003, 2},/* enable IO access */ - {0xFFFF, 0,0}} /* end of device table */ -}, +static struct pci_pip405_config_entry vga_ct69000[] = { + {PCI_BASE_ADDRESS_0, 0x80000000, 4}, /* Frame buffer access */ + {PCI_ROM_ADDRESS, 0x00000000, 4}, /* disable ROM */ + {PCI_INTERRUPT_LINE, 29, 1}, /* Int vector = 29 */ + {PCI_COMMAND, 0x0003, 2}, /* enable IO access */ + { } /* end of device table */ +}; + /* Symbois 810 function 0 */ -{0x1000,0x0001,0xff,0,{ - {PCI_CFG_BASE_ADDRESS_0, 0x00001001, 4},/* IO Base address */ - {PCI_CFG_BASE_ADDRESS_1, 0x81000000, 4},/* Memory Base address */ - {PCI_CFG_DEV_INT_LINE, 30, 1},/* Int vector = 30 */ - {PCI_CFG_COMMAND, 0x0006, 2},/* enable Memory access and busmaster */ - {0xFFFF, 0,0}} /* end of device table */ -}, -/* Terminator */ -{0xffff,0xffff,0xff,0xff,{ - {0xFFFF, 0,0}} /* end of device table */ -} +static struct pci_pip405_config_entry symbois_810_f0[] = { + {PCI_BASE_ADDRESS_0, 0x00001001, 4}, /* IO Base address */ + {PCI_BASE_ADDRESS_1, 0x81000000, 4}, /* Memory Base address */ + {PCI_INTERRUPT_LINE, 30, 1}, /* Int vector = 30 */ + {PCI_COMMAND, 0x0006, 2}, /* enable Memory access and busmaster */ + {0xFFFF, 0,0} /* end of device table */ +}; + +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry); + +static struct pci_config_table pci_pip405_config_table[]={ + {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ + PCI_DEVICE_ID_INTEL_82371AB_0, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 0, + pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}}, + + {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */ + PCI_DEVICE_ID_INTEL_82371AB, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 1, + pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}}, + + {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */ + PCI_DEVICE_ID_INTEL_82371AB_2, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 2, + pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}}, + + {PCI_VENDOR_ID_CT, /* VGA Controller ct69000 (logical device 0) */ + PCI_DEVICE_ID_CT_69000, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 0, + pci_pip405_write_regs, {(unsigned long) vga_ct69000}}, + + {PCI_VENDOR_ID_NCR, /* Symbois 810 function 0 */ + PCI_DEVICE_ID_NCR_53C810, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 0, + pci_pip405_write_regs, {(unsigned long) symbois_810_f0}}, + + {PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_405gp_setup_vga}, + + {PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_405gp_setup_vga}, + + { } }; #endif /* _PCI_PARTS_H_ */ diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h new file mode 100644 index 0000000..ce9f835 --- /dev/null +++ b/board/mpl/common/piix4_pci.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + + +#ifndef _PIIX4_PCI_H +#define _PIIX4_PCI_H + +/*************************************************************************** +* Defines PIIX4 Config Registers +****************************************************************************/ + +/* Function 0 ISA Bridge */ +#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ +#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ +#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ +#define PCI_CFG_PIIX4_SERIRQ 0x64 +#define PCI_CFG_PIIX4_TOM 0x69 +#define PCI_CFG_PIIX4_MSTAT 0x6A +#define PCI_CFG_PIIX4_MBDMA 0x76 +#define PCI_CFG_PIIX4_APICBS 0x80 +#define PCI_CFG_PIIX4_DLC 0x82 +#define PCI_CFG_PIIX4_PDMACFG 0x90 +#define PCI_CFG_PIIX4_DDMABS 0x92 +#define PCI_CFG_PIIX4_GENCFG 0xB0 +#define PCI_CFG_PIIX4_RTCCFG 0xCB + +/* IO Addresses */ +#define PIIX4_ISA_DMA1_CH0BA 0x00 +#define PIIX4_ISA_DMA1_CH0CA 0x01 +#define PIIX4_ISA_DMA1_CH1BA 0x02 +#define PIIX4_ISA_DMA1_CH1CA 0x03 +#define PIIX4_ISA_DMA1_CH2BA 0x04 +#define PIIX4_ISA_DMA1_CH2CA 0x05 +#define PIIX4_ISA_DMA1_CH3BA 0x06 +#define PIIX4_ISA_DMA1_CH3CA 0x07 +#define PIIX4_ISA_DMA1_CMDST 0x08 +#define PIIX4_ISA_DMA1_REQ 0x09 +#define PIIX4_ISA_DMA1_WSBM 0x0A +#define PIIX4_ISA_DMA1_CH_MOD 0x0B +#define PIIX4_ISA_DMA1_CLR_PT 0x0C +#define PIIX4_ISA_DMA1_M_CLR 0x0D +#define PIIX4_ISA_DMA1_CLR_M 0x0E +#define PIIX4_ISA_DMA1_RWAMB 0x0F + +#define PIIX4_ISA_DMA2_CH0BA 0xC0 +#define PIIX4_ISA_DMA2_CH0CA 0xC1 +#define PIIX4_ISA_DMA2_CH1BA 0xC2 +#define PIIX4_ISA_DMA2_CH1CA 0xC3 +#define PIIX4_ISA_DMA2_CH2BA 0xC4 +#define PIIX4_ISA_DMA2_CH2CA 0xC5 +#define PIIX4_ISA_DMA2_CH3BA 0xC6 +#define PIIX4_ISA_DMA2_CH3CA 0xC7 +#define PIIX4_ISA_DMA2_CMDST 0xD0 +#define PIIX4_ISA_DMA2_REQ 0xD2 +#define PIIX4_ISA_DMA2_WSBM 0xD4 +#define PIIX4_ISA_DMA2_CH_MOD 0xD6 +#define PIIX4_ISA_DMA2_CLR_PT 0xD8 +#define PIIX4_ISA_DMA2_M_CLR 0xDA +#define PIIX4_ISA_DMA2_CLR_M 0xDC +#define PIIX4_ISA_DMA2_RWAMB 0xDE + +#define PIIX4_ISA_INT1_ICW1 0x20 +#define PIIX4_ISA_INT1_OCW2 0x20 +#define PIIX4_ISA_INT1_OCW3 0x20 +#define PIIX4_ISA_INT1_ICW2 0x21 +#define PIIX4_ISA_INT1_ICW3 0x21 +#define PIIX4_ISA_INT1_ICW4 0x21 +#define PIIX4_ISA_INT1_OCW1 0x21 + +#define PIIX4_ISA_INT1_ELCR 0x4D0 + +#define PIIX4_ISA_INT2_ICW1 0xA0 +#define PIIX4_ISA_INT2_OCW2 0xA0 +#define PIIX4_ISA_INT2_OCW3 0xA0 +#define PIIX4_ISA_INT2_ICW2 0xA1 +#define PIIX4_ISA_INT2_ICW3 0xA1 +#define PIIX4_ISA_INT2_ICW4 0xA1 +#define PIIX4_ISA_INT2_OCW1 0xA1 +#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ + +#define PIIX4_ISA_INT2_ELCR 0x4D1 + +#define PIIX4_ISA_TMR0_CNT_ST 0x40 +#define PIIX4_ISA_TMR1_CNT_ST 0x41 +#define PIIX4_ISA_TMR2_CNT_ST 0x42 +#define PIIX4_ISA_TMR_TCW 0x43 + +#define PIIX4_ISA_RST_XBUS 0x60 + +#define PIIX4_ISA_NMI_CNT_ST 0x61 +#define PIIX4_ISA_NMI_ENABLE 0x70 + +#define PIIX4_ISA_RTC_INDEX 0x70 +#define PIIX4_ISA_RTC_DATA 0x71 +#define PIIX4_ISA_RTCEXT_IND 0x70 +#define PIIX4_ISA_RTCEXT_DATA 0x71 + +#define PIIX4_ISA_DMA1_CH2LPG 0x81 +#define PIIX4_ISA_DMA1_CH3LPG 0x82 +#define PIIX4_ISA_DMA1_CH1LPG 0x83 +#define PIIX4_ISA_DMA1_CH0LPG 0x87 +#define PIIX4_ISA_DMA2_CH2LPG 0x89 +#define PIIX4_ISA_DMA2_CH3LPG 0x8A +#define PIIX4_ISA_DMA2_CH1LPG 0x8B +#define PIIX4_ISA_DMA2_LPGRFR 0x8F + +#define PIIX4_ISA_PORT_92 0x92 + +#define PIIX4_ISA_APM_CONTRL 0xB2 +#define PIIX4_ISA_APM_STATUS 0xB3 + +#define PIIX4_ISA_COCPU_ERROR 0xF0 + +/* Function 1 IDE Controller */ +#define PCI_CFG_PIIX4_BMIBA 0x20 +#define PCI_CFG_PIIX4_IDETIM 0x40 +#define PCI_CFG_PIIX4_SIDETIM 0x44 +#define PCI_CFG_PIIX4_UDMACTL 0x48 +#define PCI_CFG_PIIX4_UDMATIM 0x4A + +/* Function 2 USB Controller */ +#define PCI_CFG_PIIX4_SBRNUM 0x60 +#define PCI_CFG_PIIX4_LEGSUP 0xC0 + +/* Function 3 Power Management */ +#define PCI_CFG_PIIX4_PMAB 0x40 +#define PCI_CFG_PIIX4_CNTA 0x44 +#define PCI_CFG_PIIX4_CNTB 0x48 +#define PCI_CFG_PIIX4_GPICTL 0x4C +#define PCI_CFG_PIIX4_DEVRESD 0x50 +#define PCI_CFG_PIIX4_DEVACTA 0x54 +#define PCI_CFG_PIIX4_DEVACTB 0x58 +#define PCI_CFG_PIIX4_DEVRESA 0x5C +#define PCI_CFG_PIIX4_DEVRESB 0x60 +#define PCI_CFG_PIIX4_DEVRESC 0x64 +#define PCI_CFG_PIIX4_DEVRESE 0x68 +#define PCI_CFG_PIIX4_DEVRESF 0x6C +#define PCI_CFG_PIIX4_DEVRESG 0x70 +#define PCI_CFG_PIIX4_DEVRESH 0x74 +#define PCI_CFG_PIIX4_DEVRESI 0x78 + + +#endif diff --git a/board/mpl/common/sym53c8xx.c b/board/mpl/common/sym53c8xx.c deleted file mode 100644 index 6afc282..0000000 --- a/board/mpl/common/sym53c8xx.c +++ /dev/null @@ -1,751 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * partly derived from - * linux/drivers/scsi/sym53c8xx.c - * - */ - -/* - * SCSI support based on the chip sym53C810. - */ - -#include -#include -#include -#include "pci.h" -#include -#include "sym53c8xx_defs.h" -#include - -#undef SYM53C8XX_DEBUG - -#ifdef SYM53C8XX_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) - - -#undef SCSI_SINGLE_STEP -/* - * Single Step is only used for debug purposes - */ -#ifdef SCSI_SINGLE_STEP -static unsigned long start_script_select; -static unsigned long start_script_msgout; -static unsigned long start_script_msgin; -static unsigned long start_script_msg_ext; -static unsigned long start_script_cmd; -static unsigned long start_script_data_in; -static unsigned long start_script_data_out; -static unsigned long start_script_status; -static unsigned long start_script_complete; -static unsigned long start_script_error; -static unsigned long start_script_reselection; -static unsigned int len_script_select; -static unsigned int len_script_msgout; -static unsigned int len_script_msgin; -static unsigned int len_script_msg_ext; -static unsigned int len_script_cmd; -static unsigned int len_script_data_in; -static unsigned int len_script_data_out; -static unsigned int len_script_status; -static unsigned int len_script_complete; -static unsigned int len_script_error; -static unsigned int len_script_reselection; -#endif - - -static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ -static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ -static unsigned long script_select[8]; /* script for selection */ -static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ -static unsigned long script_msgin[14]; /* script for message in phase */ -static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ -static unsigned long script_cmd[18]; /* script for command phase */ -static unsigned long script_data_in[8]; /* script for data in phase */ -static unsigned long script_data_out[8]; /* script for data out phase */ -static unsigned long script_status[6]; /* script for status phase */ -static unsigned long script_complete[10]; /* script for complete */ -static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ -static unsigned long script_error[2]; /* script for error handling */ - -static unsigned long int_stat[3]; /* interrupt status */ -static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ - - -#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ - -#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ -#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ - -/********************************************************************************* - * forward declerations - */ - -void scsi_chip_init(void); -void handle_scsi_int(void); - - -/******************************************************************************** - * reports SCSI errors to the user - */ -void scsi_print_error(ccb *pccb) -{ - int i; - printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); - printf(" CCB: "); - for(i=0;icmdlen;i++) - printf("%02X ",pccb->cmd[i]); - printf("(len=%d)\n",pccb->cmdlen); - printf(" Cntrl: "); - switch(pccb->contr_stat) { - case SIR_COMPLETE: printf("Complete (no Error)\n"); break; - case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; - case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; - case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; - case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; - case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; - case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; - case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; - case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; - case INT_ON_FY: printf("Interrupt on fly\n"); break; - case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; - case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; - case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; - case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; - default: printf("unknown status %lx\n",pccb->contr_stat); break; - } - printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); - switch(pccb->sense_buf[2]&0xf) { - case SENSE_NO_SENSE: printf("No Sense)"); break; - case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; - case SENSE_NOT_READY: printf("Not Ready)"); break; - case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; - case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; - case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; - case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; - case SENSE_DATA_PROTECT: printf("Data Protect)"); break; - case SENSE_BLANK_CHECK: printf("Blank check)"); break; - case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; - case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; - case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; - case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; - case SENSE_MISCOMPARE: printf("Misscompare\n"); break; - default: printf("Illegal Sensecode\n"); break; - } - printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); - printf(" Status: "); - switch(pccb->status) { - case S_GOOD : printf("Good\n"); break; - case S_CHECK_COND: printf("Check condition\n"); break; - case S_COND_MET: printf("Condition Met\n"); break; - case S_BUSY: printf("Busy\n"); break; - case S_INT: printf("Intermediate\n"); break; - case S_INT_COND_MET: printf("Intermediate condition met\n"); break; - case S_CONFLICT: printf("Reservation conflict\n"); break; - case S_TERMINATED: printf("Command terminated\n"); break; - case S_QUEUE_FULL: printf("Task set full\n"); break; - default: printf("unknown: %02X\n",pccb->status); break; - } - -} - - - -/****************************************************************************** - * sets-up the SCSI controller - * the base memory address is retrived via the PCI_Read_CFG_Reg - */ -void scsi_low_level_init(int busdevfunc) -{ - unsigned long addr; - unsigned char vec; - vec=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_DEV_INT_LINE, 1); - addr=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_BASE_ADDRESS_1, 4); - scsi_mem_addr=addr; - scsi_chip_init(); - scsi_bus_reset(); - irq_install_handler(vec, (interrupt_handler_t *)handle_scsi_int, NULL); -} - - -/************************************************************************************ - * Low level Part of SCSI Driver - */ - -/* - * big-endian -> little endian conversion for the script - */ -unsigned long swap_script(unsigned long val) -{ - unsigned long tmp; - tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); - return tmp; -} - - -void scsi_write_byte(ulong offset,unsigned char val) -{ - out8(scsi_mem_addr+offset,val); -} - - -unsigned char scsi_read_byte(ulong offset) -{ - return(in8(scsi_mem_addr+offset)); -} - - -/******************************************************************************** - * interrupt handler - */ -void handle_scsi_int(void) -{ - unsigned char stat,stat1,stat2; - unsigned short sstat; - int i; -#ifdef SCSI_SINGLE_STEP - unsigned long tt; -#endif - stat=scsi_read_byte(ISTAT); - if((stat & DIP)==DIP) { /* DMA Interrupt pending */ - stat1=scsi_read_byte(DSTAT); -#ifdef SCSI_SINGLE_STEP - if((stat1 & SSI)==SSI) - { - tt=in32r(scsi_mem_addr+DSP); - if(((tt)>=start_script_select) && ((tt)<=start_script_select+len_script_select)) { - printf("select %d\n",(tt-start_script_select)>>2); - goto end_single; - } - if(((tt)>=start_script_msgout) && ((tt)<=start_script_msgout+len_script_msgout)) { - printf("msgout %d\n",(tt-start_script_msgout)>>2); - goto end_single; - } - if(((tt)>=start_script_msgin) && ((tt)<=start_script_msgin+len_script_msgin)) { - printf("msgin %d\n",(tt-start_script_msgin)>>2); - goto end_single; - } - if(((tt)>=start_script_msg_ext) && ((tt)<=start_script_msg_ext+len_script_msg_ext)) { - printf("msgin_ext %d\n",(tt-start_script_msg_ext)>>2); - goto end_single; - } - if(((tt)>=start_script_cmd) && ((tt)<=start_script_cmd+len_script_cmd)) { - printf("cmd %d\n",(tt-start_script_cmd)>>2); - goto end_single; - } - if(((tt)>=start_script_data_in) && ((tt)<=start_script_data_in+len_script_data_in)) { - printf("data_in %d\n",(tt-start_script_data_in)>>2); - goto end_single; - } - if(((tt)>=start_script_data_out) && ((tt)<=start_script_data_out+len_script_data_out)) { - printf("data_out %d\n",(tt-start_script_data_out)>>2); - goto end_single; - } - if(((tt)>=start_script_status) && ((tt)<=start_script_status+len_script_status)) { - printf("status %d\n",(tt-start_script_status)>>2); - goto end_single; - } - if(((tt)>=start_script_complete) && ((tt)<=start_script_complete+len_script_complete)) { - printf("complete %d\n",(tt-start_script_complete)>>2); - goto end_single; - } - if(((tt)>=start_script_error) && ((tt)<=start_script_error+len_script_error)) { - printf("error %d\n",(tt-start_script_error)>>2); - goto end_single; - } - if(((tt)>=start_script_reselection) && ((tt)<=start_script_reselection+len_script_reselection)) { - printf("reselection %d\n",(tt-start_script_reselection)>>2); - goto end_single; - } - printf("sc: %lx\n",tt); -end_single: - stat2=scsi_read_byte(DCNTL); - stat2|=STD; - scsi_write_byte(DCNTL,stat2); - } -#endif - if((stat1 & SIR)==SIR) /* script interrupt */ - { - int_stat[0]=in32(scsi_mem_addr+DSPS); - } - if((stat1&DFE)==0) { /* fifo not epmty */ - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ - stat2=scsi_read_byte(STEST3); - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ - } - } - if((stat & SIP)==SIP) { /* scsi interrupt */ - sstat = (unsigned short)scsi_read_byte(SIST+1); - sstat <<=8; - sstat |= (unsigned short)scsi_read_byte(SIST); - for(i=0;i<3;i++) { - if(int_stat[i]==0) - break; /* found an empty int status */ - } - int_stat[i]=SCSI_INT_STATE | sstat; - stat1=scsi_read_byte(DSTAT); - if((stat1&DFE)==0) { /* fifo not epmty */ - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ - stat2=scsi_read_byte(STEST3); - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ - } - } - if((stat & INTF)==INTF) { /* interrupt on Fly */ - scsi_write_byte(ISTAT,stat); /* clear it */ - for(i=0;i<3;i++) { - if(int_stat[i]==0) - break; /* found an empty int status */ - } - int_stat[i]=INT_ON_FY; - } -} - - -void scsi_bus_reset(void) -{ - unsigned char t; - int i; - t=scsi_read_byte(SCNTL1); - scsi_write_byte(SCNTL1,(t | CRST)); - udelay(50); - scsi_write_byte(SCNTL1,t); - for(i=0;i<2000;i++) - udelay(1000); /* 2sec to give the devices time to spin up */ - scsi_chip_init(); /* reinit the chip ...*/ - -} - -void scsi_int_enable(void) -{ - scsi_write_byte(SIEN,(unsigned char)scsi_int_mask); - scsi_write_byte(SIEN+1,(unsigned char)(scsi_int_mask>>8)); - scsi_write_byte(DIEN,script_int_mask); -} - -void scsi_write_dsp(unsigned long start) -{ - unsigned long val; -#ifdef SCSI_SINGLE_STEP - unsigned char t; -#endif - val = start; - out32r(scsi_mem_addr + DSP,start); -#ifdef SCSI_SINGLE_STEP - t=scsi_read_byte(DCNTL); - t|=STD; - scsi_write_byte(DCNTL,t); -#endif -} - -/* only used for debug purposes */ -void scsi_print_script(void) -{ - printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); - printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); - printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); - printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); - printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); - printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); - printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); - printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); - printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); - printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); -} - - - -void scsi_set_script(ccb *pccb) -{ - int i; - i=0; - script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); - script_select[i++]=0; /* LED ON */ - script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ - script_select[i++]=0; - /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ - script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); - script_select[i++]=swap_script((unsigned long)&script_cmd[0x04]); /* error handling */ - script_select[i++]=swap_script(SCR_JUMP); /* next section */ - /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ - script_select[i++]=swap_script((unsigned long)&script_cmd[0]); /* command out */ - -#ifdef SCSI_SINGLE_STEP - start_script_select=(unsigned long)&script_select[0]; - len_script_select=i*4; -#endif - - i=0; - script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); - script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; - script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); - script_msgout[i++]=swap_script((unsigned long)&pccb->msgout[0]); - script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ - script_msgout[i++]=swap_script((unsigned long)&script_cmd[0]); /* switch to command */ - script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ - script_msgout[i++]=SIR_MSG_OUT_NO_CMD; - -#ifdef SCSI_SINGLE_STEP - start_script_msgout=(unsigned long)&script_msgout[0]; - len_script_msgout=i*4; -#endif - i=0; - script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); - script_cmd[i++]=swap_script((unsigned long)&pccb->cmd[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ - script_cmd[i++]=swap_script((unsigned long)&script_msgin[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ - script_cmd[i++]=swap_script((unsigned long)&script_data_out[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ - script_cmd[i++]=swap_script((unsigned long)&script_data_in[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ - script_cmd[i++]=swap_script((unsigned long)&script_status[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ - script_cmd[i++]=swap_script((unsigned long)&script_cmd[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ - script_cmd[i++]=swap_script((unsigned long)&script_msgout[0]); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ - script_cmd[i++]=swap_script((unsigned long)&script_msgin[0]); - script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ - script_cmd[i++]=SIR_CMD_OUT_ILL_PH; -#ifdef SCSI_SINGLE_STEP - start_script_cmd=(unsigned long)&script_cmd[0]; - len_script_cmd=i*4; -#endif - i=0; - script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ - script_data_out[i++]=swap_script((unsigned long)pccb->pdata); /* pointer to buffer */ - script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); - script_data_out[i++]=swap_script((unsigned long)&script_status[0]); - script_data_out[i++]=swap_script(SCR_INT); - script_data_out[i++]=SIR_DATA_OUT_ERR; - -#ifdef SCSI_SINGLE_STEP - start_script_data_out=(unsigned long)&script_data_out[0]; - len_script_data_out=i*4; -#endif - i=0; - script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ - script_data_in[i++]=swap_script((unsigned long)pccb->pdata); /* pointer to buffer */ - script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); - script_data_in[i++]=swap_script((unsigned long)&script_status[0]); - script_data_in[i++]=swap_script(SCR_INT); - script_data_in[i++]=SIR_DATA_IN_ERR; -#ifdef SCSI_SINGLE_STEP - start_script_data_in=(unsigned long)&script_data_in[0]; - len_script_data_in=i*4; -#endif - i=0; - script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); - script_msgin[i++]=swap_script((unsigned long)&pccb->msgin[0]); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); - script_msgin[i++]=swap_script((unsigned long)&script_complete[0]); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); - script_msgin[i++]=swap_script((unsigned long)&script_complete[0]); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); - script_msgin[i++]=swap_script((unsigned long)&script_complete[0]); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); - script_msgin[i++]=swap_script((unsigned long)&script_complete[0]); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); - script_msgin[i++]=swap_script((unsigned long)&script_msg_ext[0]); - script_msgin[i++]=swap_script(SCR_INT); - script_msgin[i++]=SIR_MSG_RECEIVED; -#ifdef SCSI_SINGLE_STEP - start_script_msgin=(unsigned long)&script_msgin[0]; - len_script_msgin=i*4; -#endif - i=0; - script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ - script_msg_ext[i++]=0; - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[1]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[2]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[3]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[4]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[5]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[6]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script((unsigned long)&pccb->msgin[7]); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script((unsigned long)&script_complete[0]); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_INT); - script_msg_ext[i++]=SIR_MSG_OVER7; -#ifdef SCSI_SINGLE_STEP - start_script_msg_ext=(unsigned long)&script_msg_ext[0]; - len_script_msg_ext=i*4; -#endif - i=0; - script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); - script_status[i++]=swap_script((unsigned long)&pccb->status); - script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); - script_status[i++]=swap_script((unsigned long)&script_msgin[0]); - script_status[i++]=swap_script(SCR_INT); - script_status[i++]=SIR_STATUS_ILL_PH; -#ifdef SCSI_SINGLE_STEP - start_script_status=(unsigned long)&script_status[0]; - len_script_status=i*4; -#endif - i=0; - script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_WAIT_DISC); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); - script_complete[i++]=0; /* LED OFF */ - script_complete[i++]=swap_script(SCR_INT); - script_complete[i++]=SIR_COMPLETE; -#ifdef SCSI_SINGLE_STEP - start_script_complete=(unsigned long)&script_complete[0]; - len_script_complete=i*4; -#endif - i=0; - script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ - script_error[i++]=SIR_SCRIPT_ERROR; -#ifdef SCSI_SINGLE_STEP - start_script_error=(unsigned long)&script_error[0]; - len_script_error=i*4; -#endif - i=0; - script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ - script_reselection[i++]=0; - script_reselection[i++]=swap_script(SCR_WAIT_RESEL); - script_reselection[i++]=swap_script((unsigned long)&script_select[0]); /* len = 4 */ -#ifdef SCSI_SINGLE_STEP - start_script_reselection=(unsigned long)&script_reselection[0]; - len_script_reselection=i*4; -#endif -} - - - -void scsi_issue(ccb *pccb) -{ - int i; - unsigned short sstat; - int retrycnt; /* retry counter */ - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - /* struct pccb must be set-up correctly */ - retrycnt=0; - PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); - pccb->trans_bytes=0; /* no bytes transfered yet */ - scsi_set_script(pccb); /* fill in SCRIPT */ - scsi_int_mask=STO | UDC | MA; /* Interrupts which are enabled */ - script_int_mask=0xff; /* enable all Ints */ - scsi_int_enable(); - scsi_write_dsp((unsigned long)&script_select[0]); /* start script */ - /* now we have to wait for IRQs */ -retry: - while(int_stat[0]==0); - if(int_stat[0]==SIR_COMPLETE) { - if(pccb->msgin[0]==M_DISCONNECT) { - PRINTF("Wait for reselection\n"); - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - scsi_write_dsp((unsigned long)&script_reselection[0]); /* start reselection script */ - goto retry; - } - pccb->contr_stat=SIR_COMPLETE; - return; - } - if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ - sstat=(unsigned short)int_stat[0]; - if((sstat & STO)==STO) { /* selection timeout */ - pccb->contr_stat=SCSI_SEL_TIME_OUT; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Selection Timeout\n",pccb->target); - return; - } - if((sstat & UDC)==UDC) { /* unexpected disconnect */ - pccb->contr_stat=SCSI_UNEXP_DIS; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); - return; - } - if((sstat & RSL)==RSL) { /* reselection */ - pccb->contr_stat=SCSI_UNEXP_DIS; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); - return; - } - if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ - if(retrycnttrans_bytes=pccb->datalen - - ((unsigned long)scsi_read_byte(DBC) | - ((unsigned long)scsi_read_byte(DBC+1)<<8) | - ((unsigned long)scsi_read_byte(DBC+2)<<16)); - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - retrycnt++; - PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", - pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); - scsi_write_dsp((unsigned long)&script_cmd[4]); /* start retry script */ - goto retry; - } - if((sstat & MA)==MA) - pccb->contr_stat=SCSI_MA_TIME_OUT; - else - pccb->contr_stat=SCSI_HNS_TIME_OUT; - PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); - return; - } /* no phase int */ - PRINTF("SCSI INT %lX\n",int_stat[0]); - pccb->contr_stat=int_stat[0]; - return; - } /* end scsi int */ - PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); - pccb->contr_stat=int_stat[0]; - return; -} - -int scsi_exec(ccb *pccb) -{ - unsigned char tmpcmd[16],tmpstat; - int i,retrycnt,t; - unsigned long transbytes,datalen; - unsigned char *tmpptr; - retrycnt=0; -retry: - scsi_issue(pccb); - if(pccb->contr_stat!=SIR_COMPLETE) - return FALSE; - if(pccb->status==S_GOOD) - return TRUE; - if(pccb->status==S_CHECK_COND) { /* check condition */ - for(i=0;i<16;i++) - tmpcmd[i]=pccb->cmd[i]; - pccb->cmd[0]=SCSI_REQ_SENSE; - pccb->cmd[1]=pccb->lun<<5; - pccb->cmd[2]=0; - pccb->cmd[3]=0; - pccb->cmd[4]=14; - pccb->cmd[5]=0; - pccb->cmdlen=6; - pccb->msgout[0]=SCSI_IDENTIFY; - transbytes=pccb->trans_bytes; - tmpptr=pccb->pdata; - pccb->pdata=&pccb->sense_buf[0]; - datalen=pccb->datalen; - pccb->datalen=14; - tmpstat=pccb->status; - scsi_issue(pccb); - for(i=0;i<16;i++) - pccb->cmd[i]=tmpcmd[i]; - pccb->trans_bytes=transbytes; - pccb->pdata=tmpptr; - pccb->datalen=datalen; - pccb->status=tmpstat; - PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, - pccb->sense_buf[12],pccb->sense_buf[13]); - switch(pccb->sense_buf[2]&0xf) { - case SENSE_NO_SENSE: - case SENSE_RECOVERED_ERROR: - /* seems to be ok */ - return TRUE; - break; - case SENSE_NOT_READY: - if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { - /* if device is not in process of becoming ready */ - return FALSE; - break; - } /* else fall through */ - case SENSE_UNIT_ATTENTION: - if(retrycnttarget,retrycnt); - for(t=0;ttarget,retrycnt); - return FALSE; - default: - return FALSE; - } - } - PRINTF("Status = %X\n",pccb->status); - return FALSE; -} - - - - -void scsi_chip_init(void) -{ - /* first we issue a soft reset */ - scsi_write_byte(ISTAT,SRST); - udelay(1000); - scsi_write_byte(ISTAT,0); - /* setup chip */ - scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ - scsi_write_byte(SCNTL1,0x00); - scsi_write_byte(SCNTL2,0x00); - scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ - scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ - scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ - scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ - scsi_int_mask=0x0000; /* no Interrupt is enabled */ - script_int_mask=0x00; - scsi_int_enable(); - scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ - scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ - scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ - scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ - scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ - scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ - scsi_write_byte(STEST3,0x80); /* enable tolerANT */ - scsi_write_byte(CTEST3,0x04); /* clear FIFO */ - scsi_write_byte(CTEST4,0x00); - scsi_write_byte(CTEST5,0x00); -#ifdef SCSI_SINGLE_STEP - scsi_write_byte(DCNTL,IRQM | SSM); - scsi_write_byte(DMODE,MAN); -#else - scsi_write_byte(DCNTL,IRQM); - scsi_write_byte(DMODE,0x00); -#endif -} -#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ - - diff --git a/board/mpl/common/sym53c8xx_defs.h b/board/mpl/common/sym53c8xx_defs.h deleted file mode 100644 index 1eb96ab..0000000 --- a/board/mpl/common/sym53c8xx_defs.h +++ /dev/null @@ -1,582 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * Most of these definitions are derived from - * linux/drivers/scsi/sym53c8xx_defs.h - * - */ - -#ifndef _SYM53C8XX_DEFS_H -#define _SYM53C8XX_DEFS_H - - -#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ - -#define SCNTL1 0x01 /* no reset */ - #define ISCON 0x10 /* connected to scsi */ - #define CRST 0x08 /* force reset */ - #define IARB 0x02 /* immediate arbitration */ - -#define SCNTL2 0x02 /* no disconnect expected */ - #define SDU 0x80 /* cmd: disconnect will raise error */ - #define CHM 0x40 /* sta: chained mode */ - #define WSS 0x08 /* sta: wide scsi send [W]*/ - #define WSR 0x01 /* sta: wide scsi received [W]*/ - -#define SCNTL3 0x03 /* cnf system clock dependent */ - #define EWS 0x08 /* cmd: enable wide scsi [W]*/ - #define ULTRA 0x80 /* cmd: ULTRA enable */ - /* bits 0-2, 7 rsvd for C1010 */ - -#define SCID 0x04 /* cnf host adapter scsi address */ - #define RRE 0x40 /* r/w:e enable response to resel. */ - #define SRE 0x20 /* r/w:e enable response to select */ - -#define SXFER 0x05 /* ### Sync speed and count */ - /* bits 6-7 rsvd for C1010 */ - -#define SDID 0x06 /* ### Destination-ID */ - -#define GPREG 0x07 /* ??? IO-Pins */ - -#define SFBR 0x08 /* ### First byte in phase */ - -#define SOCL 0x09 - #define CREQ 0x80 /* r/w: SCSI-REQ */ - #define CACK 0x40 /* r/w: SCSI-ACK */ - #define CBSY 0x20 /* r/w: SCSI-BSY */ - #define CSEL 0x10 /* r/w: SCSI-SEL */ - #define CATN 0x08 /* r/w: SCSI-ATN */ - #define CMSG 0x04 /* r/w: SCSI-MSG */ - #define CC_D 0x02 /* r/w: SCSI-C_D */ - #define CI_O 0x01 /* r/w: SCSI-I_O */ - -#define SSID 0x0a - -#define SBCL 0x0b - -#define DSTAT 0x0c - #define DFE 0x80 /* sta: dma fifo empty */ - #define MDPE 0x40 /* int: master data parity error */ - #define BF 0x20 /* int: script: bus fault */ - #define ABRT 0x10 /* int: script: command aborted */ - #define SSI 0x08 /* int: script: single step */ - #define SIR 0x04 /* int: script: interrupt instruct. */ - #define IID 0x01 /* int: script: illegal instruct. */ - -#define SSTAT0 0x0d - #define ILF 0x80 /* sta: data in SIDL register lsb */ - #define ORF 0x40 /* sta: data in SODR register lsb */ - #define OLF 0x20 /* sta: data in SODL register lsb */ - #define AIP 0x10 /* sta: arbitration in progress */ - #define LOA 0x08 /* sta: arbitration lost */ - #define WOA 0x04 /* sta: arbitration won */ - #define IRST 0x02 /* sta: scsi reset signal */ - #define SDP 0x01 /* sta: scsi parity signal */ - -#define SSTAT1 0x0e - #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ - -#define SSTAT2 0x0f - #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ - #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ - #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ - #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ - #define LDSC 0x02 /* sta: disconnect & reconnect */ - -#define DSA 0x10 /* --> Base page */ -#define DSA1 0x11 -#define DSA2 0x12 -#define DSA3 0x13 - -#define ISTAT 0x14 /* --> Main Command and status */ - #define CABRT 0x80 /* cmd: abort current operation */ - #define SRST 0x40 /* mod: reset chip */ - #define SIGP 0x20 /* r/w: message from host to ncr */ - #define SEM 0x10 /* r/w: message between host + ncr */ - #define CON 0x08 /* sta: connected to scsi */ - #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ - #define SIP 0x02 /* sta: scsi-interrupt */ - #define DIP 0x01 /* sta: host/script interrupt */ - - -#define CTEST0 0x18 -#define CTEST1 0x19 -#define CTEST2 0x1a - #define CSIGP 0x40 - /* bits 0-2,7 rsvd for C1010 */ - -#define CTEST3 0x1b - #define FLF 0x08 /* cmd: flush dma fifo */ - #define CLF 0x04 /* cmd: clear dma fifo */ - #define FM 0x02 /* mod: fetch pin mode */ - #define WRIE 0x01 /* mod: write and invalidate enable */ - /* bits 4-7 rsvd for C1010 */ - -#define DFIFO 0x20 -#define CTEST4 0x21 - #define BDIS 0x80 /* mod: burst disable */ - #define MPEE 0x08 /* mod: master parity error enable */ - -#define CTEST5 0x22 - #define DFS 0x20 /* mod: dma fifo size */ - /* bits 0-1, 3-7 rsvd for C1010 */ -#define CTEST6 0x23 - -#define DBC 0x24 /* ### Byte count and command */ -#define DNAD 0x28 /* ### Next command register */ -#define DSP 0x2c /* --> Script Pointer */ -#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ - -#define SCRATCHA 0x34 /* Temporary register a */ -#define SCRATCHA1 0x35 -#define SCRATCHA2 0x36 -#define SCRATCHA3 0x37 - -#define DMODE 0x38 - #define BL_2 0x80 /* mod: burst length shift value +2 */ - #define BL_1 0x40 /* mod: burst length shift value +1 */ - #define ERL 0x08 /* mod: enable read line */ - #define ERMP 0x04 /* mod: enable read multiple */ - #define BOF 0x02 /* mod: burst op code fetch */ - #define MAN 0x01 /* mod: manual start */ - -#define DIEN 0x39 -#define SBR 0x3a - -#define DCNTL 0x3b /* --> Script execution control */ - #define CLSE 0x80 /* mod: cache line size enable */ - #define PFF 0x40 /* cmd: pre-fetch flush */ - #define PFEN 0x20 /* mod: pre-fetch enable */ - #define SSM 0x10 /* mod: single step mode */ - #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ - #define STD 0x04 /* cmd: start dma mode */ - #define IRQD 0x02 /* mod: irq disable */ - #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ - /* bits 0-1 rsvd for C1010 */ - -#define ADDER 0x3c - -#define SIEN 0x40 /* -->: interrupt enable */ -#define SIST 0x42 /* <--: interrupt status */ - #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ - #define STO 0x0400/* sta: timeout (select) */ - #define GEN 0x0200/* sta: timeout (general) */ - #define HTH 0x0100/* sta: timeout (handshake) */ - #define MA 0x80 /* sta: phase mismatch */ - #define CMP 0x40 /* sta: arbitration complete */ - #define SEL 0x20 /* sta: selected by another device */ - #define RSL 0x10 /* sta: reselected by another device*/ - #define SGE 0x08 /* sta: gross error (over/underflow)*/ - #define UDC 0x04 /* sta: unexpected disconnect */ - #define RST 0x02 /* sta: scsi bus reset detected */ - #define PAR 0x01 /* sta: scsi parity error */ - -#define SLPAR 0x44 -#define SWIDE 0x45 -#define MACNTL 0x46 -#define GPCNTL 0x47 -#define STIME0 0x48 /* cmd: timeout for select&handshake*/ -#define STIME1 0x49 /* cmd: timeout user defined */ -#define RESPID 0x4a /* sta: Reselect-IDs */ - -#define STEST0 0x4c - -#define STEST1 0x4d - #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ - #define DBLEN 0x08 /* clock doubler running */ - #define DBLSEL 0x04 /* clock doubler selected */ - - -#define STEST2 0x4e - #define ROF 0x40 /* reset scsi offset (after gross error!) */ - #define EXT 0x02 /* extended filtering */ - -#define STEST3 0x4f - #define TE 0x80 /* c: tolerAnt enable */ - #define HSC 0x20 /* c: Halt SCSI Clock */ - #define CSF 0x02 /* c: clear scsi fifo */ - -#define SIDL 0x50 /* Lowlevel: latched from scsi data */ -#define STEST4 0x52 - #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ - #define SMODE_HVD 0x40 /* High Voltage Differential */ - #define SMODE_SE 0x80 /* Single Ended */ - #define SMODE_LVD 0xc0 /* Low Voltage Differential */ - #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ - /* bits 0-5 rsvd for C1010 */ - -#define SODL 0x54 /* Lowlevel: data out to scsi data */ - -#define SBDL 0x58 /* Lowlevel: data from scsi data */ - - - - -/*----------------------------------------------------------- -** -** Utility macros for the script. -** -**----------------------------------------------------------- -*/ - -#define REG(r) (r) - -/*----------------------------------------------------------- -** -** SCSI phases -** -** DT phases illegal for ncr driver. -** -**----------------------------------------------------------- -*/ - -#define SCR_DATA_OUT 0x00000000 -#define SCR_DATA_IN 0x01000000 -#define SCR_COMMAND 0x02000000 -#define SCR_STATUS 0x03000000 -#define SCR_DT_DATA_OUT 0x04000000 -#define SCR_DT_DATA_IN 0x05000000 -#define SCR_MSG_OUT 0x06000000 -#define SCR_MSG_IN 0x07000000 - -#define SCR_ILG_OUT 0x04000000 -#define SCR_ILG_IN 0x05000000 - -/*----------------------------------------------------------- -** -** Data transfer via SCSI. -** -**----------------------------------------------------------- -** -** MOVE_ABS (LEN) -** <> -** -** MOVE_IND (LEN) -** <> -** -** MOVE_TBL -** <> -** -**----------------------------------------------------------- -*/ - -#define OPC_MOVE 0x08000000 - -#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) - -#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) -#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) -#define SCR_CHMOV_TBL (0x10000000) - - -/*----------------------------------------------------------- -** -** Selection -** -**----------------------------------------------------------- -** -** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] -** <> -** -** SEL_TBL | << dnad_offset>> [ | REL_JMP] -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_SEL_ABS 0x40000000 -#define SCR_SEL_ABS_ATN 0x41000000 -#define SCR_SEL_TBL 0x42000000 -#define SCR_SEL_TBL_ATN 0x43000000 - - -#define SCR_JMP_REL 0x04000000 -#define SCR_ID(id) (((unsigned long)(id)) << 16) - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** WAIT_DISC -** dummy: <> -** -** WAIT_RESEL -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_WAIT_DISC 0x48000000 -#define SCR_WAIT_RESEL 0x50000000 - -/*----------------------------------------------------------- -** -** Bit Set / Reset -** -**----------------------------------------------------------- -** -** SET (flags {|.. }) -** -** CLR (flags {|.. }) -** -**----------------------------------------------------------- -*/ - -#define SCR_SET(f) (0x58000000 | (f)) -#define SCR_CLR(f) (0x60000000 | (f)) - -#define SCR_CARRY 0x00000400 -#define SCR_TRG 0x00000200 -#define SCR_ACK 0x00000040 -#define SCR_ATN 0x00000008 - - - - -/*----------------------------------------------------------- -** -** Memory to memory move -** -**----------------------------------------------------------- -** -** COPY (bytecount) -** << source_address >> -** << destination_address >> -** -** SCR_COPY sets the NO FLUSH option by default. -** SCR_COPY_F does not set this option. -** -** For chips which do not support this option, -** ncr_copy_and_bind() will remove this bit. -**----------------------------------------------------------- -*/ - -#define SCR_NO_FLUSH 0x01000000 - -#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) -#define SCR_COPY_F(n) (0xc0000000 | (n)) - -/*----------------------------------------------------------- -** -** Register move and binary operations -** -**----------------------------------------------------------- -** -** SFBR_REG (reg, op, data) reg = SFBR op data -** << 0 >> -** -** REG_SFBR (reg, op, data) SFBR = reg op data -** << 0 >> -** -** REG_REG (reg, op, data) reg = reg op data -** << 0 >> -** -**----------------------------------------------------------- -** On 810A, 860, 825A, 875, 895 and 896 chips the content -** of SFBR register can be used as data (SCR_SFBR_DATA). -** The 896 has additionnal IO registers starting at -** offset 0x80. Bit 7 of register offset is stored in -** bit 7 of the SCRIPTS instruction first DWORD. -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ - -#define SCR_SFBR_REG(reg,op,data) \ - (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_SFBR(reg,op,data) \ - (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_REG(reg,op,data) \ - (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - - -#define SCR_LOAD 0x00000000 -#define SCR_SHL 0x01000000 -#define SCR_OR 0x02000000 -#define SCR_XOR 0x03000000 -#define SCR_AND 0x04000000 -#define SCR_SHR 0x05000000 -#define SCR_ADD 0x06000000 -#define SCR_ADDC 0x07000000 - -#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ - -/*----------------------------------------------------------- -** -** FROM_REG (reg) SFBR = reg -** << 0 >> -** -** TO_REG (reg) reg = SFBR -** << 0 >> -** -** LOAD_REG (reg, data) reg = -** << 0 >> -** -** LOAD_SFBR(data) SFBR = -** << 0 >> -** -**----------------------------------------------------------- -*/ - -#define SCR_FROM_REG(reg) \ - SCR_REG_SFBR(reg,SCR_OR,0) - -#define SCR_TO_REG(reg) \ - SCR_SFBR_REG(reg,SCR_OR,0) - -#define SCR_LOAD_REG(reg,data) \ - SCR_REG_REG(reg,SCR_LOAD,data) - -#define SCR_LOAD_SFBR(data) \ - (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) - -/*----------------------------------------------------------- -** -** LOAD from memory to register. -** STORE from register to memory. -** -** Only supported by 810A, 860, 825A, 875, 895 and 896. -** -**----------------------------------------------------------- -** -** LOAD_ABS (LEN) -** <> -** -** LOAD_REL (LEN) (DSA relative) -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) -#define SCR_NO_FLUSH2 0x02000000 -#define SCR_DSA_REL2 0x10000000 - -#define SCR_LOAD_R(reg, how, n) \ - (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_STORE_R(reg, how, n) \ - (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) -#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) -#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) -#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) - -#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) -#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) -#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) -#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) - - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** JUMP [ | IFTRUE/IFFALSE ( ... ) ] -** <
> -** -** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** CALL [ | IFTRUE/IFFALSE ( ... ) ] -** <
> -** -** CALLR [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** RETURN [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** INT [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** Conditions: -** WHEN (phase) -** IF (phase) -** CARRYSET -** DATA (data, mask) -** -**----------------------------------------------------------- -*/ - -#define SCR_NO_OP 0x80000000 -#define SCR_JUMP 0x80080000 -#define SCR_JUMP64 0x80480000 -#define SCR_JUMPR 0x80880000 -#define SCR_CALL 0x88080000 -#define SCR_CALLR 0x88880000 -#define SCR_RETURN 0x90080000 -#define SCR_INT 0x98080000 -#define SCR_INT_FLY 0x98180000 - -#define IFFALSE(arg) (0x00080000 | (arg)) -#define IFTRUE(arg) (0x00000000 | (arg)) - -#define WHEN(phase) (0x00030000 | (phase)) -#define IF(phase) (0x00020000 | (phase)) - -#define DATA(D) (0x00040000 | ((D) & 0xff)) -#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) - -#define CARRYSET (0x00200000) - - - -#define SIR_COMPLETE 0x10000000 -/* script errors */ -#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 -#define SIR_CMD_OUT_ILL_PH 0x00000002 -#define SIR_STATUS_ILL_PH 0x00000003 -#define SIR_MSG_RECEIVED 0x00000004 -#define SIR_DATA_IN_ERR 0x00000005 -#define SIR_DATA_OUT_ERR 0x00000006 -#define SIR_SCRIPT_ERROR 0x00000007 -#define SIR_MSG_OUT_NO_CMD 0x00000008 -#define SIR_MSG_OVER7 0x00000009 -/* Fly interrupt */ -#define INT_ON_FY 0x00000080 -/* Hardware errors are defined in scsi.h */ - -#define SCSI_IDENTIFY 0xC0 - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 3796ad4..4be57ca 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -72,10 +72,8 @@ */ #include +#include -#ifdef CONFIG_4xx -#include <405gp_pci.h> -#endif #ifdef CONFIG_USB_UHCI #include @@ -95,7 +93,7 @@ static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */ -unsigned long usb_base_addr; /* base address */ +unsigned int usb_base_addr; /* base address */ static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */ static uhci_qh_t qh_cntrl; /* control Queue Head */ @@ -588,20 +586,21 @@ void handle_usb_interrupt(void) */ int usb_lowlevel_init(void) { - unsigned long temp; + unsigned char temp; int busdevfunc; - busdevfunc=PCI_Find_Device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); /* get PCI Device ID */ + busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ if(busdevfunc==-1) { printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); return -1; } - irqvec=PCI_Read_CFG_Reg(busdevfunc,PCI_CFG_DEV_INT_LINE,1); + pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp); + irqvec = temp; irq_free_handler(irqvec); USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec); - temp=PCI_Read_CFG_Reg(busdevfunc,PCI_CFG_DEV_INT_PIN,1); + pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp); USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp); - usb_base_addr=PCI_Read_CFG_Reg(busdevfunc,PCI_CFG_BASE_ADDRESS_4,4); + pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); usb_base_addr&=0xFFFFFFF0; usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; diff --git a/board/mpl/common/video.c b/board/mpl/common/video.c index c2672ad..6b61548 100644 --- a/board/mpl/common/video.c +++ b/board/mpl/common/video.c @@ -33,9 +33,7 @@ #include #include #include "video.h" -#ifdef CONFIG_4xx -#include <405gp_pci.h> -#endif +#include #include "vga_table.h" @@ -103,7 +101,7 @@ static int video_row; static int video_col; static unsigned char video_attr; -static unsigned long font_base_addr; +static unsigned int font_base_addr; /********************************************************************** * some forward declerations... */ @@ -129,7 +127,7 @@ int drv_video_init(void) device_t vgadev ; int busdevfunc; - busdevfunc=PCI_Find_Device(VIDEO_VEND_ID,VIDEO_DEV_ID); /* get PCI Device ID */ + busdevfunc=pci_find_device(VIDEO_VEND_ID,VIDEO_DEV_ID,0); /* get PCI Device ID */ if(busdevfunc==-1) { printf("Error VGA Controller (%04X,%04X) not found\n",VIDEO_VEND_ID,VIDEO_DEV_ID); return -1; @@ -157,7 +155,7 @@ int drv_video_init(void) int video_init(int busdevfunc) { - font_base_addr = PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_BASE_ADDRESS_0, 4); + pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_0, &font_base_addr); video_fb = (char*)font_base_addr; /* we look into the big linaer memory area */ diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 1e6d57a..62b3385 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -28,7 +28,7 @@ LIB = lib$(BOARD).a OBJS = $(BOARD).o \ ../common/flash.o cmd_pip405.o ../common/pci.o \ ../common/isa.o ../common/kbd.o ../common/video.o \ - ../common/sym53c8xx.o ../common/usb_uhci.o \ + ../common/usb_uhci.o \ ../common/memtst.o ../common/common_util.o SOBJS = init.o diff --git a/board/musenki/Makefile b/board/musenki/Makefile index 3d890bd..2613292 100644 --- a/board/musenki/Makefile +++ b/board/musenki/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ns16550.o serial.o dc2114x.o +OBJS = $(BOARD).o flash.o SOBJS = $(LIB): .depend $(OBJS) $(SOBJS) diff --git a/board/musenki/dc2114x.c b/board/musenki/dc2114x.c deleted file mode 100644 index 7448b18..0000000 --- a/board/musenki/dc2114x.c +++ /dev/null @@ -1,615 +0,0 @@ -#include -#include -#include - - /* PCI Registers. - */ -#define PCI_VENDOR_ID 0x00 -#define PCI_COMMAND 0x04 -#define PCI_CLASS_REVISION 0x08 -#define PCI_LATENCY_TIMER 0x0d -#define PCI_BASE_ADDRESS_0 0x10 -#define PCI_CFDA_PSM 0x43 - -#define PCI_COMMAND_IO 0x1 -#define PCI_COMMAND_MASTER 0x4 - -#define CFRV_RN 0x000000f0 /* Revision Number */ -#define CBIO_MASK -128 - -#define WAKEUP 0x00 /* Power Saving Wakeup */ -#define SLEEP 0x80 /* Power Saving Sleep Mode */ - - -#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ -#define DC2114x_DID 0x1900 /* Unique Device ID # */ -#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -#define DC21142 (DC2114x_DID | 0x0010) -#define DC21143 (DC2114x_DID | 0x0030) - -#define DAVICOM_VID 0x1282 /* DC2114[23] Manufacturer */ -#define DAVICOM_DID 0x9102 /* Unique Device ID # */ - -#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) -#define is_DAVICOM ((vendor == DAVICOM_VID) && (device == DAVICOM_DID)) - - - /* Ethernet chip registers. - */ -#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */ -#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */ -#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */ -#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */ -#define DE4X5_STS iobase + 0x028 /* Status Register */ -#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */ -#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */ -#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */ - - /* Register bits. - */ -#define BMR_SWR 0x00000001 /* Software Reset */ -#define STS_TS 0x00700000 /* Transmit Process State */ -#define STS_RS 0x000e0000 /* Receive Process State */ -#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -#define OMR_SR 0x00000002 /* Start/Stop Receive */ -#define OMR_PS 0x00040000 /* Port Select */ -#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ -#define OMR_PM 0x00000080 /* Pass All Multicast */ - - /* Descriptor bits. - */ -#define R_OWN 0x80000000 /* Own Bit */ -#define RD_RER 0x02000000 /* Receive End Of Ring */ -#define RD_LS 0x00000100 /* Last Descriptor */ -#define RD_ES 0x00008000 /* Error Summary */ -#define TD_TER 0x02000000 /* Transmit End Of Ring */ -#define T_OWN 0x80000000 /* Own Bit */ -#define TD_LS 0x40000000 /* Last Segment */ -#define TD_FS 0x20000000 /* First Segment */ -#define TD_ES 0x00008000 /* Error Summary */ -#define TD_SET 0x08000000 /* Setup Packet */ - - -#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ -#define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define SROM_SR 0x00000800 /* Select Serial ROM when set */ - -#define DT_IN 0x00000004 /* Serial Data In */ -#define DT_CLK 0x00000002 /* Serial ROM Clock */ -#define DT_CS 0x00000001 /* Serial ROM Chip Select */ - -#define POLL_DEMAND 1 - -#define RESET_DE4X5 {\ - int i;\ - i=inl(DE4X5_BMR);\ - udelay(1000);\ - outl(i | BMR_SWR, DE4X5_BMR);\ - udelay(1000);\ - outl(i, DE4X5_BMR);\ - udelay(1000);\ - for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\ - udelay(1000);\ -} - -#define START_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr |= OMR_ST | OMR_SR;\ - outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ -} - -#define STOP_DE4X5 {\ - s32 omr; \ - omr = inl(DE4X5_OMR);\ - omr &= ~(OMR_ST|OMR_SR);\ - outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ -} - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ -#define RX_BUFF_SZ PKTSIZE_ALIGN - -#define TOUT_LOOP 1000000 - -#define SETUP_FRAME_LEN 192 -#define ETH_ALEN 6 - - -struct de4x5_desc { - volatile s32 status; - u32 des1; - u32 buf; - u32 next; -}; - - -static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_new; /* RX descriptor ring pointer */ -static int tx_new; /* TX descriptor ring pointer */ - -static char rxRingSize; -static char txRingSize; - -static u_long iobase; - -static void send_setup_frame(bd_t * bis); -static void check_hw_addr(bd_t * bis); -static short srom_rd(u_long address, u_char offset); -static void srom_latch(u_int command, u_long address); -static void srom_command(u_int command, u_long address); -static void srom_address(u_int command, u_long address, u_char offset); -static short srom_data(u_int command, u_long address); -static void sendto_srom(u_int command, u_long addr); -static int getfrom_srom(u_long addr); - -static inline int inl(u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr + 0xfe000000)); -} - -static inline void outl (int command, u_long addr) -{ - *(volatile u_long *)(addr + 0xfe000000) = cpu_to_le32(command); -} - -int eth_init(bd_t *bis) -{ - int i, status = 0; - int vendor, device, l; - int cfrv; - unsigned char timer; - - - CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, l); - - l >>= 8; - - if (l != 0x00020000) - { - printf("Error: Can not find an ethernet card on the PCI bus %d " - "in slot %d\n", CFG_ETH_DEV_FN >> 16, - (CFG_ETH_DEV_FN & 0xFFFF) >> 11); - goto Done; - } - - CONFIG_READ_WORD(0x80000000 | PCI_VENDOR_ID | CFG_ETH_DEV_FN, vendor); - - device = (vendor >> 16) & 0xffff; - vendor = vendor & 0xffff; - device = device << 8; - - if (!(is_DAVICOM)) - { - printf("Error: The chip is not DAVICOM.\n"); - goto Done; - } - - /* Get the chip configuration revision register. - */ - CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, - cfrv); - - device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); - - if (device != 0x9102) - { - printf("Error: The chip is not a DM92102F.\n"); - goto Done; - } - - /* Check if I/O accesses and Bus Mastering are enabled. - */ - CONFIG_READ_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, status); - - if (!(status & PCI_COMMAND_IO)) - { - status |= PCI_COMMAND_IO; - CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - } - - if (!(status & PCI_COMMAND_IO)) - { - printf("Error: Can not enable I/O access.\n"); - goto Done; - } - - if (!(status & PCI_COMMAND_MASTER)) - { - status |= PCI_COMMAND_MASTER; - CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, - status); - } - if (!(status & PCI_COMMAND_MASTER)) - { - printf("Error: Can not enable Bus Mastering.\n"); - goto Done; - } - - /* Check the latency timer for values >= 0x60. - */ - CONFIG_READ_BYTE(0x80000000 | PCI_LATENCY_TIMER | CFG_ETH_DEV_FN, - timer); - if (timer < 0x60) - { - CONFIG_WRITE_BYTE(0x80000000 | PCI_LATENCY_TIMER | - CFG_ETH_DEV_FN, - 0X60); - } - - /* Set I/O base register. - */ - CONFIG_WRITE_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN, - CFG_ETH_IOBASE); - - CONFIG_READ_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN, - iobase); - - if (iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - goto Done; - } - - iobase &= CBIO_MASK; - - /* Ensure we're not sleeping. - */ - CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, WAKEUP); - - udelay(10 * 1000); - - check_hw_addr(bis); - - RESET_DE4X5; - - if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; - } - - outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); - - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].status = cpu_to_le32(R_OWN); - rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32((u_long)NetRxPackets[i]); - rx_ring[i].next = 0; - } - - for (i=0; i < NUM_TX_DESC; i++) - { - tx_ring[i].status = 0; - tx_ring[i].des1 = 0; - tx_ring[i].buf = 0; - tx_ring[i].next = 0; - } - - rxRingSize = NUM_RX_DESC; - txRingSize = NUM_TX_DESC; - - /* Write the end of list marker to the descriptor lists. - */ - rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); - tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); - - /* Tell the adapter where the TX/RX rings are located. - */ - outl((u_long)&rx_ring, DE4X5_RRBA); - outl((u_long)&tx_ring, DE4X5_TRBA); - - START_DE4X5; - - tx_new = 0; - rx_new = 0; - - send_setup_frame(bis); - -Done: - - return 0; -} - -int eth_send(volatile void *packet, int length) -{ - int status = 0; - int i; - - if (length <= 0) - { - printf("eth: bad packet size: %d\n", length); - goto out; - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)packet); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - - if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) - { -#if 0 - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); -#endif - status++; - } - - out: - return status; -} - -int eth_rx(void) -{ - s32 status; - int length = 0; - - for ( ; ; ) - { - status = (s32)le32_to_cpu(rx_ring[rx_new].status); - - if (status & R_OWN) - { - break; - } - - if (status & RD_LS) - { - /* Valid frame status. - */ - if (status & RD_ES) - { - /* There was an error. - */ - printf("RX error status = 0x%08X\n", status); - } - else - { - /* A valid frame received. - */ - length = (le32_to_cpu(rx_ring[rx_new].status) >> - 16); - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(NetRxPackets[rx_new], length - 4); - } - - /* Change buffer ownership for this frame, back - * to the adapter. - */ - rx_ring[rx_new].status = cpu_to_le32(R_OWN); - } - - /* Update entry information. - */ - rx_new = (rx_new + 1) % rxRingSize; - } - - return length; -} - -void eth_halt(void) -{ - if (iobase != CFG_ETH_IOBASE) { - /* Ethernet has not been initialized yet. */ - return; - } - - STOP_DE4X5; - outl(0, DE4X5_SICR); - CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, SLEEP); -} - -static void check_hw_addr(bd_t *bis) -{ - unsigned char hw_addr[ETH_ALEN]; - u_short tmp, *p = (short *)(&hw_addr[0]); - int i, j = 0; - - for (i = 0; i < (ETH_ALEN >> 1); i++) - { - tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if ((j == 0) || (j == 0x2fffd)) - { - printf("Warning: can't read HW address from SROM.\n"); - goto Done; - } - - for (i = 0; i < ETH_ALEN; i++) - { - if (hw_addr[i] != bis->bi_enetaddr[i]) - { - printf("Warning: HW addresses don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - goto Done; - } - } - -Done: - return; -} - -static void send_setup_frame(bd_t *bis) -{ - int i; - char setup_frame[SETUP_FRAME_LEN]; - char * pa = &setup_frame[0]; - - memset(pa, 0xff, SETUP_FRAME_LEN); - - for (i = 0; i < ETH_ALEN; i++) - { - *(pa + (i & 1)) = bis->bi_enetaddr[i]; - if (i & 0x01) - { - pa += 4; - } - } - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx error buffer not ready\n"); - goto out; - } - } - - tx_ring[tx_new].buf = cpu_to_le32((u_long)&setup_frame[0]); - tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); - tx_ring[tx_new].status = cpu_to_le32(T_OWN); - - outl(POLL_DEMAND, DE4X5_TPD); - - for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: tx buffer not ready\n"); - goto out; - } - } - -#if 0 - if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) - { - printf("TX error status = 0x%08X\n", - le32_to_cpu(tx_ring[tx_new].status)); - } -#endif -out: - return; -} - - /* SROM Read. - */ -static short -srom_rd(u_long addr, u_char offset) -{ - sendto_srom(SROM_RD | SROM_SR, addr); - - srom_latch(SROM_RD | SROM_SR | DT_CS, addr); - srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data(SROM_RD | SROM_SR | DT_CS, addr); -} - -static void -srom_latch(u_int command, u_long addr) -{ - sendto_srom(command, addr); - sendto_srom(command | DT_CLK, addr); - sendto_srom(command, addr); - - return; -} - -static void -srom_command(u_int command, u_long addr) -{ - srom_latch(command, addr); - srom_latch(command, addr); - srom_latch((command & 0x0000ff00) | DT_CS, addr); - - return; -} - -static void -srom_address(u_int command, u_long addr, u_char offset) -{ - int i; - signed char a; - - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) { - srom_latch(command | ((a < 0) ? DT_IN : 0), addr); - } - udelay(1); - - i = (getfrom_srom(addr) >> 3) & 0x01; - - return; -} - -static short -srom_data(u_int command, u_long addr) -{ - int i; - short word = 0; - s32 tmp; - - for (i=0; i<16; i++) { - sendto_srom(command | DT_CLK, addr); - tmp = getfrom_srom(addr); - sendto_srom(command, addr); - - word = (word << 1) | ((tmp >> 3) & 0x01); - } - - sendto_srom(command & 0x0000ff00, addr); - - return word; -} - -static void -sendto_srom(u_int command, u_long addr) -{ - outl(command, addr); - udelay(1); - - return; -} - -static int -getfrom_srom(u_long addr) -{ - s32 tmp; - - tmp = inl(addr); - udelay(1); - - return tmp; -} - diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c index 74cf6af..eb5e794 100644 --- a/board/musenki/musenki.c +++ b/board/musenki/musenki.c @@ -23,6 +23,7 @@ #include #include +#include int checkboard (void) { @@ -95,11 +96,37 @@ Done: } /* - * Initialize PCI Devices, report devices found. + * Initialize PCI Devices */ -void pci_init (bd_t * dummy) -{ - extern int pci_dev_init (int busNo); +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { +#if 0 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + 0x0, 0x0, 0x0, /* unknown eth0 divice */ + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + 0x0, 0x0, 0x0, /* unknown eth1 device */ + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, +#endif + { } +}; +#endif - pci_dev_init (0); +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init(bd_t *bd) +{ + pci_mpc824x_init(bd, &hose); } diff --git a/board/musenki/ns16550.c b/board/musenki/ns16550.c deleted file mode 100644 index b05d52b..0000000 --- a/board/musenki/ns16550.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - */ - -#include -#include "ns16550.h" - -#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ -#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ -#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ - -typedef struct NS16550 *NS16550_t; - -static const NS16550_t COM_PORTS[] = { - (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), - (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) -}; - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE | LCRVAL; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCRVAL; - com_port->mcr = MCRVAL; - com_port->fcr = FCRVAL; - return (com_port); -} - -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCRVAL; - com_port->mcr = MCRVAL; - com_port->fcr = FCRVAL; -} - -void NS16550_putc (volatile struct NS16550 *com_port, char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -char NS16550_getc (volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} diff --git a/board/musenki/ns16550.h b/board/musenki/ns16550.h deleted file mode 100644 index 74fa79d..0000000 --- a/board/musenki/ns16550.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - */ - - -struct NS16550 { - char rbr; /* 0 */ - unsigned char ier; /* 1 */ - unsigned char fcr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ -}; - -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -#define FCR_FIFO_EN 0x01 /*fifo enable */ -#define FCR_RXSR 0x02 /*receiver soft reset */ -#define FCR_TXSR 0x04 /*transmitter soft reset */ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask */ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble */ -#define LCR_EPS 0x10 /* Even Parity Select */ -#define LCR_STKP 0x20 /* Stick Parity */ -#define LCR_SBRK 0x40 /* Set Break */ -#define LCR_BKSE 0x80 /* Bank select enable */ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor); -void NS16550_putc (volatile struct NS16550 *com_port, char c); -char NS16550_getc (volatile struct NS16550 *com_port); -int NS16550_tstc (volatile struct NS16550 *com_port); -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/musenki/serial.c b/board/musenki/serial.c deleted file mode 100644 index 40c6c39..0000000 --- a/board/musenki/serial.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "ns16550.h" - -#define IDATA (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET) - -/* - * Minimal serial functions needed to use onboard DUART as serial console interface. - */ - -volatile struct NS16550 *console; - -void -serial_init (unsigned long dummy, int baudrate) -{ - init_data_t * const idata = IDATA; - int clock_divisor = get_bus_freq(0) / 16 / baudrate; - idata->console_addr = (void *)NS16550_init((CONFIG_CONS_INDEX - 1), clock_divisor); -} - -void -serial_putc(const char c) -{ - init_data_t * const idata = IDATA; - NS16550_putc((struct NS16550 *) idata->console_addr, c); - if(c == '\n') NS16550_putc((struct NS16550 *) idata->console_addr, '\r'); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - init_data_t * const idata = IDATA; - return NS16550_getc((struct NS16550 *) idata->console_addr); -} - -int -serial_tstc(void) -{ - init_data_t * const idata = IDATA; - return NS16550_tstc((struct NS16550 *) idata->console_addr); -} - -void -serial_setbrg (unsigned long dummy, int baudrate) -{ - init_data_t * const idata = IDATA; - const int clock_divisor = get_bus_freq(0) / 16 / baudrate; - NS16550_reinit((struct NS16550 *) idata->console_addr, clock_divisor); -} diff --git a/board/pcippc2/Makefile b/board/pcippc2/Makefile index 66d49b4..d771100 100644 --- a/board/pcippc2/Makefile +++ b/board/pcippc2/Makefile @@ -25,9 +25,9 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o eepro100.o pci.o \ - fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o sym53c8xx.o \ - dc2114x.o +COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \ + fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o + AOBJS = OBJS = $(COBJS) $(AOBJS) diff --git a/board/pcippc2/cpc710.h b/board/pcippc2/cpc710.h index 92ff5eb..cfae734 100644 --- a/board/pcippc2/cpc710.h +++ b/board/pcippc2/cpc710.h @@ -85,4 +85,8 @@ #define HW_BRIDGE_BARPS 0xf8120 #define HW_BRIDGE_PSBAR 0xf8140 +/* Configuration space registers */ +#define CPC710_BUS_NUMBER 0x40 +#define CPC710_SUB_BUS_NUMBER 0x41 + #endif diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c index 89c249e..e322cdd 100644 --- a/board/pcippc2/cpc710_pci.c +++ b/board/pcippc2/cpc710_pci.c @@ -24,39 +24,14 @@ #include #include #include - -#include "pci.h" +#include #include "hardware.h" #include "pcippc2.h" -static u32 cpc710_mapped_ram; +struct pci_controller local_hose, cpci_hose; -static inline u32 bdf_to_dev ( - u32 bdf) -{ - return (bdf >> 11) & 0x1f; -} - -static inline u32 bdf_to_bus ( - u32 bdf) -{ - return (bdf >> 16) & 0xff; -} - -static inline u32 bdf_to_func ( - u32 bdf) -{ - return (bdf >> 8) & 0x07; -} - -static inline u32 make_bdf ( - u32 bus, - u32 dev, - u32 func) -{ - return (bus << 16) | (dev << 11) | (func << 8); -} +static u32 cpc710_mapped_ram; /* Enable PCI retry timeouts */ @@ -167,7 +142,7 @@ void cpc710_pci_init (void) out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080); iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER << 16); + out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); iobarrier_rw(); /* Set bus and subbus numbers @@ -201,7 +176,7 @@ void cpc710_pci_init (void) out32(BRIDGE(CPCI, CFGADDR), 0x0c000180); iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER << 16); + out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); iobarrier_rw(); /* Write to the PSBAR */ @@ -231,203 +206,104 @@ void cpc710_pci_init (void) iobarrier_rw(); out32(BRIDGE(CPCI, CRR), 0xfc000000); iobarrier_rw(); -} - -unsigned int PCI_Read_CFG_Reg ( - int busdevfunc, - int reg, - int width) -{ - u32 bus = bdf_to_bus(busdevfunc); - u32 dev = bdf_to_dev(busdevfunc); - u32 bridge_addr = bus == 0 ? BRIDGE_LOCAL_PHYS : BRIDGE_CPCI_PHYS; - u32 ret; - - /* Drop out-of-range device numbers - */ - if (bus >= 2 || dev == 0 || dev > 21) - { - return (1 << (8 * width)) - 1; - } - - out32r(bridge_addr + HW_BRIDGE_CFGADDR, busdevfunc | (reg & 0xfc) | 0x80000000); - iobarrier_rw(); - - switch (width) - { - case 1: - ret = in8(bridge_addr + HW_BRIDGE_CFGDATA + (reg & 0x3)); - break; - case 2: - ret = in16r(bridge_addr + HW_BRIDGE_CFGDATA + (reg & 0x2)); - break; - case 4: - ret = in32r(bridge_addr + HW_BRIDGE_CFGDATA); - break; - default: - puts("Invalid PCI access !\n"); - hang(); - /* To avoid warning - */ - ret = 0xffffffff; - } - - iobarrier_rw(); - - return ret; -} - -int PCI_Write_CFG_Reg ( - int busdevfunc, - int reg, - unsigned int value, - int width) -{ - u32 bus = bdf_to_bus(busdevfunc); - u32 dev = bdf_to_dev(busdevfunc); - u32 bridge_addr = bus == 0 ? BRIDGE_LOCAL_PHYS : BRIDGE_CPCI_PHYS; - - /* Drop out-of-range device numbers - */ - if (bus >= 2 || dev == 0 || dev > 21) - { - return 0; - } - - out32r(bridge_addr + HW_BRIDGE_CFGADDR, busdevfunc | (reg & 0xfc) | 0x80000000); - iobarrier_rw(); - - switch (width) - { - case 1: - out8(bridge_addr + HW_BRIDGE_CFGDATA + (reg & 0x3), value); - break; - case 2: - out16r(bridge_addr + HW_BRIDGE_CFGDATA + (reg & 0x2), value); - break; - case 4: - out32r(bridge_addr + HW_BRIDGE_CFGDATA, value); - break; - default: - puts("Invalid PCI access !\n"); - hang(); - } - - iobarrier_rw(); - - return 0; -} - -u32 pci_phys_to_io ( - u32 p) -{ - if (p >= BRIDGE_LOCAL_IO_PHYS && - p < BRIDGE_LOCAL_IO_PHYS + BRIDGE_LOCAL_IO_SIZE) - { - return p - BRIDGE_LOCAL_IO_PHYS + BRIDGE_LOCAL_IO_BUS; - } - - if (p >= BRIDGE_CPCI_IO_PHYS && - p < BRIDGE_CPCI_IO_PHYS + BRIDGE_CPCI_IO_SIZE) - { - return p - BRIDGE_CPCI_IO_PHYS + BRIDGE_CPCI_IO_BUS; - } - - puts("Address not in the PCI I/O space !\n"); - hang(); - - return 0; -} - -u32 pci_io_to_phys ( - u32 i) -{ - if (i >= BRIDGE_LOCAL_IO_BUS && - i < BRIDGE_LOCAL_IO_BUS + BRIDGE_LOCAL_IO_SIZE) - { - return i - BRIDGE_LOCAL_IO_BUS + BRIDGE_LOCAL_IO_PHYS; - } - - if (i >= BRIDGE_CPCI_IO_BUS && - i < BRIDGE_CPCI_IO_BUS + BRIDGE_CPCI_IO_SIZE) - { - return i - BRIDGE_CPCI_IO_BUS + BRIDGE_CPCI_IO_PHYS; - } - - puts("Address not in the PCI I/O space !\n"); - hang(); - - return 0; -} - -u32 pci_phys_to_mem ( - u32 p) -{ - if (p >= BRIDGE_LOCAL_MEM_PHYS && - p < BRIDGE_LOCAL_MEM_PHYS + BRIDGE_LOCAL_MEM_SIZE) - { - return p - BRIDGE_LOCAL_MEM_PHYS + BRIDGE_LOCAL_MEM_BUS; - } - - if (p >= BRIDGE_CPCI_MEM_PHYS && - p < BRIDGE_CPCI_MEM_PHYS + BRIDGE_CPCI_MEM_SIZE) - { - return p - BRIDGE_CPCI_MEM_PHYS + BRIDGE_CPCI_MEM_BUS; - } - - puts("Address not in the PCI memory space !\n"); - hang(); - - return 0; -} - -u32 pci_mem_to_phys ( - u32 m) -{ - if (m >= BRIDGE_LOCAL_MEM_BUS && - m < BRIDGE_LOCAL_MEM_BUS + BRIDGE_LOCAL_MEM_SIZE) - { - return m - BRIDGE_LOCAL_MEM_BUS + BRIDGE_LOCAL_MEM_PHYS; - } - - if (m >= BRIDGE_CPCI_MEM_BUS && - m < BRIDGE_CPCI_MEM_BUS + BRIDGE_CPCI_MEM_SIZE) - { - return m - BRIDGE_CPCI_MEM_BUS + BRIDGE_CPCI_MEM_PHYS; - } - - puts("Address not in the PCI memory space !\n"); - hang(); - - return 0; -} - -u32 pci_ram_to_mem ( - u32 r) -{ - if (r >= PCI_MEMORY_PHYS && - r < PCI_MEMORY_PHYS + cpc710_mapped_ram) - { - return r - PCI_MEMORY_PHYS + PCI_MEMORY_BUS; - } - - puts("Address not in the RAM space !\n"); - hang(); - - return 0; -} - -u32 pci_mem_to_ram ( - u32 p) -{ - if (p >= PCI_MEMORY_BUS && - p < PCI_MEMORY_BUS + cpc710_mapped_ram) - { - return p - PCI_MEMORY_BUS + PCI_MEMORY_PHYS; - } - - puts("Address not in the PCI RAM memory space !\n"); - hang(); - return 0; + local_hose.first_busno = 0; + local_hose.last_busno = 0xff; + + /* System memory space */ + pci_set_region(local_hose.regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHYS, + PCI_MEMORY_MAXSIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(local_hose.regions + 1, + BRIDGE_LOCAL_MEM_BUS, + BRIDGE_LOCAL_MEM_PHYS, + BRIDGE_LOCAL_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(local_hose.regions + 2, + BRIDGE_LOCAL_IO_BUS, + BRIDGE_LOCAL_IO_PHYS, + BRIDGE_LOCAL_IO_SIZE, + PCI_REGION_IO); + + local_hose.region_count = 3; + + pci_setup_indirect(&local_hose, + BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR, + BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA); + + pci_register_hose(&local_hose); + + /* Initialize PCI32 bus registers */ + pci_hose_write_config_byte(&local_hose, + PCI_BDF(local_hose.first_busno,0,0), + CPC710_BUS_NUMBER, + local_hose.first_busno); + pci_hose_write_config_byte(&local_hose, + PCI_BDF(local_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + local_hose.last_busno); + + local_hose.last_busno = pci_hose_scan(&local_hose); + + /* Write out correct max subordinate bus number for local hose */ + pci_hose_write_config_byte(&local_hose, + PCI_BDF(local_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + local_hose.last_busno); + + cpci_hose.first_busno = local_hose.last_busno + 1; + cpci_hose.last_busno = 0xff; + + /* System memory space */ + pci_set_region(cpci_hose.regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHYS, + PCI_MEMORY_MAXSIZE, + PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(cpci_hose.regions + 1, + BRIDGE_CPCI_MEM_BUS, + BRIDGE_CPCI_MEM_PHYS, + BRIDGE_CPCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(cpci_hose.regions + 2, + BRIDGE_CPCI_IO_BUS, + BRIDGE_CPCI_IO_PHYS, + BRIDGE_CPCI_IO_SIZE, + PCI_REGION_IO); + + cpci_hose.region_count = 3; + + pci_setup_indirect(&cpci_hose, + BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR, + BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA); + + pci_register_hose(&cpci_hose); + + /* Initialize PCI64 bus registers */ + pci_hose_write_config_byte(&cpci_hose, + PCI_BDF(cpci_hose.first_busno,0,0), + CPC710_BUS_NUMBER, + cpci_hose.first_busno); + pci_hose_write_config_byte(&cpci_hose, + PCI_BDF(cpci_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + cpci_hose.last_busno); + + cpci_hose.last_busno = pci_hose_scan(&cpci_hose); + + /* Write out correct max subordinate bus number for cpci hose */ + pci_hose_write_config_byte(&cpci_hose, + PCI_BDF(cpci_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + cpci_hose.last_busno); } diff --git a/board/pcippc2/cpc710_pci.h b/board/pcippc2/cpc710_pci.h index 3903c4c..24d0db6 100644 --- a/board/pcippc2/cpc710_pci.h +++ b/board/pcippc2/cpc710_pci.h @@ -46,6 +46,6 @@ #define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x) -#define PCI_LATENCY_TIMER 0xff +#define PCI_LATENCY_TIMER_VAL 0xff #endif diff --git a/board/pcippc2/pci.c b/board/pcippc2/pci.c deleted file mode 100644 index 4d63dbb..0000000 --- a/board/pcippc2/pci.c +++ /dev/null @@ -1,767 +0,0 @@ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI routines - */ - -#include -#include -#include -#include - -#include "pci.h" -#include "hardware.h" - -#undef DEBUG - -/* - * These are the lowest addresses allowed for PCI configuration. - * They correspond to lowest available I/O and Memory addresses. - * In the case where where multiple PMM regs are being used to map - * different PLB to PCI regions, each region should have it's own - * minimum address. - */ -unsigned long LowestMemBase, LowestMemAddr; -unsigned long LowestIOBase, LowestIOAddr; - -unsigned long MaxBusNum = 0; - -unsigned char ShortPCIListing = 0; - -/* - * Subroutine: PCI_Scan - * - * Description: Scan through all allowable PCI IDs and configure - * those for which the vendor ID indicates there is a - * device present. Routine scans only function 0. - * - * Inputs: BusNum Bus number where scanning begins - * - * Return: Number of devices found on the bus. - * - */ -int PCI_Scan(int BusNum) -{ - int Device; - int Function; - int BusDevFunc; - int Found = 0; - unsigned int HeaderType = 0; - unsigned int VendorID = 0; - -#ifdef DEBUG - printf("Scanning PCI bus %d\n", BusNum); -#endif - - /* - * Start with device 0 - */ - for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { - HeaderType = 0; - VendorID = 0; - for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { - /* - * If this is not a multi-function device, we skip the rest - */ - if (Function && !(HeaderType & 0x80)) - break; - - BusDevFunc = (BusNum << 16) | - (Device << 11) | - (Function << 8); - - VendorID = PCI_Read_CFG_Reg (BusDevFunc, - PCI_CFG_VENDOR_ID, 2); - if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) - continue; - - HeaderType = PCI_Read_CFG_Reg(BusDevFunc, - PCI_CFG_HEADER_TYPE, 1); -#ifdef DEBUG - printf("\nPCI Device %d Function %d is present\n", - Device, Function); -#endif - if (HeaderType & 0x01) { - /* PCI-PCI Bridge */ - PCI_Config_Bridge(BusDevFunc); - } else { - PCI_Config_Device(BusDevFunc, 6); - } - Found++; - } - } - return Found; -} - -/* - * Subroutine: PCI_Scan_Controller - * - * Description: Scan through all allowable PCI Buses on the controller - * and configure those devices. - * - * Inputs: BusNum Bus number where scanning begins - * lIOAddr Lower I/O and Memory addressed for - * lMemAddr PCI configuration - * - * Return: Number of busses found on the controller. - * - */ -int PCI_Scan_Controller(int BusNum, unsigned long lMemAddr, unsigned long lIOAddr) -{ -#ifdef DEBUG - printf("Scanning PCI Controller start (bus#%d mem:%lx io:%lx)\n", - BusNum, lMemAddr, lIOAddr); -#endif - - MaxBusNum = BusNum; - LowestMemBase = LowestMemAddr = lMemAddr; - LowestIOBase = LowestIOAddr = lIOAddr; - - PCI_Scan(BusNum); - -#ifdef DEBUG - printf("Scanning PCI Controller finish (bus#%ld mem:%lx io:%lx)\n", - MaxBusNum, LowestMemAddr, LowestIOAddr); -#endif - - return MaxBusNum - BusNum + 1; -} - -/* - * Subroutine: PCI_Config_Device - * - * Description: Configure a PCI device by examining its I/O and memory - * address space needs and allocating address space to it by - * programming the address decoders in the Base Address Registers. - * - * Inputs: BusDevFunc Bus+Device+Function number - * NumBaseAddr Number of base address registers to - * configure - * - * Return: None - * - */ -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) -{ - int AddrSlot, i; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val; - - unsigned long pcicmd; - pcicmd = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - PCI_Write_CFG_Reg (BusDevFunc, PCI_CFG_COMMAND, - pcicmd & ~(PCI_CMD_MEMEN|PCI_CMD_IOEN), 2); - - for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) { - /* - * Write virtual address into register to check LSB. - * LSB == 1 => IO space, else memory space. - */ - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - 0xFFFFFFFF, 4); - - AddrDesc = PCI_Read_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - 4); - - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; /* 01/04/99 MCG */ - -#ifdef DEBUG - printf ("Read Base Addr Reg %d = 0x%08lx\n", - AddrSlot, AddrDesc); -#endif - - if ((AddrDesc & 1) == 1) { /* I/O space */ - AddrDesc &= 0xFFFFFFFC; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; -#ifdef DEBUG - printf(" PCI I/O space = 0x%lx bytes\n", AddrDesc); -#endif - for (AddrProg = LowestIOBase; - AddrProg < LowestIOAddr; - AddrProg += AddrDesc) { - ; /* empty */ - } - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - AddrProg, 4); -#ifdef DEBUG - printf(" PCI I/O addr = 0x%lx\n", AddrProg); -#endif - LowestIOAddr = AddrProg + AddrDesc; - } else { /* memory space */ - AddrDesc &= 0xFFFFFFF0; - - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; - - if ((unsigned long)AddrDesc < 4096) - AddrDesc = 4096; -#ifdef DEBUG - printf(" PCI memory space = 0x%lx bytes \n",AddrDesc); -#endif - for (AddrProg = LowestMemBase; - AddrProg < LowestMemAddr; - AddrProg += AddrDesc) { - ; /* empty */ - } - - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - AddrProg, 4); -#ifdef DEBUG - printf(" PCI memory addr = 0x%lx\n", AddrProg); -#endif - LowestMemAddr = AddrProg + AddrDesc; - - /* Check 64 bit BAR */ - if ((PCI_Read_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - 4) & 0x6 ) == 0x4) { - AddrSlot++; - PCI_Write_CFG_Reg (BusDevFunc, - PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), - 0x0, 4); - } - } - } - - /* - * Assign expansion ROM address - */ - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 0xFFFFFFFE, 4); - - AddrDesc = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - - if (AddrDesc != 0) { -#ifdef DEBUG - printf("Read Expansion ROM Addr Reg = 0x%08lx\n" , AddrDesc); -#endif - for (i = 0; (AddrDesc & 1) != 1; i++) - AddrDesc = AddrDesc >> 1; - - AddrDesc = 1 << i; -#ifdef DEBUG - printf(" PCI Expansion ROM space = 0x%lx bytes\n", AddrDesc); -#endif - for (AddrProg = LowestMemBase; - AddrProg < LowestMemAddr; - AddrProg += AddrDesc) { - ; /* empty */ - } - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, AddrProg, 4); -#ifdef DEBUG - printf(" PCI Expansion ROM addr = 0x%lx\n", AddrProg); -#endif - LowestMemAddr = AddrProg + AddrDesc; - } - - Min_Gnt_Val = 0x80; - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, Min_Gnt_Val, 1); - - /* - * Disable interrupt line, if device says it wants to use interrupts - */ - if (PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1) != 0) - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 0xFF, 1); - /* - * Enable i/o space and memory space on this device - */ - PCI_Write_CFG_Reg (BusDevFunc, PCI_CFG_COMMAND, - pcicmd | PCI_CMD_MEMEN | PCI_CMD_IOEN, 2); -} - -/* - * Subroutine: PCI_Config_Bridge - * - * Description: Configure a PCI-PCI bridge - * - * Inputs: BusDevFunc Bus+Device+Function number - * - * Return: None - * - */ -void PCI_Config_Bridge(int BusDevFunc) -{ - int SecondaryBus; - int PrimaryBus; - int CommandReg_Val; - int InitialLowestIOAddr, InitialLowestMemAddr; - int IOBase, MemBase; - int IOLimit, MemLimit; - - InitialLowestIOAddr = LowestIOAddr; - InitialLowestMemAddr = LowestMemAddr; - - CommandReg_Val = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - - /* Configure bridge's base address registers */ - PCI_Config_Device(BusDevFunc, 2); - - /* - * PCI_config_device() for the bridge could have changed the values in - * LowestIOAddr and LowestMemAddr, if the bridge itself uses - * I/O and/or memory space. - */ - if ( LowestIOAddr > InitialLowestIOAddr ) /* bridge uses IO space? */ - CommandReg_Val |= 0x01; /* enable I/O Space */ - - if ( LowestMemAddr > InitialLowestMemAddr ) /* bridge uses memory space? */ - CommandReg_Val |= 0x02; /* enable Memory Space */ - - PrimaryBus = (BusDevFunc >> 16) & 0xFF; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_PRIMARYBUS, PrimaryBus, 1); - - SecondaryBus = ++MaxBusNum; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SECONDARYBUS, SecondaryBus, 1); - - /* - * Start with max. possible value for subordinate bus number - * Later, after any additional child busses are found, we'll update this - */ - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, 0xFF, 1); - - /* IO Base must be on 4Kb boundary. Adjust if needed */ - if ((LowestIOAddr % 4096) != 0) - LowestIOAddr += 4096 - (LowestIOAddr % 4096); - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOBASE, - (LowestIOAddr>>8) & 0xF0, 1); - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOBASEUPPER16, - (LowestIOAddr>>16) & 0xFFFF, 2); - - IOBase = LowestIOAddr; - - /* Mem Base must be on 1 MB boundary. adjust if needed */ - if ((LowestMemAddr % 0x100000) != 0) - LowestMemAddr += 0x100000 - (LowestMemAddr % 0x100000); - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_MEMBASE, - (LowestMemAddr>>16) & 0xFFF0, 2); - MemBase = LowestMemAddr; - - /* - * secondary bus on this bridge - */ - PCI_Scan(SecondaryBus); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, MaxBusNum, 1); - - IOLimit = LowestIOAddr; - if (LowestIOAddr > IOBase) { /* IO space used on secondary bus? */ - CommandReg_Val |= 0x01; /* enable IO Space */ - IOLimit--; /* IOLimit is highest used address */ - } - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOLIMIT, - ((IOLimit)>>8) & 0xF0, 1); - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_IOLIMITUPPER16, - ((IOLimit)>>16) & 0xFFFF, 2); - - /* - * IOLIMIT is the starting address of a 4K block forwarded by the bridge. - * Round LowestIOAddr up to the next 4K boundary if IO space is enabled. - */ - if ((CommandReg_Val & 0x01) == 0x01) - LowestIOAddr = (IOLimit | 0xFFF) + 1; - - MemLimit = LowestMemAddr; - if ( LowestMemAddr > MemBase ) { /* mem. space is used on secondary bus? */ - CommandReg_Val |= 0x02; /* enable Memory Space */ - MemLimit--; /* MemLimit is highest used address */ - } - - PCI_Write_CFG_Reg (BusDevFunc, PCIPCI_MEMLIMIT, - ((MemLimit)>>16) & 0xFFF0, 2); - - /* - * MEMLIMIT is the starting address of a 1M block forwarded by the bridge. - * Round LowestMemAddr up to the next 1M boundary - * if Memory space is enabled. - */ - - if ( (CommandReg_Val & 0x02) == 0x02 ) - LowestMemAddr = (MemLimit | 0xFFFFF) + 1; - - /* Enable Bus Master on secondary bus */ - CommandReg_Val |= 0x04; - - PCI_Write_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, CommandReg_Val, 2); -} - -/* - * Subroutine: PCI_Find_Device - * - * Description: Locate a PCI device by vendor and device number on any bus. - * - * Inputs: VendorID Value of the device's Vendor ID field - * DeviceID Value of the device's Device ID field - * - * Return: < 0 Device not found - * (int) PCI Bus+Device+Function number - * - */ -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID, int Index) -{ - int Device; - int BusDevFunc; - int BusNum; - -#if CFG_SCSI_SCAN_BUS_REVERSE - for (BusNum = MaxBusNum; BusNum >= 0; BusNum--) { -#else - for (BusNum = 0; BusNum <= MaxBusNum; BusNum++) { -#endif - for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { - BusDevFunc = (BusNum << 16) | (Device << 11); - - if (PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2) == VendorID - && PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2) == DeviceID) { - - if (Index-- == 0) - return (BusDevFunc); - } - } - } - return (-1); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCI) -/* - * Follows routines for the output of infos about devices on PCI bus. - */ - -void pciinfo(int BusNum); - -/* - * Subroutine: do_pciinfo - * - * Description: Handler for 'pciinfo' command.. - * - * Inputs: argv[1] may contain the number of the bus to be scanned. - * Default is bus 0. - * - * Return: None - * - */ -void do_pciinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - char *s; - int bus_no = 0; - - if (argc == 2) - { - bus_no = (int)simple_strtoul(argv[1], NULL, 10); - } - - if ((s = getenv("pci_listing")) != NULL) - ShortPCIListing = (strcmp(s, "short") == 0) ? 1 : 0; - else - ShortPCIListing = 0; - - pciinfo(bus_no); -} - - -/* - * Subroutine: pciinfo - * - * Description: Show information about devices on PCI bus. - * Depending on the define CFG_SHORT_PCI_LISTING - * the output will be more or less exhaustive. - * - * Inputs: bus_no the number of the bus to be scanned. - * - * Return: None - * - */ -void pciinfo(int BusNum) -{ - int Device; - int Function; - unsigned int HeaderType; - unsigned int VendorID; - int BusDevFunc; - - printf("Scanning PCI devices on bus %d\n", BusNum); - - if (ShortPCIListing) { - printf("No. VendorId DeviceId Device Class Sub-Class\n"); - printf("________________________________________________________\n"); - } - - for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { - HeaderType = 0; - VendorID = 0; - for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { - /* - * If this is not a multi-function device, we skip the rest. - */ - if (Function && !(HeaderType & 0x80)) - break; - - BusDevFunc = (BusNum << 16) | - (Device << 11) | - (Function << 8); - - VendorID = PCI_Read_CFG_Reg (BusDevFunc, PCI_CFG_VENDOR_ID, 2); - if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) - continue; - - HeaderType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - - if (ShortPCIListing) - printf("%02d.%d ", Device, Function); - else - printf("\nFound PCI device %d, function %d:\n", - Device, Function); - - PCI_Header_Show(BusDevFunc); - } - } -} - - -/* - * Subroutine: PCI_Header_Show - * - * Description: Reads the header of the specified PCI device. - * - * Inputs: BusDevFunc Bus+Device+Function number - * - * Return: None - * - */ -void PCI_Header_Show(int BusDevFunc) -{ - PCI_HEADER_DEVICE headerDevice; - PCI_HEADER_BRIDGE headerBridge; - PCI_HEADER_DEVICE * pD = &headerDevice; - PCI_HEADER_BRIDGE * pB = &headerBridge; - - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - - if (pD->headerType & 0x01) { /* PCI-to-PCI bridge */ - pB->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pB->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pB->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pB->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 2); - pB->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pB->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pB->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pB->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pB->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pB->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pB->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pB->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pB->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pB->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pB->priBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRIMARY_BUS, 1); - pB->secBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SECONDARY_BUS, 1); - pB->subBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBORDINATE_BUS, 1); - pB->secLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_LATENCY, 1); - pB->ioBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE, 1); - pB->ioLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT, 1); - pB->secStatus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_STATUS, 2); - pB->memBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_BASE, 2); - pB->memLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_LIMIT, 2); - pB->preBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE, 2); - pB->preLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT, 2); - pB->preBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE_U, 4); - pB->preLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT_U, 4); - pB->ioBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE_U, 2); - pB->ioLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT_U, 2); - pB->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_ROM_BASE, 4); - pB->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_LINE, 1); - pB->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_PIN, 1); - pB->control = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRIDGE_CONTROL, 2); - PCI_Bheader_Print(pB); - } else { /* PCI device */ - pD->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pD->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pD->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pD->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 1); - pD->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pD->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pD->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pD->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pD->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pD->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pD->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pD->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pD->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pD->base2 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_2, 4); - pD->base3 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_3, 4); - pD->base4 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_4, 4); - pD->base5 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_5, 4); - pD->cis = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CIS, 4); - pD->subVendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_VENDER_ID, 2); - pD->subSystemId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_SYSTEM_ID, 2); - pD->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - pD->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 1); - pD->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1); - pD->minGrant = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MIN_GRANT, 1); - pD->maxLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MAX_LATENCY, 1); - PCI_Dheader_Print(pD); - } -} - -static char *PCI_classes[] = { - "Build before PCI Rev2.0", - "Mass storage controller", - "Network controller ", - "Display controller ", - "Multimedia device ", - "Memory controller ", - "Bridge device ", - "Simple comm. controller", - "Base system peripheral ", - "Input device ", - "Docking station ", - "Processor ", - "Serial bus controller ", - "Reserved entry ", - "Does not fit any class " -}; - -/* - * Subroutine: PCI_Dheader_Print - * - * Description: Prints the header of the specified PCI device. - * - * Inputs: pD pointer to device header info - * - * Return: None - * - */ -void PCI_Dheader_Print(PCI_HEADER_DEVICE * pD) -{ - if (ShortPCIListing) { - printf("0x%.4x 0x%.4x %s 0x%.2x\n", - (ushort)pD->vendorId, - (ushort)pD->deviceId, - PCI_classes[(uchar)pD->classCode], - (uchar)pD->subClass); - } else { - printf(" vendor ID = 0x%.4x\n", (ushort)pD->vendorId); - printf(" device ID = 0x%.4x\n", (ushort)pD->deviceId); - printf(" command register = 0x%.4x\n", (ushort)pD->command); - printf(" status register = 0x%.4x\n", (ushort)pD->status); - printf(" revision ID = 0x%.2x\n", (uchar)pD->revisionId); - printf(" class code = 0x%.2x (%s)\n", - (uchar)pD->classCode, - PCI_classes[(int)pD->classCode]); - printf(" sub class code = 0x%.2x\n", (uchar)pD->subClass); - printf(" programming interface = 0x%.2x\n", (uchar)pD->progIf); - printf(" cache line = 0x%.2x\n", (uchar)pD->cacheLine); - printf(" latency time = 0x%.2x\n", (uchar)pD->latency); - printf(" header type = 0x%.2x\n", (uchar)pD->headerType); - printf(" BIST = 0x%.2x\n", (uchar)pD->bist); - printf(" base address 0 = 0x%.8x\n", pD->base0); - printf(" base address 1 = 0x%.8x\n", pD->base1); - printf(" base address 2 = 0x%.8x\n", pD->base2); - printf(" base address 3 = 0x%.8x\n", pD->base3); - printf(" base address 4 = 0x%.8x\n", pD->base4); - printf(" base address 5 = 0x%.8x\n", pD->base5); - printf(" cardBus CIS pointer = 0x%.8x\n", pD->cis); - printf(" sub system vendor ID = 0x%.4x\n", (ushort)pD->subVendorId); - printf(" sub system ID = 0x%.4x\n", (ushort)pD->subSystemId); - printf(" expansion ROM base address = 0x%.8x\n", pD->romBase); - printf(" interrupt line = 0x%.2x\n", (uchar)pD->intLine); - printf(" interrupt pin = 0x%.2x\n", (uchar)pD->intPin); - printf(" min Grant = 0x%.2x\n", (uchar)pD->minGrant); - printf(" max Latency = 0x%.2x\n", (uchar)pD->maxLatency); - } -} - -/* - * Subroutine: PCI_Bheader_Print - * - * Description: Prints the header of the specified PCI-to-PCI bridge. - * - * Inputs: pB pointer to bridge header info - * - * Return: None - * - */ -void PCI_Bheader_Print (PCI_HEADER_BRIDGE * pB) -{ - if (ShortPCIListing) { - printf("0x%.4x 0x%.4x %s 0x%.2x\n", - (ushort)pB->vendorId, - (ushort)pB->deviceId, - PCI_classes[(uchar)pB->classCode], - (uchar)pB->subClass); - } else { - printf (" vendor ID = 0x%.4x\n", (ushort)pB->vendorId); - printf (" device ID = 0x%.4x\n", (ushort)pB->deviceId); - printf (" command register = 0x%.4x\n", (ushort)pB->command); - printf (" status register = 0x%.4x\n", (ushort)pB->status); - printf (" revision ID = 0x%.2x\n", (uchar)pB->revisionId); - printf (" class code = 0x%.2x (%s)\n", - (uchar)pB->classCode, - PCI_classes[(int)pB->classCode]); - printf (" sub class code = 0x%.2x\n", (uchar)pB->subClass); - printf (" programming interface = 0x%.2x\n", (uchar)pB->progIf); - printf (" cache line = 0x%.2x\n", (uchar)pB->cacheLine); - printf (" latency time = 0x%.2x\n", (uchar)pB->latency); - printf (" header type = 0x%.2x\n", (uchar)pB->headerType); - printf (" BIST = 0x%.2x\n", (uchar)pB->bist); - printf (" base address 0 = 0x%.8x\n", pB->base0); - printf (" base address 1 = 0x%.8x\n", pB->base1); - printf (" primary bus number = 0x%.2x\n", (uchar)pB->priBus); - printf (" secondary bus number = 0x%.2x\n", (uchar)pB->secBus); - printf (" subordinate bus number = 0x%.2x\n", (uchar)pB->subBus); - printf (" secondary latency timer = 0x%.2x\n", (uchar)pB->secLatency); - printf (" IO base = 0x%.2x\n", (uchar)pB->ioBase); - printf (" IO limit = 0x%.2x\n", (uchar)pB->ioLimit); - printf (" secondary status = 0x%.4x\n", (ushort)pB->secStatus); - printf (" memory base = 0x%.4x\n", (ushort)pB->memBase); - printf (" memory limit = 0x%.4x\n", (ushort)pB->memLimit); - printf (" prefetch memory base = 0x%.4x\n", (ushort)pB->preBase); - printf (" prefetch memory limit = 0x%.4x\n", (ushort)pB->preLimit); - printf (" prefetch memory base upper = 0x%.8x\n", pB->preBaseUpper); - printf (" prefetch memory limit upper = 0x%.8x\n", pB->preLimitUpper); - printf (" IO base upper 16 bits = 0x%.4x\n", (ushort)pB->ioBaseUpper); - printf (" IO limit upper 16 bits = 0x%.4x\n", (ushort)pB->ioLimitUpper); - printf (" expansion ROM base address = 0x%.8x\n", pB->romBase); - printf (" interrupt line = 0x%.2x\n", (uchar)pB->intLine); - printf (" interrupt pin = 0x%.2x\n", (uchar)pB->intPin); - printf (" bridge control = 0x%.4x\n", (ushort)pB->control); - } -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ diff --git a/board/pcippc2/pci.h b/board/pcippc2/pci.h deleted file mode 100644 index 0921b1f..0000000 --- a/board/pcippc2/pci.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCI_H -#define _PCI_H - -typedef struct pciHeaderDevice { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - int base2; /* base address 2 */ - int base3; /* base address 3 */ - int base4; /* base address 4 */ - int base5; /* base address 5 */ - int cis; /* cardBus CIS pointer */ - short subVendorId; /* sub system vendor ID */ - short subSystemId; /* sub system ID */ - int romBase; /* expansion ROM base address */ - int reserved0; /* reserved */ - int reserved1; /* reserved */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - char minGrant; /* min Grant */ - char maxLatency; /* max Latency */ -} PCI_HEADER_DEVICE; - -typedef struct pciHeaderBridge { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - char priBus; /* primary bus number */ - char secBus; /* secondary bus number */ - char subBus; /* subordinate bus number */ - char secLatency; /* secondary latency timer */ - char ioBase; /* IO base */ - char ioLimit; /* IO limit */ - short secStatus; /* secondary status */ - short memBase; /* memory base */ - short memLimit; /* memory limit */ - short preBase; /* prefetchable memory base */ - short preLimit; /* prefetchable memory limit */ - int preBaseUpper; /* prefetchable memory base upper 32 bits */ - int preLimitUpper; /* prefetchable memory base upper 32 bits */ - short ioBaseUpper; /* IO base upper 16 bits */ - short ioLimitUpper; /* IO limit upper 16 bits */ - int reserved; /* reserved */ - int romBase; /* expansion ROM base address */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - short control; /* bridge control */ -} PCI_HEADER_BRIDGE; - -#define PCI_CMD_MASTER 0x0004 -#define PCI_CMD_MEMEN 0x0002 -#define PCI_CMD_IOEN 0x0001 - -#define PCI_BUSNUM 0x40 -#define PCI_SUBBUSNUM 0x41 -#define PCI_DISCOUNT 0x42 - -/* - * PCI-PCI bridge header - */ -#define PCIPCI_PRIMARYBUS 0x18 -#define PCIPCI_SECONDARYBUS 0x19 -#define PCIPCI_SUBORDINATEBUS 0x1A -#define PCIPCI_SECONDARYLATENCY 0x1B -#define PCIPCI_IOBASE 0x1C -#define PCIPCI_IOLIMIT 0x1D -#define PCIPCI_SECONDARYSTATUS 0x1E -#define PCIPCI_MEMBASE 0x20 -#define PCIPCI_MEMLIMIT 0x22 -#define PCIPCI_PREFETCHMEMBASE 0x24 -#define PCIPCI_PREFETCHMEMLIMIT 0x26 -#define PCIPCI_IOBASEUPPER16 0x30 -#define PCIPCI_IOLIMITUPPER16 0x32 - -/* - * Standard device configuration register offsets - * Note that only modulo-4 addresses are written to the address register - */ -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDER_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - -/* - * PCI-to-PCI bridge configuration register offsets - * Note that only modulo-4 addresses are written to the address register - */ -#define PCI_CFG_PRIMARY_BUS 0x18 -#define PCI_CFG_SECONDARY_BUS 0x19 -#define PCI_CFG_SUBORDINATE_BUS 0x1a -#define PCI_CFG_SEC_LATENCY 0x1b -#define PCI_CFG_IO_BASE 0x1c -#define PCI_CFG_IO_LIMIT 0x1d -#define PCI_CFG_SEC_STATUS 0x1e -#define PCI_CFG_MEM_BASE 0x20 -#define PCI_CFG_MEM_LIMIT 0x22 -#define PCI_CFG_PRE_MEM_BASE 0x24 -#define PCI_CFG_PRE_MEM_LIMIT 0x26 -#define PCI_CFG_PRE_MEM_BASE_U 0x28 -#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c -#define PCI_CFG_IO_BASE_U 0x30 -#define PCI_CFG_IO_LIMIT_U 0x32 -#define PCI_CFG_ROM_BASE 0x38 -#define PCI_CFG_BRG_INT_LINE 0x3c -#define PCI_CFG_BRG_INT_PIN 0x3d -#define PCI_CFG_BRIDGE_CONTROL 0x3e - -#define PCI_MAX_PCI_DEVICES 32 -#define PCI_MAX_PCI_FUNCTIONS 8 - -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); -int PCI_Scan_Controller(int BusNum, unsigned long LowestMemAddr, unsigned long LowestIOAddr); -int PCI_Scan(int BusNum); -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_Bridge(int BusDevFunc); -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID, int Index); -void PCI_Header_Show(int BusDevFunc); -void PCI_Dheader_Print(PCI_HEADER_DEVICE * pD); -void PCI_Bheader_Print(PCI_HEADER_BRIDGE * pB); - -extern u32 pci_phys_to_io (u32 p); -extern u32 pci_io_to_phys (u32 i); -extern u32 pci_phys_to_mem (u32 p); -extern u32 pci_mem_to_phys (u32 m); -extern u32 pci_ram_to_mem (u32 r); -extern u32 pci_mem_to_ram (u32 m); - -#endif diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index b99a0a0..6019bd9 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -27,8 +27,7 @@ #include #include #include - -#include "pci.h" +#include #include "hardware.h" #include "pcippc2.h" @@ -131,11 +130,6 @@ void pci_init (bd_t * bd) { cpc710_pci_init (); -#ifdef CONFIG_PCI_PNP - PCI_Scan_Controller (0, BRIDGE_LOCAL_MEM_BUS, BRIDGE_LOCAL_IO_BUS); - PCI_Scan_Controller (1, BRIDGE_CPCI_MEM_BUS, BRIDGE_CPCI_IO_BUS); -#endif - /* FPGA requires no retry timeouts to be enabled */ cpc710_pci_enable_timeout (); diff --git a/board/pcippc2/pcippc2_fpga.c b/board/pcippc2/pcippc2_fpga.c index 5fe6294..dd961ed 100644 --- a/board/pcippc2/pcippc2_fpga.c +++ b/board/pcippc2/pcippc2_fpga.c @@ -35,8 +35,9 @@ u32 pcippc2_fpga1_phys; void pcippc2_fpga_init (void) { - u32 bdf = PCI_Find_Device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); - u32 addr; + pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); + unsigned int addr; + u16 cmd; if (bdf == -1) { @@ -44,39 +45,39 @@ void pcippc2_fpga_init (void) hang(); } - if ((PCI_Read_CFG_Reg(bdf, PCI_CFG_COMMAND, 2) & - (PCI_CMD_MEMEN | PCI_CMD_IOEN)) != (PCI_CMD_MEMEN | PCI_CMD_IOEN)) + pci_read_config_word(bdf, PCI_COMMAND, &cmd); + if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) { puts("FPGA is not configured !\n"); hang(); } - addr = PCI_Read_CFG_Reg(bdf, PCI_CFG_BASE_ADDRESS_0, 4); + pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr); if (addr & 0x1) { /* IO space */ - pcippc2_fpga0_phys = pci_io_to_phys(addr & 0xfffffffc); + pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); } else { /* Memory space */ - pcippc2_fpga0_phys = pci_mem_to_phys(addr & 0xfffffff0); + pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); } - addr = PCI_Read_CFG_Reg(bdf, PCI_CFG_BASE_ADDRESS_1, 4); + pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); if (addr & 0x1) { /* IO space */ - pcippc2_fpga1_phys = pci_io_to_phys(addr & 0xfffffffc); + pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); } else { /* Memory space */ - pcippc2_fpga1_phys = pci_mem_to_phys(addr & 0xfffffff0); + pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); } /* Interrupts are not used diff --git a/board/pcippc2/sym53c8xx.h b/board/pcippc2/sym53c8xx.h deleted file mode 100644 index 821e1f8..0000000 --- a/board/pcippc2/sym53c8xx.h +++ /dev/null @@ -1,583 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * Most of these definitions are derived from - * linux/drivers/scsi/sym53c8xx_defs.h - * - */ - -#ifndef _SYM53C8XX_DEFS_H -#define _SYM53C8XX_DEFS_H - - -#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ - -#define SCNTL1 0x01 /* no reset */ - #define ISCON 0x10 /* connected to scsi */ - #define CRST 0x08 /* force reset */ - #define IARB 0x02 /* immediate arbitration */ - -#define SCNTL2 0x02 /* no disconnect expected */ - #define SDU 0x80 /* cmd: disconnect will raise error */ - #define CHM 0x40 /* sta: chained mode */ - #define WSS 0x08 /* sta: wide scsi send [W]*/ - #define WSR 0x01 /* sta: wide scsi received [W]*/ - -#define SCNTL3 0x03 /* cnf system clock dependent */ - #define EWS 0x08 /* cmd: enable wide scsi [W]*/ - #define ULTRA 0x80 /* cmd: ULTRA enable */ - /* bits 0-2, 7 rsvd for C1010 */ - -#define SCID 0x04 /* cnf host adapter scsi address */ - #define RRE 0x40 /* r/w:e enable response to resel. */ - #define SRE 0x20 /* r/w:e enable response to select */ - -#define SXFER 0x05 /* ### Sync speed and count */ - /* bits 6-7 rsvd for C1010 */ - -#define SDID 0x06 /* ### Destination-ID */ - -#define GPREG 0x07 /* ??? IO-Pins */ - -#define SFBR 0x08 /* ### First byte in phase */ - -#define SOCL 0x09 - #define CREQ 0x80 /* r/w: SCSI-REQ */ - #define CACK 0x40 /* r/w: SCSI-ACK */ - #define CBSY 0x20 /* r/w: SCSI-BSY */ - #define CSEL 0x10 /* r/w: SCSI-SEL */ - #define CATN 0x08 /* r/w: SCSI-ATN */ - #define CMSG 0x04 /* r/w: SCSI-MSG */ - #define CC_D 0x02 /* r/w: SCSI-C_D */ - #define CI_O 0x01 /* r/w: SCSI-I_O */ - -#define SSID 0x0a - -#define SBCL 0x0b - -#define DSTAT 0x0c - #define DFE 0x80 /* sta: dma fifo empty */ - #define MDPE 0x40 /* int: master data parity error */ - #define BF 0x20 /* int: script: bus fault */ - #define ABRT 0x10 /* int: script: command aborted */ - #define SSI 0x08 /* int: script: single step */ - #define SIR 0x04 /* int: script: interrupt instruct. */ - #define IID 0x01 /* int: script: illegal instruct. */ - -#define SSTAT0 0x0d - #define ILF 0x80 /* sta: data in SIDL register lsb */ - #define ORF 0x40 /* sta: data in SODR register lsb */ - #define OLF 0x20 /* sta: data in SODL register lsb */ - #define AIP 0x10 /* sta: arbitration in progress */ - #define LOA 0x08 /* sta: arbitration lost */ - #define WOA 0x04 /* sta: arbitration won */ - #define IRST 0x02 /* sta: scsi reset signal */ - #define SDP 0x01 /* sta: scsi parity signal */ - -#define SSTAT1 0x0e - #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ - -#define SSTAT2 0x0f - #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ - #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ - #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ - #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ - #define LDSC 0x02 /* sta: disconnect & reconnect */ - -#define DSA 0x10 /* --> Base page */ -#define DSA1 0x11 -#define DSA2 0x12 -#define DSA3 0x13 - -#define ISTAT 0x14 /* --> Main Command and status */ - #define CABRT 0x80 /* cmd: abort current operation */ - #define SRST 0x40 /* mod: reset chip */ - #define SIGP 0x20 /* r/w: message from host to ncr */ - #define SEM 0x10 /* r/w: message between host + ncr */ - #define CON 0x08 /* sta: connected to scsi */ - #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ - #define SIP 0x02 /* sta: scsi-interrupt */ - #define DIP 0x01 /* sta: host/script interrupt */ - - -#define CTEST0 0x18 -#define CTEST1 0x19 -#define CTEST2 0x1a - #define CSIGP 0x40 - /* bits 0-2,7 rsvd for C1010 */ - -#define CTEST3 0x1b - #define FLF 0x08 /* cmd: flush dma fifo */ - #define CLF 0x04 /* cmd: clear dma fifo */ - #define FM 0x02 /* mod: fetch pin mode */ - #define WRIE 0x01 /* mod: write and invalidate enable */ - /* bits 4-7 rsvd for C1010 */ - -#define DFIFO 0x20 -#define CTEST4 0x21 - #define BDIS 0x80 /* mod: burst disable */ - #define MPEE 0x08 /* mod: master parity error enable */ - -#define CTEST5 0x22 - #define DFS 0x20 /* mod: dma fifo size */ - /* bits 0-1, 3-7 rsvd for C1010 */ -#define CTEST6 0x23 - -#define DBC 0x24 /* ### Byte count and command */ -#define DNAD 0x28 /* ### Next command register */ -#define DSP 0x2c /* --> Script Pointer */ -#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ - -#define SCRATCHA 0x34 /* Temporary register a */ -#define SCRATCHA1 0x35 -#define SCRATCHA2 0x36 -#define SCRATCHA3 0x37 - -#define DMODE 0x38 - #define BL_2 0x80 /* mod: burst length shift value +2 */ - #define BL_1 0x40 /* mod: burst length shift value +1 */ - #define ERL 0x08 /* mod: enable read line */ - #define ERMP 0x04 /* mod: enable read multiple */ - #define BOF 0x02 /* mod: burst op code fetch */ - #define MAN 0x01 /* mod: manual start */ - -#define DIEN 0x39 -#define SBR 0x3a - -#define DCNTL 0x3b /* --> Script execution control */ - #define CLSE 0x80 /* mod: cache line size enable */ - #define PFF 0x40 /* cmd: pre-fetch flush */ - #define PFEN 0x20 /* mod: pre-fetch enable */ - #define SSM 0x10 /* mod: single step mode */ - #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ - #define STD 0x04 /* cmd: start dma mode */ - #define IRQD 0x02 /* mod: irq disable */ - #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ - /* bits 0-1 rsvd for C1010 */ - -#define ADDER 0x3c - -#define SIEN 0x40 /* -->: interrupt enable */ -#define SIST 0x42 /* <--: interrupt status */ - #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ - #define STO 0x0400/* sta: timeout (select) */ - #define GEN 0x0200/* sta: timeout (general) */ - #define HTH 0x0100/* sta: timeout (handshake) */ - #define MA 0x80 /* sta: phase mismatch */ - #define CMP 0x40 /* sta: arbitration complete */ - #define SEL 0x20 /* sta: selected by another device */ - #define RSL 0x10 /* sta: reselected by another device*/ - #define SGE 0x08 /* sta: gross error (over/underflow)*/ - #define UDC 0x04 /* sta: unexpected disconnect */ - #define RST 0x02 /* sta: scsi bus reset detected */ - #define PAR 0x01 /* sta: scsi parity error */ - -#define SLPAR 0x44 -#define SWIDE 0x45 -#define MACNTL 0x46 -#define GPCNTL 0x47 -#define STIME0 0x48 /* cmd: timeout for select&handshake*/ -#define STIME1 0x49 /* cmd: timeout user defined */ -#define RESPID 0x4a /* sta: Reselect-IDs */ - -#define STEST0 0x4c - -#define STEST1 0x4d - #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ - #define DBLEN 0x08 /* clock doubler running */ - #define DBLSEL 0x04 /* clock doubler selected */ - - -#define STEST2 0x4e - #define ROF 0x40 /* reset scsi offset (after gross error!) */ - #define EXT 0x02 /* extended filtering */ - -#define STEST3 0x4f - #define TE 0x80 /* c: tolerAnt enable */ - #define HSC 0x20 /* c: Halt SCSI Clock */ - #define CSF 0x02 /* c: clear scsi fifo */ - -#define SIDL 0x50 /* Lowlevel: latched from scsi data */ -#define STEST4 0x52 - #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ - #define SMODE_HVD 0x40 /* High Voltage Differential */ - #define SMODE_SE 0x80 /* Single Ended */ - #define SMODE_LVD 0xc0 /* Low Voltage Differential */ - #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ - /* bits 0-5 rsvd for C1010 */ - -#define SODL 0x54 /* Lowlevel: data out to scsi data */ - -#define SBDL 0x58 /* Lowlevel: data from scsi data */ - - - - -/*----------------------------------------------------------- -** -** Utility macros for the script. -** -**----------------------------------------------------------- -*/ - -#define REG(r) (r) - -/*----------------------------------------------------------- -** -** SCSI phases -** -** DT phases illegal for ncr driver. -** -**----------------------------------------------------------- -*/ - -#define SCR_DATA_OUT 0x00000000 -#define SCR_DATA_IN 0x01000000 -#define SCR_COMMAND 0x02000000 -#define SCR_STATUS 0x03000000 -#define SCR_DT_DATA_OUT 0x04000000 -#define SCR_DT_DATA_IN 0x05000000 -#define SCR_MSG_OUT 0x06000000 -#define SCR_MSG_IN 0x07000000 - -#define SCR_ILG_OUT 0x04000000 -#define SCR_ILG_IN 0x05000000 - -/*----------------------------------------------------------- -** -** Data transfer via SCSI. -** -**----------------------------------------------------------- -** -** MOVE_ABS (LEN) -** <> -** -** MOVE_IND (LEN) -** <> -** -** MOVE_TBL -** <> -** -**----------------------------------------------------------- -*/ - -#define OPC_MOVE 0x08000000 - -#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) - -#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) -#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) -#define SCR_CHMOV_TBL (0x10000000) - - -/*----------------------------------------------------------- -** -** Selection -** -**----------------------------------------------------------- -** -** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] -** <> -** -** SEL_TBL | << dnad_offset>> [ | REL_JMP] -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_SEL_ABS 0x40000000 -#define SCR_SEL_ABS_ATN 0x41000000 -#define SCR_SEL_TBL 0x42000000 -#define SCR_SEL_TBL_ATN 0x43000000 - - -#define SCR_JMP_REL 0x04000000 -#define SCR_ID(id) (((unsigned long)(id)) << 16) - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** WAIT_DISC -** dummy: <> -** -** WAIT_RESEL -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_WAIT_DISC 0x48000000 -#define SCR_WAIT_RESEL 0x50000000 - -/*----------------------------------------------------------- -** -** Bit Set / Reset -** -**----------------------------------------------------------- -** -** SET (flags {|.. }) -** -** CLR (flags {|.. }) -** -**----------------------------------------------------------- -*/ - -#define SCR_SET(f) (0x58000000 | (f)) -#define SCR_CLR(f) (0x60000000 | (f)) - -#define SCR_CARRY 0x00000400 -#define SCR_TRG 0x00000200 -#define SCR_ACK 0x00000040 -#define SCR_ATN 0x00000008 - - - - -/*----------------------------------------------------------- -** -** Memory to memory move -** -**----------------------------------------------------------- -** -** COPY (bytecount) -** << source_address >> -** << destination_address >> -** -** SCR_COPY sets the NO FLUSH option by default. -** SCR_COPY_F does not set this option. -** -** For chips which do not support this option, -** ncr_copy_and_bind() will remove this bit. -**----------------------------------------------------------- -*/ - -#define SCR_NO_FLUSH 0x01000000 - -#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) -#define SCR_COPY_F(n) (0xc0000000 | (n)) - -/*----------------------------------------------------------- -** -** Register move and binary operations -** -**----------------------------------------------------------- -** -** SFBR_REG (reg, op, data) reg = SFBR op data -** << 0 >> -** -** REG_SFBR (reg, op, data) SFBR = reg op data -** << 0 >> -** -** REG_REG (reg, op, data) reg = reg op data -** << 0 >> -** -**----------------------------------------------------------- -** On 810A, 860, 825A, 875, 895 and 896 chips the content -** of SFBR register can be used as data (SCR_SFBR_DATA). -** The 896 has additionnal IO registers starting at -** offset 0x80. Bit 7 of register offset is stored in -** bit 7 of the SCRIPTS instruction first DWORD. -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ - -#define SCR_SFBR_REG(reg,op,data) \ - (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_SFBR(reg,op,data) \ - (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_REG(reg,op,data) \ - (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - - -#define SCR_LOAD 0x00000000 -#define SCR_SHL 0x01000000 -#define SCR_OR 0x02000000 -#define SCR_XOR 0x03000000 -#define SCR_AND 0x04000000 -#define SCR_SHR 0x05000000 -#define SCR_ADD 0x06000000 -#define SCR_ADDC 0x07000000 - -#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ - -/*----------------------------------------------------------- -** -** FROM_REG (reg) SFBR = reg -** << 0 >> -** -** TO_REG (reg) reg = SFBR -** << 0 >> -** -** LOAD_REG (reg, data) reg = -** << 0 >> -** -** LOAD_SFBR(data) SFBR = -** << 0 >> -** -**----------------------------------------------------------- -*/ - -#define SCR_FROM_REG(reg) \ - SCR_REG_SFBR(reg,SCR_OR,0) - -#define SCR_TO_REG(reg) \ - SCR_SFBR_REG(reg,SCR_OR,0) - -#define SCR_LOAD_REG(reg,data) \ - SCR_REG_REG(reg,SCR_LOAD,data) - -#define SCR_LOAD_SFBR(data) \ - (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) - -/*----------------------------------------------------------- -** -** LOAD from memory to register. -** STORE from register to memory. -** -** Only supported by 810A, 860, 825A, 875, 895 and 896. -** -**----------------------------------------------------------- -** -** LOAD_ABS (LEN) -** <> -** -** LOAD_REL (LEN) (DSA relative) -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) -#define SCR_NO_FLUSH2 0x02000000 -#define SCR_DSA_REL2 0x10000000 - -#define SCR_LOAD_R(reg, how, n) \ - (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_STORE_R(reg, how, n) \ - (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) -#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) -#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) -#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) - -#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) -#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) -#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) -#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) - - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** JUMP [ | IFTRUE/IFFALSE ( ... ) ] -** <
> -** -** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** CALL [ | IFTRUE/IFFALSE ( ... ) ] -** <
> -** -** CALLR [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** RETURN [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** INT [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** Conditions: -** WHEN (phase) -** IF (phase) -** CARRYSET -** DATA (data, mask) -** -**----------------------------------------------------------- -*/ - -#define SCR_NO_OP 0x80000000 -#define SCR_JUMP 0x80080000 -#define SCR_JUMP64 0x80480000 -#define SCR_JUMPR 0x80880000 -#define SCR_CALL 0x88080000 -#define SCR_CALLR 0x88880000 -#define SCR_RETURN 0x90080000 -#define SCR_INT 0x98080000 -#define SCR_INT_FLY 0x98180000 - -#define IFFALSE(arg) (0x00080000 | (arg)) -#define IFTRUE(arg) (0x00000000 | (arg)) - -#define WHEN(phase) (0x00030000 | (phase)) -#define IF(phase) (0x00020000 | (phase)) - -#define DATA(D) (0x00040000 | ((D) & 0xff)) -#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) - -#define CARRYSET (0x00200000) - - - -#define SIR_COMPLETE 0x10000000 -/* script errors */ -#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 -#define SIR_CMD_OUT_ILL_PH 0x00000002 -#define SIR_STATUS_ILL_PH 0x00000003 -#define SIR_MSG_RECEIVED 0x00000004 -#define SIR_DATA_IN_ERR 0x00000005 -#define SIR_DATA_OUT_ERR 0x00000006 -#define SIR_SCRIPT_ERROR 0x00000007 -#define SIR_MSG_OUT_NO_CMD 0x00000008 -#define SIR_MSG_OVER7 0x00000009 -/* Fly interrupt */ -#define INT_ON_FY 0x00000080 - -/* Hardware errors are defined in scsi.h */ - -#define SCSI_IDENTIFY 0xC0 - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile index 8285616..0a4bf0d 100644 --- a/board/sandpoint/Makefile +++ b/board/sandpoint/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ns16550.o ns87308.o serial.o \ - pci.o eepro100.o +OBJS = $(BOARD).o flash.o $(LIB): .depend $(OBJS) $(AR) crv $@ $^ diff --git a/board/sandpoint/eepro100.c b/board/sandpoint/eepro100.c deleted file mode 100644 index 950956d..0000000 --- a/board/sandpoint/eepro100.c +++ /dev/null @@ -1,680 +0,0 @@ -#include -#include -#include -#include - -#include "pci.h" - -#undef DEBUG - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_EEPRO100) - - /* Ethernet chip registers. - */ -#define SCBStatus 0 /* Rx/Command Unit Status *Word* */ -#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ -#define SCBCmd 2 /* Rx/Command Unit Command *Word* */ -#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ -#define SCBPointer 4 /* General purpose pointer. */ -#define SCBPort 8 /* Misc. commands and operands. */ -#define SCBflash 12 /* Flash memory control. */ -#define SCBeeprom 14 /* EEPROM memory control. */ -#define SCBCtrlMDI 16 /* MDI interface control. */ -#define SCBEarlyRx 20 /* Early receive byte count. */ -#define SCBGenControl 28 /* 82559 General Control Register */ -#define SCBGenStatus 29 /* 82559 General Status register */ - - /* 82559 SCB status word defnitions - */ -#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ -#define SCB_STATUS_FR 0x4000 /* frame received */ -#define SCB_STATUS_CNA 0x2000 /* CU left active state */ -#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ -#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ -#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ -#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ - -#define SCB_INTACK_MASK 0xFD00 /* all the above */ - -#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) -#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) - - /* System control block commands - */ -/* CU Commands */ -#define CU_NOP 0x0000 -#define CU_START 0x0010 -#define CU_RESUME 0x0020 -#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ -#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ -#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ -#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ - -/* RUC Commands */ -#define RUC_NOP 0x0000 -#define RUC_START 0x0001 -#define RUC_RESUME 0x0002 -#define RUC_ABORT 0x0004 -#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ -#define RUC_RESUMENR 0x0007 - -#define CU_CMD_MASK 0x00f0 -#define RU_CMD_MASK 0x0007 - -#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ -#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ - -#define CU_STATUS_MASK 0x00C0 -#define RU_STATUS_MASK 0x003C - -#define RU_STATUS_IDLE (0<<2) -#define RU_STATUS_SUS (1<<2) -#define RU_STATUS_NORES (2<<2) -#define RU_STATUS_READY (4<<2) -#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) -#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) -#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) - - /* 82559 Port interface commands. - */ -#define I82559_RESET 0x00000000 /* Software reset */ -#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ -#define I82559_SELECTIVE_RESET 0x00000002 -#define I82559_DUMP 0x00000003 -#define I82559_DUMP_WAKEUP 0x00000007 - - /* 82559 Eeprom interface. - */ -#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ -#define EE_CS 0x02 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ -#define EE_WRITE_0 0x01 -#define EE_WRITE_1 0x05 -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ -#define EE_ENB (0x4800 | EE_CS) - - /* The EEPROM commands include the alway-set leading bit. - */ -#define EE_WRITE_CMD (5 << addr_len) -#define EE_READ_CMD (6 << addr_len) -#define EE_ERASE_CMD (7 << addr_len) - - /* Receive frame descriptors. - */ -struct RxFD { - volatile u16 status; - volatile u16 control; - volatile u32 link; /* struct RxFD * */ - volatile u32 rx_buf_addr; /* void * */ - volatile u32 count; - volatile u8 data[PKTSIZE_ALIGN]; -}; - -#define RFD_STATUS_C 0x8000 /* completion of received frame */ -#define RFD_STATUS_OK 0x2000 /* frame received with no errors */ - -#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ -#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ -#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ -#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ - -#define RFD_COUNT_MASK 0x3fff -#define RFD_COUNT_F 0x4000 -#define RFD_COUNT_EOF 0x8000 - -#define RFD_RX_CRC 0x0800 /* crc error */ -#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ -#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ -#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ -#define RFD_RX_SHORT 0x0080 /* short frame error */ -#define RFD_RX_LENGTH 0x0020 -#define RFD_RX_ERROR 0x0010 /* receive error */ -#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ -#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ -#define RFD_RX_TCO 0x0001 /* TCO indication */ - - /* Transmit frame descriptors - */ -struct TxFD { /* Transmit frame descriptor set. */ - volatile u16 status; - volatile u16 command; - volatile u32 link; /* void * */ - volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ - volatile s32 count; - - volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ - volatile s32 tx_buf_size0; /* Length of Tx frame. */ - volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ - volatile s32 tx_buf_size1; /* Length of Tx frame. */ -}; - -#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ -#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ -#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ -#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ -#define TxCB_CMD_S 0x4000 /* suspend on completion */ -#define TxCB_CMD_EL 0x8000 /* last command block in CBL */ - -#define TxCB_COUNT_MASK 0x3fff -#define TxCB_COUNT_EOF 0x8000 - - /* The Speedo3 Rx and Tx frame/buffer descriptors. - */ -struct descriptor { /* A generic descriptor. */ - volatile u16 status; - volatile u16 command; - volatile u32 link; /* struct descriptor * */ - - unsigned char params[0]; -}; - -#define CFG_CMD_EL 0x8000 -#define CFG_CMD_SUSPEND 0x4000 -#define CFG_CMD_INT 0x2000 -#define CFG_CMD_IAS 0x0001 /* individual address setup */ -#define CFG_CMD_CONFIGURE 0x0002 /* configure */ - -#define CFG_STATUS_C 0x8000 -#define CFG_STATUS_OK 0x2000 - - /* Misc. - */ -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ - -#define TOUT_LOOP 1000000 - -#define ETH_ALEN 6 - -static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_next; /* RX descriptor ring pointer */ -static int tx_next; /* TX descriptor ring pointer */ -static int tx_threshold; - -static void init_rx_ring (void); -static void purge_tx_ring (void); - -static void read_hw_addr (struct eth_device* dev, bd_t * bis); - -static int eepro100_init (struct eth_device* dev, bd_t * bis); -static int eepro100_send (struct eth_device *dev, volatile void *packet, int length); -static int eepro100_recv (struct eth_device *dev); -static void eepro100_halt (struct eth_device* dev); - -static inline int INL (struct eth_device* dev, u_long addr) -{ - return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); -} - -static inline int INW (struct eth_device* dev, u_long addr) -{ - return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); -} - -static inline int INB (struct eth_device* dev, u_long addr) -{ - return *(volatile u8 *) (addr + dev->iobase); -} - -static inline void OUTB (struct eth_device* dev, int command, u_long addr) -{ - *(volatile u8 *) (addr + dev->iobase) = command; -} - -static inline void OUTW (struct eth_device* dev, int command, u_long addr) -{ - *(volatile u16 *) (addr + dev->iobase) = cpu_to_le16 (command); -} - -static inline void OUTL (struct eth_device* dev, int command, u_long addr) -{ - *(volatile u32 *) (addr + dev->iobase) = cpu_to_le32 (command); -} - - /* Wait for the chip get the command. - */ -static int wait_for_eepro100 (struct eth_device* dev) -{ - int i; - - for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { - if (i >= TOUT_LOOP) { - return 0; - } - } - - return 1; -} - -int eepro100_initialize (bd_t * bis) -{ - int card_number, i, status = 0; - int bus, devno, func; - struct eth_device *dev; - u_long iobase; - static int supported[] = { - PCI_DEVICE_ID_INTEL_82557, - PCI_DEVICE_ID_INTEL_82559, - -1 - }, *devid; - - for (card_number = i = 0, devid = supported; *devid != -1; devid++) - { - for (; ; i++) - { - /* Find PCI device - */ - if (pci_dev_find (PCI_VENDOR_ID_INTEL, - *devid, - i, &bus, &devno, &func) != TRUE) { - break; - } - - pci_config_inl (bus, devno, func, - PCI_CFG_BASE_ADDRESS_0, (uint32 *) & iobase); - iobase &= PCI_MEMBASE_MASK; - -#ifdef DEBUG - printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%lX" - "(bus=%d, device=%d, func=%d)\n", - iobase, bus, devno, func); -#endif - - pci_config_outl (bus, devno, func, - PCI_CFG_COMMAND, - PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE); - - /* Check if I/O accesses and Bus Mastering are enabled. - */ - pci_config_inl (bus, devno, func, PCI_CFG_COMMAND, &status); - - if (!(status & PCI_CMD_MEM_ENABLE)) { - puts ("Error: Can not enable MEM access\n"); - continue; - } - - if (!(status & PCI_CMD_MASTER_ENABLE)) { - puts ("Error: Can not enable Bus Mastering\n"); - continue; - } - - dev = (struct eth_device*) malloc(sizeof *dev); - - sprintf(dev->name, "i82559#%d", i); - dev->iobase = iobase; - dev->priv = (void*) devno; - dev->init = eepro100_init; - dev->halt = eepro100_halt; - dev->send = eepro100_send; - dev->recv = eepro100_recv; - - card_number++; - - eth_register(dev); - - /* Set the latency timer for value. - */ - pci_config_outb (bus, devno, func, - PCI_CFG_LATENCY_TIMER, PCI_LATENCY_TIMER); - - udelay (10 * 1000); - - read_hw_addr (dev, bis); - } - } - - return card_number; -} - -static int eepro100_init (struct eth_device* dev, bd_t * bis) -{ - int i, status = 0; - int tx_cur; - struct descriptor *ias_cmd; - - /* Reset the ethernet controller - */ - OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); - udelay (20); - - OUTL (dev, I82559_RESET, SCBPort); - udelay (20); - - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not reset ethernet controller\n"); - return (status); - } - OUTL (dev, 0, SCBPointer); - OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); - - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not reset ethernet controller\n"); - return (status); - } - OUTL (dev, 0, SCBPointer); - OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); - - /* Initialize Rx and Tx rings. - */ - init_rx_ring (); - purge_tx_ring (); - - /* Tell the adapter where the RX ring is located. - */ - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not reset ethernet controller\n"); - return (status); - } - - OUTL (dev, (u32) & rx_ring[rx_next], SCBPointer); - OUTW (dev, SCB_M | RUC_START, SCBCmd); - - /* Send the Individual Address Setup frame - */ - tx_cur = tx_next; - tx_next = ((tx_next + 1) % NUM_TX_DESC); - - ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; - ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); - ias_cmd->status = 0; - ias_cmd->link = cpu_to_le32 ((u32) & tx_ring[tx_next]); - - memcpy (ias_cmd->params, bis->bi_enetaddr, 6); - - /* Tell the adapter where the TX ring is located. - */ - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not reset ethernet controller\n"); - return (status); - } - - OUTL (dev, (u32) & tx_ring[tx_cur], SCBPointer); - OUTW (dev, SCB_M | CU_START, SCBCmd); - - for (i = 0; - !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); - i++) { - if (i >= TOUT_LOOP) { - printf ("%s: Tx error buffer not ready\n", dev->name); - return (status); - } - } - - if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { - printf ("TX error status = 0x%08X\n", - le16_to_cpu (tx_ring[tx_cur].status)); - return (status); - } - - status = 1; - - return (status); -} - -static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) -{ - int i, status = -1; - int tx_cur; - - if (length <= 0) { - printf ("%s: bad packet size: %d\n", dev->name, length); - return (status); - } - - tx_cur = tx_next; - tx_next = (tx_next + 1) % NUM_TX_DESC; - - tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | - TxCB_CMD_SF | - TxCB_CMD_S | - TxCB_CMD_EL); - tx_ring[tx_cur].status = 0; - tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); - tx_ring[tx_cur].link = cpu_to_le32 ((u32) & tx_ring[tx_next]); - tx_ring[tx_cur].tx_desc_addr = cpu_to_le32 ((u32) & tx_ring[tx_cur].tx_buf_addr0); - tx_ring[tx_cur].tx_buf_addr0 = cpu_to_le32 ((u_long) packet); - tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); - - if (!wait_for_eepro100 (dev)) { - printf ("%s: Tx error ethernet controller not ready\n", dev->name); - return (status); - } - - /* Send the packet. - */ - OUTL (dev, (u32) & tx_ring[tx_cur], SCBPointer); - OUTW (dev, SCB_M | CU_START, SCBCmd); - - for (i = 0; - !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); - i++) { - if (i >= TOUT_LOOP) { - printf ("%s: Tx error buffer not ready\n", dev->name); - return (status); - } - } - - if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { - printf ("TX error status = 0x%08X\n", - le16_to_cpu (tx_ring[tx_cur].status)); - return (status); - } - - status = length; - - return (status); -} - -static int eepro100_recv (struct eth_device *dev) -{ - u16 status, stat; - int rx_prev, length = 0; - - stat = INW (dev, SCBStatus); - OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); - - for (;;) { - status = le16_to_cpu (rx_ring[rx_next].status); - - if (!(status & RFD_STATUS_C)) { - break; - } - - /* Valid frame status. - */ - if ((status & RFD_STATUS_OK)) { - /* A valid frame received. - */ - length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive (rx_ring[rx_next].data, length); - } else { - /* There was an error. - */ - printf ("RX error status = 0x%08X\n", status); - } - - rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); - rx_ring[rx_next].status = 0; - rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); - - rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; - rx_ring[rx_prev].control = 0; - - /* Update entry information. - */ - rx_next = (rx_next + 1) % NUM_RX_DESC; - } - - if (stat & SCB_STATUS_RNR) { - - printf ("%s: Receiver is not ready, restart it\n", dev->name); - - /* Reinitialize Rx ring. - */ - init_rx_ring (); - - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not restart ethernet controller\n"); - return (length); - } - - OUTL (dev, (u32) & rx_ring[rx_next], SCBPointer); - OUTW (dev, SCB_M | RUC_START, SCBCmd); - } - - return (length); -} - -static void eepro100_halt (struct eth_device* dev) -{ - /* Reset the ethernet controller - */ - OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); - udelay (20); - - OUTL (dev, I82559_RESET, SCBPort); - udelay (20); - - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not reset ethernet controller\n"); - return; - } - OUTL (dev, 0, SCBPointer); - OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); - - if (!wait_for_eepro100 (dev)) { - puts ("Error: Can not reset ethernet controller\n"); - return; - } - OUTL (dev, 0, SCBPointer); - OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); - - return; -} - - /* SROM Read. - */ -static int read_eeprom (struct eth_device* dev, int location, int addr_len) -{ - unsigned short retval = 0; - int read_cmd = location | EE_READ_CMD; - int i; - - OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); - OUTW (dev, EE_ENB, SCBeeprom); - - /* Shift the read command bits out. */ - for (i = 12; i >= 0; i--) { - short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; - - OUTW (dev, EE_ENB | dataval, SCBeeprom); - udelay (1); - OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); - udelay (1); - } - OUTW (dev, EE_ENB, SCBeeprom); - - for (i = 15; i >= 0; i--) { - OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); - udelay (1); - retval = (retval << 1) | - ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); - OUTW (dev, EE_ENB, SCBeeprom); - udelay (1); - } - - /* Terminate the EEPROM access. */ - OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); - return retval; -} - -static void init_rx_ring (void) -{ - int i; - - for (i = 0; i < NUM_RX_DESC; i++) { - rx_ring[i].status = 0; - rx_ring[i].control = (i == NUM_RX_DESC - 1) ? - cpu_to_le16 (RFD_CONTROL_S) : 0; - rx_ring[i].link = cpu_to_le32 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]); - rx_ring[i].rx_buf_addr = 0xffffffff; - rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); - } - - rx_next = 0; -} - -static void purge_tx_ring (void) -{ - int i; - - tx_next = 0; - tx_threshold = 0x01208000; - - for (i = 0; i < NUM_TX_DESC; i++) { - tx_ring[i].status = 0; - tx_ring[i].command = 0; - tx_ring[i].link = 0; - tx_ring[i].tx_desc_addr = 0; - tx_ring[i].count = 0; - - tx_ring[i].tx_buf_addr0 = 0; - tx_ring[i].tx_buf_size0 = 0; - tx_ring[i].tx_buf_addr1 = 0; - tx_ring[i].tx_buf_size1 = 0; - } -} - -static void read_hw_addr (struct eth_device *dev, bd_t * bis) -{ - u16 eeprom[0x40]; - u16 sum = 0; - int i, j; - int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; - - for (j = 0, i = 0; i < 0x40; i++) { - u16 value = read_eeprom (dev, i, addr_len); - - eeprom[i] = value; - sum += value; - if (i < 3) { - dev->enetaddr[j++] = value; - dev->enetaddr[j++] = value >> 8; - } - } - - if (sum != 0xBABA) { - printf ("%s: Invalid EEPROM checksum %#4.4x, " - "check settings before activating this device!\n", - dev->name, sum); - } - -#ifdef DEBUG - for (i = 0; i < ETH_ALEN; i++) { - if (dev->enetaddr[i] != bis->bi_enetaddr[i]) { - printf ("Warning: HW address don't match:\n"); - printf ("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - dev->enetaddr[0], dev->enetaddr[1], - dev->enetaddr[2], dev->enetaddr[3], - dev->enetaddr[4], dev->enetaddr[5]); - printf ("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - return; - } - } -#endif - - return; -} - -#endif diff --git a/board/sandpoint/ns16550.h b/board/sandpoint/ns16550.h deleted file mode 100644 index f525d74..0000000 --- a/board/sandpoint/ns16550.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - */ - - -struct NS16550 { - char rbr; /* 0 */ - unsigned char ier; /* 1 */ - unsigned char fcr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ -}; - -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -#define FCR_FIFO_EN 0x01 /*fifo enable */ -#define FCR_RXSR 0x02 /*receiver soft reset */ -#define FCR_TXSR 0x04 /*transmitter soft reset */ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask */ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble */ -#define LCR_EPS 0x10 /* Even Parity Select */ -#define LCR_STKP 0x20 /* Stick Parity */ -#define LCR_SBRK 0x40 /* Set Break */ -#define LCR_BKSE 0x80 /* Bank select enable */ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor); -void NS16550_putc (volatile struct NS16550 *com_port, char c); -char NS16550_getc (volatile struct NS16550 *com_port); -int NS16550_tstc (volatile struct NS16550 *com_port); -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/sandpoint/ns87308.c b/board/sandpoint/ns87308.c deleted file mode 100644 index 1da0f54..0000000 --- a/board/sandpoint/ns87308.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#include -#include "ns87308.h" -#include "ns16550.h" /* to configure the 87308's internal 16550's */ -#include /* to configure 87308's RTC */ - -void initialise_ns87308 (void) -{ - PNP_SET_DEVICE_BASE(LDEV_UART1, COM1); - PNP_SET_DEVICE_BASE(LDEV_UART2, COM2); - - PNP_SET_DEVICE_BASE(LDEV_RTC_APC, RTC_PORT(0)); - PNP_ACTIVATE_DEVICE(LDEV_POWRMAN); - - /* set up the NVRAM access registers - NVRAM's controlled by the configurable CS line from the 87308*/ - - PNP_PGCS_CSLINE_BASE(0, 0x76); - PNP_PGCS_CSLINE_CONF(0, 0x30); - PNP_PGCS_CSLINE_BASE(1, 0x75); - PNP_PGCS_CSLINE_CONF(1, 0x30); - PNP_PGCS_CSLINE_BASE(2, 0x74); - PNP_PGCS_CSLINE_CONF(2, 0x30); -} -/* -void write_pnp_config(unsigned char index, unsigned char data) -{ - unsigned char *io_index = (unsigned char *) IO_INDEX; - unsigned char *io_data = (unsigned char *) IO_DATA; - *io_index = index; - *io_data = data; -} - -void pnp_set_device(unsigned char dev) -{ - write_pnp_config(LOGICAL_DEVICE, dev); -} -*/ diff --git a/board/sandpoint/ns87308.h b/board/sandpoint/ns87308.h deleted file mode 100644 index f007cbf..0000000 --- a/board/sandpoint/ns87308.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _NS87308_H_ -#define _NS87308_H_ - -#include - -/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty - functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */ - -/*PNP config registers: - * these depend on the stated of BADDR1 and BADDR0 on startup - * so there's three versions here with the last two digits indicating - * for which configuration their valid - * the 1st of the two digits indicates the state of BADDR1 - * the 2st of the two digits indicates the state of BADDR0 - */ - - -#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */ -#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */ -#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */ -#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */ -#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */ -#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */ - -#if defined(CFG_NS87308_BADDR_0x) -#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x) -#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_0x) -#elif defined(CFG_NS87308_BADDR_10) -#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10) -#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_10) -#elif defined(CFG_NS87308_BADDR_11) -#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11) -#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_11) -#endif - -/* PnP register definitions */ - -#define SET_RD_DATA_PORT 0x00 -#define SERIAL_ISOLATION 0x01 -#define CONFIG_CONTROL 0x02 -#define WAKE_CSN 0x03 -#define RES_DATA 0x04 -#define STATUS 0x05 -#define SET_CSN 0x06 -#define LOGICAL_DEVICE 0x07 -/*vendor defined values */ -#define SID_REG 0x20 -#define SUPOERIO_CONF1 0x21 -#define SUPOERIO_CONF2 0x22 -#define PGCS_INDEX 0x23 -#define PGCS_DATA 0x24 - -/* values above 30 are different for each logical device - but I can't be arsed to enter them all. the ones here - are pretty consistent between all logical devices - feel free to correct the situation if you want.. ;) - */ -#define ACTIVATE 0x30 -#define ACTIVATE_OFF 0x00 -#define ACTIVATE_ON 0x01 - -#define BASE_ADDR_HIGH 0x60 -#define BASE_ADDR_LOW 0x61 - -/* the logical devices*/ -#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/ -#define LDEV_KBC2 0x01 -#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/ -#define LDEV_FDC 0x03 /*floppy disk controller*/ -#define LDEV_PARP 0x04 /*Parallel port*/ -#define LDEV_UART2 0x05 -#define LDEV_UART1 0x06 -#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/ -#define LDEV_POWRMAN 0x08 /*Power Managment*/ - -/*some functions and macro's for doing configuration */ - -static inline void write_pnp_config(unsigned char index, unsigned char data) -{ - pci_writeb(index,IO_INDEX); - pci_writeb(data, IO_DATA); -} - -static inline void pnp_set_device(unsigned char dev) -{ - write_pnp_config(LOGICAL_DEVICE, dev); -} - - -/*void write_pnp_config(unsigned char index, unsigned char data); -void pnp_set_device(unsigned char dev); -*/ - -#define PNP_SET_DEVICE_BASE(dev,base) \ - pnp_set_device(dev); \ - write_pnp_config(ACTIVATE, ACTIVATE_OFF); \ - write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \ - write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \ - write_pnp_config(ACTIVATE, ACTIVATE_ON); - -#define PNP_ACTIVATE_DEVICE(dev) \ - pnp_set_device(dev); \ - write_pnp_config(ACTIVATE, ACTIVATE_ON); - -#define PNP_DEACTIVATE_DEVICE(dev) \ - pnp_set_device(dev); \ - write_pnp_config(ACTIVATE, ACTIVATE_OFF); - - -static inline void write_pgcs_config(unsigned char index, unsigned char data) -{ - write_pnp_config(PGCS_INDEX, index); - write_pnp_config(PGCS_DATA, data); -} - -/* these macros configure the 3 CS lines - on the sandpoint board these controll NVRAM - CS0 is connected to NVRAMCS - CS1 is connected to NVRAMAS0 - CS2 is connected to NVRAMAS1 - */ -#define PGCS_CS_ASSERT_ON_WRITE 0x10 -#define PGCS_CS_ASSERT_ON_READ 0x20 - -#define PNP_PGCS_CSLINE_BASE(cs, base) \ - write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \ - write_pgcs_config(((cs) << 2) + 1, (base) & 0xff ); - -#define PNP_PGCS_CSLINE_CONF(cs, conf) \ - write_pgcs_config(((cs) << 2) + 2, (conf) ); - - -/* The following sections are for 87308 extensions to the standard compoents it emulates */ - -/* extensions to 16550*/ - -#define MCR_MDSL_MSK 0xe0 /*mode select mask*/ -#define MCR_MDSL_UART 0x00 /*uart, default*/ -#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/ -#define MCR_MDSL_SIR 0x03 /*SIR*/ -#define MCR_MDSL_CIR 0x06 /*Consumer IR*/ - -#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */ -#define FCR_TXFTH1 0x20 /* for interrupt trigger */ - - -#endif /*_NS87308_H_*/ diff --git a/board/sandpoint/pci.c b/board/sandpoint/pci.c deleted file mode 100644 index 7b69c05..0000000 --- a/board/sandpoint/pci.c +++ /dev/null @@ -1,631 +0,0 @@ -/* - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge - */ -#include -#include "mpc824x.h" -#include "pci.h" - -int numPciBus = 1; /* One bus: MPC107 Internal bridge */ - -/* - * - * pci_dev_find - find the nth device with the given device & vendor ID - * - */ -int pci_dev_find(int vendorId, /* vendor ID */ - int deviceId, /* device ID */ - int index, /* desired instance of device */ - int* pBusNo, /* bus number */ - int* pDeviceNo, /* device number */ - int* pFuncNo) /* function number */ -{ - int status = ERROR; - int cont = TRUE; - int busNo; - int deviceNo; - int funcNo; - uint32 device; - uint32 vendor; - char header; - - for (busNo = 0; cont == TRUE && busNo <= numPciBus; busNo++) - for (deviceNo = 0; - ((cont == TRUE) && (deviceNo < PCI_MAX_DEV)); - ++deviceNo) - for (funcNo = 0; cont == TRUE && funcNo < PCI_MAX_FUNC; funcNo++){ - /* avoid a special bus cycle */ - - if ((deviceNo == 0x1f) && (funcNo == 0x07)) - continue; - - pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, - &vendor); - - /* - * If nonexistent device, skip to next, only look at - * vendor ID field for existence check - */ - if (((vendor & 0x0000ffff) == 0x0000FFFF) && (funcNo == 0)) - break; - device = vendor >> 16; - device &= 0x0000FFFF; - vendor &= 0x0000FFFF; - if ((vendor == (uint32)vendorId) && - (device == (uint32)deviceId) && - (index-- == 0)){ - *pBusNo = busNo; - *pDeviceNo = deviceNo; - *pFuncNo = funcNo; - status = OK; - cont = FALSE; /* terminate all loops */ - continue; - } - - /* goto next if current device is single function */ - - pci_config_inb (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, - &header); - if ((header & PCI_HEADER_MULTI_FUNC) != - PCI_HEADER_MULTI_FUNC && funcNo == 0) - break; - } - - return status; -} - -/* - * - * pci_class_find - find the nth occurence of a device by PCI class code. - * - * RETURNS: - * OK, or ERROR if the class didn't match. - */ - -int pci_class_find(int classCode, /* 24-bit class code */ - int index, /* desired instance of device */ - int * pBusNo, /* bus number */ - int * pDeviceNo, /* device number */ - int * pFuncNo) /* function number */ -{ - int status = ERROR; - int cont = TRUE; - int busNo; - int deviceNo; - int funcNo; - int classCodeReg; - int vendor; - char header; - - - for (busNo = 0; cont == TRUE && busNo <= numPciBus; busNo++) - for (deviceNo = 0; - ((cont == TRUE) && (deviceNo < PCI_MAX_DEV)); - ++deviceNo) - for (funcNo = 0; cont == TRUE && funcNo < PCI_MAX_FUNC; funcNo++){ - - /* avoid a special bus cycle */ - if ((deviceNo == 0x1f) && (funcNo == 0x07)) - continue; - - pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, - &vendor); - - /* - * If nonexistent device, skip to next, only look at - * vendor ID field for existence check - */ - if (((vendor & 0x0000ffff) == 0x0000FFFF) && (funcNo == 0)) - break; - - pci_config_inl (busNo, deviceNo, funcNo, PCI_CFG_REVISION, - &classCodeReg); - - if ((((classCodeReg >> 8) & 0x00ffffff) == classCode) && - (index-- == 0)) - { - *pBusNo = busNo; - *pDeviceNo = deviceNo; - *pFuncNo = funcNo; - status = OK; - cont = FALSE; /* terminate all loops */ - continue; - } - - /* goto next if current device is single function */ - - pci_config_inb (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, - &header); - if ((header & PCI_HEADER_MULTI_FUNC) != - PCI_HEADER_MULTI_FUNC && funcNo == 0) - break; - } - return status; -} - - -/* - * - * pci_dev_config - configure a device on a PCI bus - * - * This routine configures a device that is on a Peripheral Component - * Interconnect (PCI) bus by writing to the configuration header of the - * selected device. - * - * It first disables the device by clearing the command register in the - * configuration header. It then sets the I/O and/or memory space base - * address registers, the latency timer value and the cache line size. - * Finally, it re-enables the device by loading the command register with - * the specified command. - * - * NOTE: This routine is designed for Type 0 PCI Configuration Headers ONLY. - * It is NOT usable for configuring, for example, a PCI-to-PCI bridge. - * - * RETURNS: OK always. - */ -int pci_dev_config(int pciBusNo, /* PCI bus number */ - int pciDevNo, /* PCI device number */ - int pciFuncNo, /* PCI function number */ - uint32 devIoBaseAdrs, /* device IO base address */ - uint32 devMemBaseAdrs, /* device memory base address */ - uint32 command) /* command to issue */ -{ - int ix; - uint32 tmp32; - - /* - * Disable device by clearing its command register field in its - * configuration header. Write 0 clears command and preserves status. - */ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0); - - for (ix = PCI_CFG_BASE_ADDRESS_0; ix <= PCI_CFG_BASE_ADDRESS_5; ix+=4){ - - /* Write all f's and read back value */ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, 0xffffffff); - pci_config_inl (pciBusNo, pciDevNo, pciFuncNo, ix, &tmp32); - - if (tmp32 == 0){ - /* No bar */ - break; - } - - /* I/O space requested */ - if (tmp32 & 0x1){ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, - devIoBaseAdrs | 0x1); - } else{ - /* Memory space required, set specified base address */ - pci_config_outl (pciBusNo, pciDevNo, pciFuncNo, ix, - devMemBaseAdrs & ~0x1); - } - } - - /* Configure Cache Line Size Register */ - pci_config_outb (pciBusNo, pciDevNo, pciFuncNo, - PCI_CFG_CACHE_LINE_SIZE, - PCI_CACHE_LINE_SIZE); - - /* Configure Latency Timer */ - pci_config_outb (pciBusNo, pciDevNo, pciFuncNo, - PCI_CFG_LATENCY_TIMER, - PCI_LATENCY_TIMER); - - /* - * Enable the device's capabilities as specified, do not - * reset any status bits in doing so. - */ - pci_config_modl (pciBusNo, pciDevNo, pciFuncNo, - PCI_CFG_COMMAND, - (PCI_CMD_MASK | command), command); - - return OK; -} - - -/* - * - * pci_config_bdf_pack - pack parameters for the Configuration Address Register - * - * This routine packs three parameters into one integer for accessing the - * Configuration Address Register - * - */ - -int pci_config_bdf_pack(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo) /* function number */ -{ - return (((busNo << 16) & 0x00ff0000) | - ((deviceNo << 11) & 0x0000f800) | - ((funcNo << 8) & 0x00000700)); -} - -/* - * pci_config_inb - read one byte from the PCI configuration space - * - * This routine reads one byte from the PCI configuration space - * - */ -int pci_config_inb(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint8 * pData) /* data read from the offset */ -{ - uint8 retval = 0; - int retStat = ERROR; - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - retval = mpc824x_mpc107_read8 (CHRP_REG_DATA + (offset & 0x3)); - retStat = OK; - - *pData = retval; - - return retStat; -} - -/* - * - * pci_config_inw - read one word from the PCI configuration space - * - * This routine reads one word from the PCI configuration space - * - */ -int pci_config_inw(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint16 * pData) /* data read from the offset */ -{ - int retStat = ERROR; - uint16 retval = 0; - - if (((offset & (int)0x1) > 0) ) { - return (retStat); - } - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - retval = mpc824x_mpc107_read16 (CHRP_REG_DATA + (offset & 0x2)); - retStat = OK; - *pData = retval; - - return retStat; -} - -/* - * - * pci_config_inl - read one longword from the PCI configuration space - * - * This routine reads one longword from the PCI configuration space - * - */ -int pci_config_inl(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint32 * pData) /* data read from the offset */ -{ - int retStat = ERROR; - uint32 retval = 0; - - if (((offset & (int)0x3) > 0) ) { - return (retStat); - } - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - retval = mpc824x_mpc107_read32 (CHRP_REG_DATA); - asm volatile ("eieio"); - retStat = OK; - *pData = retval; - return retStat; -} - -/* - * pci_config_outb - write one byte to the PCI configuration space - * - * This routine writes one byte to the PCI configuration space. - * - */ -int pci_config_outb(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint8 data) /* data written to the offset */ -{ - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - mpc824x_mpc107_write8 ((CHRP_REG_DATA + (offset & 0x3)), data); - return OK; -} - -/* - * pci_config_outw - write one 16-bit word to the PCI configuration space - * - * This routine writes one 16-bit word to the PCI configuration space. - * - * RETURNS: OK, or ERROR if this library is not initialized - */ -int pci_config_outw(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint16 data) /* data written to the offset */ -{ - if (((offset & (int)0x1) > 0) ){ - return (ERROR); - } - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - mpc824x_mpc107_write16 ((CHRP_REG_DATA + (offset & 0x2)), data); - return OK; -} - - -/* - * - * pci_config_outl - write one longword to the PCI configuration space - * - * This routine writes one longword to the PCI configuration space. - * - */ -int pci_config_outl(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint32 data) /* data written to the offset */ -{ - if (((offset & (int)0x3) > 0) ){ - return (ERROR); - } - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - (offset & 0xfc) | 0x80000000); - mpc824x_mpc107_write32 (CHRP_REG_DATA, data); - asm volatile ("eieio"); - return OK; -} - - -/* - * - * pci_config_modl - Perform a masked longword register update - * - * This function writes a field into a PCI configuration header without - * altering any bits not present in the field. It does this by first - * doing a PCI configuration read (into a temporary location) of the PCI - * configuration header word which contains the field to be altered. - * It then alters the bits in the temporary location to match the desired - * value of the field. It then writes back the temporary location with - * a configuration write. All configuration accesses are long and the - * field to alter is specified by the "1" bits in the 'bitMask' parameter. - * - */ - -int pci_config_modl(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint32 bitMask, /* Mask of bits to alter */ - uint32 data) /* data written to the offset */ - -{ - uint32 temp; - int stat; - - if (((offset & (int)0x3) > 0) ){ - return (ERROR); - } - - stat = pci_config_inl (busNo, deviceNo, funcNo, offset, &temp); - if (stat == OK){ - temp = (temp & ~bitMask) | (data & bitMask); - stat = pci_config_outl (busNo, deviceNo, funcNo, offset, temp); - } - return stat; -} - - -/* - * - * pci_config_modw - Perform a masked short register update - * - */ -int pci_config_modw(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint16 bitMask, /* Mask of bits to alter */ - uint16 data) /* data written to the offset */ -{ - uint16 temp; - int stat; - if (((offset & (int)0x1) > 0) ){ - return (ERROR); - } - stat = pci_config_inw (busNo, deviceNo, funcNo, offset, &temp); - if (stat == OK){ - temp = (temp & ~bitMask) | (data & bitMask); - stat = pci_config_outw (busNo, deviceNo, funcNo, offset, temp); - } - return stat; -} - - - -/* - * pci_config_modb - Perform a masked byte register update - * - */ -int pci_config_modb(int busNo, /* bus number */ - int deviceNo, /* device number */ - int funcNo, /* function number */ - int offset, /* offset into config space */ - uint8 bitMask, /* Mask of bits to alter */ - uint8 data) /* data written to the offset */ -{ - uint8 temp; - int stat; - stat = pci_config_inb (busNo, deviceNo, funcNo, offset, &temp); - if (stat == OK){ - temp = (temp & ~bitMask) | (data & bitMask); - stat = pci_config_outb (busNo, deviceNo, funcNo, offset, temp); - } - return stat; -} - -/* - * pci_special_cycle - generate a special cycle with a message - */ -int -pci_special_cycle(int busNo, /* bus number */ - uint32 message) /* data driven onto AD[31:0] */ -{ - int deviceNo = 0x0000001f; - int funcNo = 0x00000007; - - mpc824x_mpc107_write32 (CHRP_REG_ADDR, - pci_config_bdf_pack (busNo, deviceNo, funcNo) | - 0x80000000); - mpc824x_mpc107_write32 (CHRP_REG_DATA, message); - return OK; -} - - -/* - * Find the extent of a PCI decode.. - */ -unsigned int -pci_size_bar(unsigned int base, unsigned long mask) -{ - uint32 size = mask & base; /* Find the significant bits */ - size = size & ~(size-1); /* Get the lowest of them to find the decode size */ - return size-1; /* extent = size - 1 */ -} - -/* - * Show/Init PCI devices on the specified bus number. - */ -int pci_dev_init(int busNo) -{ - int deviceNo; - int devices; - uint16 vendorId; - uint16 deviceId; - uint32 mbar0; - uint32 mbar1; - uint32 revId; - uint32 iline,ipin; - - union { - int classCode; - char array[4]; - } u; - - printf("PCI: scanning bus%d ...\n", busNo); - printf(" bus dev fn venID devID class" - " rev MBAR0 MBAR1 IPIN ILINE\n"); - - devices = 0x1f; - for (deviceNo=0; deviceNo < devices; deviceNo++) { - - /* Get device and vendor ID */ - pci_config_inw (busNo, deviceNo, 0, PCI_CFG_VENDOR_ID, &vendorId); - pci_config_inw (busNo, deviceNo, 0, PCI_CFG_DEVICE_ID, &deviceId); - - /* MPC107 Bridge */ - if( deviceNo == 0x0){ - /* Don't do anything */ - } - - /* Make sure IRQ's on PCI devices get configured correctly */ - if( deviceNo == 0x0f){ - /* Onboard */ - pci_dev_config(busNo, deviceNo, 0, - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_CMD_MEM_ENABLE | - PCI_CMD_MASTER_ENABLE); - } /* PCI Slot */ - else if (deviceNo == 0x10) { - /* Onboard */ - pci_dev_config(busNo, deviceNo, 0, - PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_CMD_MEM_ENABLE | - PCI_CMD_MASTER_ENABLE); - } - - pci_config_inb (busNo, deviceNo, 0, PCI_CFG_PROGRAMMING_IF, - &u.array[3]); - pci_config_inb (busNo, deviceNo, 0, PCI_CFG_SUBCLASS, &u.array[2]); - pci_config_inb (busNo, deviceNo, 0, PCI_CFG_CLASS, &u.array[1]); - u.array[0] = 0; - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_0, &mbar0); - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_1, &mbar1); - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_REVISION, &revId); - revId &= 0x000000ff; - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &iline); - iline &= 0x000000ff; - - pci_config_inl(busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &ipin); - ipin &= 0x0000ff00; - ipin >>= 8; - - - /* There are two ways to find out an empty device. - * 1. check Master Abort bit after the access. - * 2. check whether the read value is 0xffff. - * Since I didn't see the Master Abort bit of the host/PCI bridge - * changing, I use the second method. - */ - if (vendorId != 0xffff) - - printf(" %02x %02x %02x %04x %04x " - "%06x %02x %08x %08x %02x %02x\n", - busNo, deviceNo, 0, - vendorId, deviceId, u.classCode, revId, - mbar0, mbar1, ipin, iline); - } - return OK; -} - - diff --git a/board/sandpoint/pci.h b/board/sandpoint/pci.h deleted file mode 100644 index bfb6903..0000000 --- a/board/sandpoint/pci.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __MPC824X_PCI -#define __MPC824X_PCI - -/* - * PCI Configuration space Library and constants for MPC824x based - * systems. - */ - -typedef unsigned char uint8; -typedef unsigned int uint32; -typedef unsigned short uint16; -typedef int INT32; -#define LOCAL static -#define IMPORT extern - -#ifndef NULL -#define NULL 0 -#endif - -#define OK 1 -#define NONE 0 -#define ERROR -1 -#define TRUE 1 -#define FALSE (!TRUE) - - -#define PCI_MAX_BUS 255 -#define PCI_MAX_DEV 32 -#define PCI_MAX_FUNC 8 - - -/* PCI Configuration I/O Addresses */ -#define PCI_CONFIG_ADDR 0x0cf8 /* write 32 bits to set address */ -#define PCI_CONFIG_DATA 0x0cfc /* 8, 16, or 32 bit accesses */ -#define PCI_CONFIG_CSE 0x0cf8 /* CSE register */ -#define PCI_CONFIG_FORWARD 0x0cfa /* forward register */ -#define PCI_CONFIG_BASE 0xc000 /* base register */ - -/* PCI command bits */ -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ - -/* PCI base address mask bits */ - -#define PCI_MEMBASE_MASK ~0xf /* mask for memory base address */ -#define PCI_IOBASE_MASK ~0x3 /* mask for IO base address */ -#define PCI_BASE_IO 0x1 /* IO space indicator */ -#define PCI_BASE_BELOW_1M 0x2 /* memory locate below 1MB */ -#define PCI_BASE_IN_64BITS 0x4 /* memory locate anywhere in 64 bits */ -#define PCI_BASE_PREFETCH 0x8 /* memory prefetchable */ - -/* Base Address Register Memory/IO Attribute bits */ - -#define PCI_BAR_SPACE_MASK (0x01) -#define PCI_BAR_SPACE_IO (0x01) -#define PCI_BAR_SPACE_MEM (0x00) - -#define PCI_BAR_MEM_TYPE_MASK (0x06) -#define PCI_BAR_MEM_ADDR32 (0x00) -#define PCI_BAR_MEM_BELOW_1MB (0x02) -#define PCI_BAR_MEM_ADDR64 (0x04) -#define PCI_BAR_MEM_RESERVED (0x06) - -#define PCI_BAR_MEM_PREF_MASK (0x08) -#define PCI_BAR_MEM_PREFETCH (0x08) -#define PCI_BAR_MEM_NON_PREF (0x00) - -#define PCI_BAR_ALL_MASK (PCI_BAR_SPACE_MASK | \ - PCI_BAR_MEM_TYPE_MASK | \ - PCI_BAR_MEM_PREF_MASK) - -/* PCI header type bits */ - -#define PCI_HEADER_TYPE_MASK 0x7f /* mask for header type */ -#define PCI_HEADER_PCI_PCI 0x01 /* PCI to PCI bridge */ -#define PCI_HEADER_TYPE0 0x00 /* normal device header */ -#define PCI_HEADER_MULTI_FUNC 0x80 /* multi function device */ - -/* PCI configuration device and driver */ - -#define SNOOZE_MODE 0x40 /* snooze mode */ -#define SLEEP_MODE_DIS 0x00 /* sleep mode disable */ - -/* Standard device configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDER_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - - -/* PCI-to-PCI bridge configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_PRIMARY_BUS 0x18 -#define PCI_CFG_SECONDARY_BUS 0x19 -#define PCI_CFG_SUBORDINATE_BUS 0x1a -#define PCI_CFG_SEC_LATENCY 0x1b -#define PCI_CFG_IO_BASE 0x1c -#define PCI_CFG_IO_LIMIT 0x1d -#define PCI_CFG_SEC_STATUS 0x1e -#define PCI_CFG_MEM_BASE 0x20 -#define PCI_CFG_MEM_LIMIT 0x22 -#define PCI_CFG_PRE_MEM_BASE 0x24 -#define PCI_CFG_PRE_MEM_LIMIT 0x26 -#define PCI_CFG_PRE_MEM_BASE_U 0x28 -#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c -#define PCI_CFG_IO_BASE_U 0x30 -#define PCI_CFG_IO_LIMIT_U 0x32 -#define PCI_CFG_ROM_BASE 0x38 -#define PCI_CFG_BRG_INT_LINE 0x3c -#define PCI_CFG_BRG_INT_PIN 0x3d -#define PCI_CFG_BRIDGE_CONTROL 0x3e - -/* PCI Class definitions for find by class function */ - -#define PCI_CLASS_PRE_PCI20 0x00 -#define PCI_CLASS_MASS_STORAGE 0x01 -#define PCI_CLASS_NETWORK_CTLR 0x02 -#define PCI_CLASS_DISPLAY_CTLR 0x03 -#define PCI_CLASS_MMEDIA_DEVICE 0x04 -#define PCI_CLASS_MEM_CTLR 0x05 -#define PCI_CLASS_BRIDGE_CTLR 0x06 -#define PCI_CLASS_COMM_CTLR 0x07 -#define PCI_CLASS_BASE_PERIPH 0x08 -#define PCI_CLASS_INPUT_DEVICE 0x09 -#define PCI_CLASS_DOCK_DEVICE 0x0A -#define PCI_CLASS_PROCESSOR 0x0B -#define PCI_CLASS_SERIAL_BUS 0x0C -#define PCI_CLASS_UNDEFINED 0xFF - -/* PCI Subclass definitions */ - -#define PCI_SUBCLASS_00 0x00 -#define PCI_SUBCLASS_01 0x01 -#define PCI_SUBCLASS_02 0x02 -#define PCI_SUBCLASS_03 0x03 -#define PCI_SUBCLASS_04 0x04 -#define PCI_SUBCLASS_05 0x05 -#define PCI_SUBCLASS_06 0x06 -#define PCI_SUBCLASS_07 0x07 -#define PCI_SUBCLASS_10 0x10 -#define PCI_SUBCLASS_20 0x20 -#define PCI_SUBCLASS_80 0x80 - -/* Bridge Device subclasses */ - -#define PCI_SUBCLASS_HOST_PCI_BRIDGE (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_ISA_BRIDGE (PCI_SUBCLASS_01) -#define PCI_SUBCLASS_P2P_BRIDGE (PCI_SUBCLASS_04) -#define PCI_SUBCLASS_PCMCIA_BRIDGE (PCI_SUBCLASS_05) -#define PCI_SUBCLASS_CARDBUS_BRIDGE (PCI_SUBCLASS_07) - -/* Processor subclasses */ - -#define PCI_SUBCLASS_PROCESSOR_386 (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_PROCESSOR_486 (PCI_SUBCLASS_01) -#define PCI_SUBCLASS_PROCESSOR_PENTIUM (PCI_SUBCLASS_02) -#define PCI_SUBCLASS_PROCESSOR_ALPHA (PCI_SUBCLASS_10) -#define PCI_SUBCLASS_PROCESSOR_POWERPC (PCI_SUBCLASS_20) - -/* Serial bus subclasses */ - -#define PCI_SUBCLASS_SERBUS_FIREWIRE (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_SERBUS_USB (PCI_SUBCLASS_03) - -/* Network subclasses */ - -#define PCI_SUBCLASS_NET_ETHERNET (PCI_SUBCLASS_00) -#define PCI_SUBCLASS_NET_TOKEN_RING (PCI_SUBCLASS_01) -#define PCI_SUBCLASS_NET_FDDI (PCI_SUBCLASS_02) -#define PCI_SUBCLASS_NET_ATM (PCI_SUBCLASS_03) - -/* Conditional defines for new configuration definitions */ - -#define PCI_CMD_MASK 0xffff0000 -#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) -#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) - -/* Vendor and Device ID's */ - -/* Promise ATA */ -#define PCI_VENDOR_ID_PROMISE 0x105a -#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 -#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 -#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 -#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 -#define PCI_DEVICE_ID_PROMISE_5300 0x5300 - -/* Intel Ethernet */ -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 -#define PCI_DEVICE_ID_INTEL_82557 0x1229 -#define PCI_DEVICE_ID_INTEL_82559 0x1030 - -/* Cache Line Size - 32 32-bit value = 128 bytes */ -#ifndef PCI_CACHE_LINE_SIZE -#define PCI_CACHE_LINE_SIZE 0x08 -#endif /* PCI_CACHE_LINE_SIZE */ - -/* Latency Timer value - 255 PCI clocks */ -#ifndef PCI_LATENCY_TIMER -#define PCI_LATENCY_TIMER 0x20 -#endif /* PCI_LATENCY_TIMER */ - -#ifndef _ASMLANGUAGE -int pci_dev_init(int b); -int pci_dev_find(int vid, int devId, int idx,int *bus, int* dev, int* func); -int pci_class_find(int class, int idx, int* bus, int* dev, int *func); -int pci_config_inb(int b, int d, int f, int address, uint8 * pData); -int pci_config_inw(int b, int d, int f, int address, uint16 * pData); -int pci_config_inl(int b, int d, int f, int address, uint32 * pData); -int pci_config_outb(int b, int d, int f, int address, uint8 data); -int pci_config_outw(int b, int d, int f, int address, uint16 data); -int pci_config_outl(int b, int d, int f, int address, uint32 data); -int pci_special_cycle(int b, uint32 message); -int pci_config_bdf_pack(int b, int d, int f); -int pci_dev_config(int b, int d, int f, uint32 iobar, uint32 mbar, uint32 cm ); -int pci_config_modl(int b, int d, int f, int offset, - uint32 bitMask, uint32 data ); -int pci_config_modw(int b, int d, int f, int off, - uint16 bitMask, uint16 data ); -int pci_config_modb(int b, int d, int f, int offset, - uint8 bitMask, uint8 data ); -unsigned int pci_size_bar(unsigned int, unsigned long mask); -#endif /* _ASMLANGUAGE */ - -#endif /* __MPC824X_PCI */ diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index d58baba..4a8d40f 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -23,6 +23,7 @@ #include #include +#include int checkboard (void) { @@ -100,9 +101,27 @@ Done: /* * Initialize PCI Devices, report devices found. */ -void pci_init (bd_t * dummy) -{ - extern int pci_dev_init (int busNo); +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif - pci_dev_init (0); +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init(bd_t *bd) +{ + pci_mpc824x_init(bd, &hose); } diff --git a/board/sandpoint/serial.c b/board/sandpoint/serial.c deleted file mode 100644 index 71b62f3..0000000 --- a/board/sandpoint/serial.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "ns16550.h" - -#define IDATA (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET) - -void initialise_ns87308(void); - -/* - * Minimal serial functions needed to use one87308's UARTs - * as serial console interface. - */ - -volatile struct NS16550 *console; - -void -serial_init (unsigned long dummy, int baudrate) -{ - init_data_t * const idata = IDATA; - int clock_divisor = (CONFIG_CONS_INDEX < 3) ? 115200/baudrate - : (get_bus_freq(0) / 16 / baudrate); - initialise_ns87308(); - idata->console_addr = (void *)NS16550_init((CONFIG_CONS_INDEX - 1), clock_divisor); -} - -void -serial_putc(const char c) -{ - init_data_t * const idata = IDATA; - NS16550_putc((struct NS16550 *) idata->console_addr, c); - if(c == '\n') NS16550_putc((struct NS16550 *) idata->console_addr, '\r'); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - init_data_t * const idata = IDATA; - return NS16550_getc((struct NS16550 *) idata->console_addr); -} - -int -serial_tstc(void) -{ - init_data_t * const idata = IDATA; - return NS16550_tstc((struct NS16550 *) idata->console_addr); -} - -void -serial_setbrg (unsigned long dummy, int baudrate) -{ - init_data_t * const idata = IDATA; - int clock_divisor = (CONFIG_CONS_INDEX < 3) ? 115200/baudrate - : (get_bus_freq(0) / 16 / baudrate); - NS16550_reinit((struct NS16550 *) idata->console_addr, clock_divisor); -} diff --git a/board/sandpoint/serial.h b/board/sandpoint/serial.h deleted file mode 100644 index 94ab81e..0000000 --- a/board/sandpoint/serial.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - diff --git a/board/sandpoint/w83c553f.c b/board/sandpoint/w83c553f.c deleted file mode 100644 index aac06e1..0000000 --- a/board/sandpoint/w83c553f.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include "w83c553f.h" diff --git a/board/sandpoint/w83c553f.h b/board/sandpoint/w83c553f.h deleted file mode 100644 index 79fe669..0000000 --- a/board/sandpoint/w83c553f.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - /* winbond access routines and defines*/ - -/* from the winbond data sheet - - The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. - Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. -*/ - -/*ISA bridge configuration space*/ - -#define WINBOND_PCICONTR 0x40 /*pci control reg*/ -#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ -#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ -#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ -#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ -#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ -#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ -#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ -#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ -#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ -#define WINBOND_CDR 0x4c /*Clock Divisor Register*/ -#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ -#define WINBOND_ATSCR 0x4e /*AT System Control register*/ -#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ -#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ -#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ -#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ -#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ - - diff --git a/common/Makefile b/common/Makefile index 05a1605..2999370 100644 --- a/common/Makefile +++ b/common/Makefile @@ -33,7 +33,7 @@ COBJS = board.o main.o command.o environment.o bedbug.o \ cmd_fdc.o cmd_flash.o cmd_i2c.o cmd_ide.o \ cmd_immap.o cmd_jffs2.o cmd_mem.o cmd_mii.o \ cmd_misc.o cmd_net.o cmd_nvedit.o cmd_pcmcia.o \ - cmd_reginfo.o cmd_scsi.o cmd_usb.o \ + cmd_reginfo.o cmd_scsi.o cmd_usb.o cmd_pci.o \ console.o devices.o dlmalloc.o docecc.o \ flash.o hush.o kgdb.o lists.o \ miiphybb.o miiphyutil.o s_record.o \ diff --git a/common/cmd_pci.c b/common/cmd_pci.c new file mode 100644 index 0000000..2f204e8 --- /dev/null +++ b/common/cmd_pci.c @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI routines + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + +unsigned char ShortPCIListing = 0; + +/* + * Follows routines for the output of infos about devices on PCI bus. + */ + +void pciinfo(int BusNum); + +/* + * Subroutine: do_pciinfo + * + * Description: Handler for 'pciinfo' command.. + * + * Inputs: argv[1] may contain the number of the bus to be scanned. + * Default is bus 0. + * + * Return: None + * + */ +int do_pciinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + char *s; + int bus_no = 0; + + if (argc == 2) + { + bus_no = (int)simple_strtoul(argv[1], NULL, 10); + } + + if ((s = getenv("pci_listing")) != NULL) + ShortPCIListing = (strcmp(s, "short") == 0) ? 1 : 0; + else + ShortPCIListing = 0; + + pciinfo(bus_no); + + return 0; +} + +void pci_header_show(pci_dev_t dev); +void pci_header_show_brief(pci_dev_t dev); + +/* + * Subroutine: pciinfo + * + * Description: Show information about devices on PCI bus. + * Depending on the define CFG_SHORT_PCI_LISTING + * the output will be more or less exhaustive. + * + * Inputs: bus_no the number of the bus to be scanned. + * + * Return: None + * + */ +void pciinfo(int BusNum) +{ + int Device; + int Function; + unsigned char HeaderType; + unsigned short VendorID; + pci_dev_t dev; + + printf("Scanning PCI devices on bus %d\n", BusNum); + + if (ShortPCIListing) { + printf("No. VendorId DeviceId Device Class Sub-Class\n"); + printf("________________________________________________________\n"); + } + + for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { + HeaderType = 0; + VendorID = 0; + for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { + /* + * If this is not a multi-function device, we skip the rest. + */ + if (Function && !(HeaderType & 0x80)) + break; + + dev = PCI_BDF(BusNum, Device, Function); + + pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); + if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) + continue; + + pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); + + if (ShortPCIListing) + { + printf("%02d.%d ", Device, Function); + pci_header_show_brief(dev); + } + else + { + printf("\nFound PCI device %d, function %d:\n", + Device, Function); + pci_header_show(dev); + } + } + } +} + +char* pci_classes_str(u8 class) +{ + static char *pci_classes[] = { + "Build before PCI Rev2.0", + "Mass storage controller", + "Network controller ", + "Display controller ", + "Multimedia device ", + "Memory controller ", + "Bridge device ", + "Simple comm. controller", + "Base system peripheral ", + "Input device ", + "Docking station ", + "Processor ", + "Serial bus controller ", + "Reserved entry ", + "Does not fit any class " + }; + + if (class < (sizeof pci_classes / sizeof *pci_classes)) + return pci_classes[(int) class]; + + return "??? "; +} + +/* + * Subroutine: pci_header_show_brief + * + * Description: Reads and prints the header of the + * specified PCI device in short form. + * + * Inputs: dev Bus+Device+Function number + * + * Return: None + * + */ +void pci_header_show_brief(pci_dev_t dev) +{ + u16 vendor, device; + u8 class, subclass; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); + pci_read_config_word(dev, PCI_DEVICE_ID, &device); + pci_read_config_byte(dev, PCI_CLASS_CODE, &class); + pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass); + + printf("0x%.4x 0x%.4x %s 0x%.2x\n", + vendor, device, + pci_classes_str(class), subclass); +} + +/* + * Subroutine: PCI_Header_Show + * + * Description: Reads the header of the specified PCI device. + * + * Inputs: BusDevFunc Bus+Device+Function number + * + * Return: None + * + */ +void pci_header_show(pci_dev_t dev) +{ + u8 _byte, header_type; + u16 _word; + u32 _dword; + +#define PRINT(msg, type, reg) \ + pci_read_config_##type(dev, reg, &_##type); \ + printf(msg, _##type) + +#define PRINT2(msg, type, reg, func) \ + pci_read_config_##type(dev, reg, &_##type); \ + printf(msg, _##type, func(_##type)) + + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); + + PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID); + PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID); + PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND); + PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); + PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); + PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, + pci_classes_str); + PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); + PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); + PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); + PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER); + PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE); + PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST); + PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0); + PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); + + if (header_type & 0x01) { /* PCI-to-PCI bridge */ + PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS); + PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS); + PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS); + PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER); + PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE); + PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT); + PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS); + PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE); + PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT); + PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE); + PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT); + PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32); + PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32); + PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16); + PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16); + PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1); + PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); + PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); + PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL); + } else { /* PCI device */ + PRINT(" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2); + PRINT(" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3); + PRINT(" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4); + PRINT(" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5); + PRINT(" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS); + PRINT(" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID); + PRINT(" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID); + PRINT(" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS); + PRINT(" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); + PRINT(" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); + PRINT(" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT); + PRINT(" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT); + } + +#undef PRINT +#undef PRINT2 +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */ + +#endif /* CONFIG_PCI */ diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index ec3a2e8..cce5486 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -35,13 +35,7 @@ #include #include #include -#ifdef CONFIG_4xx -#include <405gp_pci.h> -#elif defined (CONFIG_BAB750) -#include -#endif - -extern int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); +#include #undef SCSI_DEBUG @@ -192,7 +186,7 @@ void scsi_init(void) { int busdevfunc; - busdevfunc=PCI_Find_Device(SCSI_VEND_ID,SCSI_DEV_ID); /* get PCI Device ID */ + busdevfunc=pci_find_device(SCSI_VEND_ID,SCSI_DEV_ID,0); /* get PCI Device ID */ if(busdevfunc==-1) { printf("Error SCSI Controller (%04X,%04X) not found\n",SCSI_VEND_ID,SCSI_DEV_ID); return; diff --git a/common/command.c b/common/command.c index a6db770..7d7e18f 100644 --- a/common/command.c +++ b/common/command.c @@ -52,6 +52,7 @@ #include /* Floppy support */ #include /* USB support */ #include +#include #include #include /* 4xx DCR register access */ #include diff --git a/cpu/mpc824x/Makefile b/cpu/mpc824x/Makefile index 33768d0..40447a1 100644 --- a/cpu/mpc824x/Makefile +++ b/cpu/mpc824x/Makefile @@ -27,7 +27,7 @@ LIB = lib$(CPU).a START = start.S drivers/i2c/i2c2.o OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ - drivers/epic/epic1.o drivers/i2c/i2c1.o + drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o all: .depend $(START) $(LIB) diff --git a/cpu/mpc824x/pci.c b/cpu/mpc824x/pci.c new file mode 100644 index 0000000..ddb968e --- /dev/null +++ b/cpu/mpc824x/pci.c @@ -0,0 +1,78 @@ +/* + * arch/ppc/kernel/mpc10x_common.c + * + * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, + * Mem ctlr, EPIC, etc. + * + * Author: Mark A. Greer + * mgreer@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +void pci_mpc824x_init (bd_t *bd, struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + CHRP_PCI_MEMORY_BUS, + CHRP_PCI_MEMORY_PHYS, + CHRP_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CHRP_PCI_MEM_BUS, + CHRP_PCI_MEM_PHYS, + CHRP_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + CHRP_ISA_MEM_BUS, + CHRP_ISA_MEM_PHYS, + CHRP_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + CHRP_PCI_IO_BUS, + CHRP_PCI_IO_PHYS, + CHRP_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + CHRP_ISA_IO_BUS, + CHRP_ISA_IO_PHYS, + CHRP_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_indirect(hose, + CHRP_REG_ADDR, + CHRP_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +} + +#endif diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index de80735..a52e05b 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -70,10 +70,7 @@ #include #include <405gp_pci.h> #include - -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) - -void pciinfo(int bus_no); +#include #ifdef CONFIG_405GP @@ -81,392 +78,216 @@ void pciinfo(int bus_no); /*#define DEBUG*/ -/*------------------------------------------------------------------------ -| These are the lowest addresses allowed for PCI configuration. -| They correspond to lowest available I/O and Memory addresses. -| In the case where where multiple PMM regs are being used to map -| different PLB to PCI regions, each region should have it's own -| minimum address. -+-----------------------------------------------------------------------*/ -unsigned long LowestMemAddr1 = MIN_PCI_MEMADDR1; -unsigned long LowestMemAddr2 = MIN_PCI_MEMADDR2; -unsigned long LowestIOAddr = MIN_PCI_PCI_IOADDR; - -unsigned long MaxBusNum = 0; - - /*-----------------------------------------------------------------------------+ | pci_init. Initializes the 405GP PCI Configuration regs. +-----------------------------------------------------------------------------*/ -void pci_init(bd_t *bd) +void pci_405gp_init(bd_t *bd, struct pci_controller *hose) { + int i, reg_num = 0; unsigned short temp_short; - unsigned long ptm1la; - unsigned long ptm1ms; - unsigned long ptm2la; - unsigned long ptm2ms; + unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; +#if defined(CONFIG_CPCI405) + unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart}; + unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1}; +#else + unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; + unsigned long ptmms[2] = {CFG_PCI_PTM2MS, CFG_PCI_PTM2MS}; +#endif +#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) + unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; + unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; + unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; + unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; +#else + unsigned long pmmla[3] = {0x80000000, 0,0}; + unsigned long pmmma[3] = {0xC0000001, 0,0}; + unsigned long pmmpcila[3] = {0x80000000, 0,0}; + unsigned long pmmpciha[3] = {0x00000000, 0,0}; +#endif - /*--------------------------------------------------------------------------+ - | 405GP PCI Master configuration. - | Map one 512 MB range of PLB/processor addresses to PCI memory space. - | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF - | Use byte reversed out routines to handle endianess. - +--------------------------------------------------------------------------*/ - out32r(PMM0MA, 0x00000000); /* ensure disabled b4 setting PMM0LA */ - out32r(PMM0LA, 0x80000000); - out32r(PMM0PCILA, 0x80000000); - out32r(PMM0PCIHA, 0x00000000); - out32r(PMM0MA, 0xC0000001); /* no prefetching, and enable region */ + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MIN_PCI_PCI_IOADDR, + MIN_PLB_PCI_IOADDR, + 0x10000, + PCI_REGION_IO); + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0xe8800000, + 0x03ffffff, + 0x02800000, + PCI_REGION_IO); + + reg_num = 2; + + /* Memory spaces */ + for (i=0; i<2; i++) + if (ptmms[i] & 1) + { + if (!i) hose->pci_fb = hose->regions + reg_num; + + pci_set_region(hose->regions + reg_num++, + ptmpcila[i], ptmla[i], + ~(ptmms[i] & 0xfffff000) + 1, + PCI_REGION_MEM | + PCI_REGION_MEMORY); + } + + /* PCI memory spaces */ + for (i=0; i<3; i++) + if (pmmma[i] & 1) + { + pci_set_region(hose->regions + reg_num++, + pmmpcila[i], pmmla[i], + ~(pmmma[i] & 0xfffff000) + 1, + PCI_REGION_MEM); + } + + hose->region_count = reg_num; + + pci_setup_indirect(hose, + PCICFGADR, + PCICFGDATA); + + if (hose->pci_fb) + pciauto_region_init(hose->pci_fb); + + pci_register_hose(hose); /*--------------------------------------------------------------------------+ - | PMM1 is not used. Initialize them to zero. - +--------------------------------------------------------------------------*/ - out32r(PMM1MA, 0x00000000); /* ensure disabled b4 setting PMM2LA */ - out32r(PMM1LA, 0x00000000); - out32r(PMM1PCILA, 0x00000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0x00000000); /* not enabled */ + | 405GP PCI Master configuration. + | Map one 512 MB range of PLB/processor addresses to PCI memory space. + | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF + | Use byte reversed out routines to handle endianess. + +--------------------------------------------------------------------------*/ + out32r(PMM0MA, pmmma[0]); /* ensure disabled b4 setting PMM0LA */ + out32r(PMM0LA, pmmla[0]); + out32r(PMM0PCILA, pmmpcila[0]); + out32r(PMM0PCIHA, pmmpciha[0]); + out32r(PMM0MA, pmmma[0]); /*--------------------------------------------------------------------------+ - | PMM2 is not used. Initialize them to zero. - +--------------------------------------------------------------------------*/ - out32r(PMM2MA, 0x00000000); /* ensure disabled b4 setting PMM2LA */ - out32r(PMM2LA, 0x00000000); - out32r(PMM2PCILA, 0x00000000); - out32r(PMM2PCIHA, 0x00000000); - out32r(PMM2MA, 0x00000000); /* not enabled */ + | PMM1 is not used. Initialize them to zero. + +--------------------------------------------------------------------------*/ + out32r(PMM1MA, pmmma[1]); /* ensure disabled b4 setting PMM2LA */ + out32r(PMM1LA, pmmla[1]); + out32r(PMM1PCILA, pmmpcila[1]); + out32r(PMM1PCIHA, pmmpciha[1]); + out32r(PMM1MA, pmmma[1]); - /* - * Set target configuration register - */ -#ifdef CONFIG_CPCI405 - /* generate target config regs from memory and flash size on cpci405 */ - ptm1la = bd->bi_memstart; - ptm1ms = ~(bd->bi_memsize - 1) | 1; - ptm2la = bd->bi_flashstart; - ptm2ms = ~(bd->bi_flashsize - 1) | 1; -#else - /* else, use config values */ - ptm1la = CFG_PCI_PTM1LA; - ptm1ms = CFG_PCI_PTM1MS; - ptm2la = CFG_PCI_PTM2LA; - ptm2ms = CFG_PCI_PTM2MS; -#endif + /*--------------------------------------------------------------------------+ + | PMM2 is not used. Initialize them to zero. + +--------------------------------------------------------------------------*/ + out32r(PMM2MA, pmmma[2]); /* ensure disabled b4 setting PMM2LA */ + out32r(PMM2LA, pmmla[2]); + out32r(PMM2PCILA, pmmpcila[2]); + out32r(PMM2PCIHA, pmmpciha[2]); + out32r(PMM2MA, pmmma[2]); /*--------------------------------------------------------------------------+ - | 405GP PCI Target configuration. (PTM1) - | Note: PTM1MS is hardwire enabled but we set the enable bit anyway. - +--------------------------------------------------------------------------*/ - out32r(PTM1LA, ptm1la); /* insert address */ - out32r(PTM1MS, ptm1ms); /* insert size, enable bit is 1 */ + | 405GP PCI Target configuration. (PTM1) + | Note: PTM1MS is hardwire enabled but we set the enable bit anyway. + +--------------------------------------------------------------------------*/ + out32r(PTM1LA, ptmla[0]); /* insert address */ + out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ /*--------------------------------------------------------------------------+ - | 405GP PCI Target configuration. (PTM2) - +--------------------------------------------------------------------------*/ - out32r(PTM2LA, ptm2la); /* insert address */ - if (ptm2ms == 0) + | 405GP PCI Target configuration. (PTM2) + +--------------------------------------------------------------------------*/ + out32r(PTM2LA, ptmla[1]); /* insert address */ + if (ptmms[1] == 0) { out32r(PTM2MS, 0x00000001); /* set enable bit */ - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCIBASEADDR2, 0x00000000, 4); + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); out32r(PTM2MS, 0x00000000); /* disable */ } else { - out32r(PTM2MS, ptm2ms); /* insert size, enable bit is 1 */ + out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ } /* * Insert Subsystem Vendor and Device ID */ - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSVENDORID, CFG_PCI_SUBSYS_VENDORID, 2); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); #ifdef CONFIG_CPCI405 if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSDEVICEID, CFG_PCI_SUBSYS_DEVICEID, 2); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); else - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSDEVICEID, CFG_PCI_SUBSYS_DEVICEID2, 2); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); #else - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSDEVICEID, CFG_PCI_SUBSYS_DEVICEID, 2); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); #endif #if 0 /* test-only: no need yet! */ /*--------------------------------------------------------------------------+ - | If PCI speed = 66Mhz, set 66Mhz capable bit. - +--------------------------------------------------------------------------*/ + | If PCI speed = 66Mhz, set 66Mhz capable bit. + +--------------------------------------------------------------------------*/ if (board_cfg.pci_speed==66666666) { - temp_short = PCI_Read_CFG_Reg(PCIDEVID_405GP, PCISTATUS, 2); - PCI_Write_CFG_Reg(PCIDEVID_405GP,PCISTATUS,(temp_short|CAPABLE_66MHZ), 2); + pci_read_config_word(PCIDEVID_405GP, PCISTATUS, &temp_short); + pci_write_config_word(PCIDEVID_405GP,PCISTATUS,(temp_short|CAPABLE_66MHZ)); + } +#endif + +#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTOR) +#if (CONFIG_PCI_HOSE == PCI_HOST_AUTO) + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) +#endif + { + /*--------------------------------------------------------------------------+ + | Write the 405GP PCI Configuration regs. + | Enable 405GP to be a master on the PCI bus (PMM). + | Enable 405GP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } #endif /* * Set HCE bit (Host Configuration Enabled) */ - temp_short = PCI_Read_CFG_Reg(PCIDEVID_405GP, PCIBRDGOPT2, 2); - PCI_Write_CFG_Reg(PCIDEVID_405GP, PCIBRDGOPT2,(temp_short | 0x0001), 2); + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); #ifdef CONFIG_PCI_PNP /*--------------------------------------------------------------------------+ - | Scan the PCI bus and configure devices found. - +--------------------------------------------------------------------------*/ -# if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + | Scan the PCI bus and configure devices found. + +--------------------------------------------------------------------------*/ +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) if (mfdcr(strap) & PSR_PCI_ARBIT_EN) -# endif +#endif { -# ifdef CONFIG_PCI_SCAN_SHOW +#ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); -# endif - PCI_Scan(0); - } -#endif /* CONFIG_PCI_PNP */ - -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Read_CFG_Reg -| Description: Read a PCI configuration register -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Width Number of bytes to read (1, 2, or 4) -| Return value: -| (unsigned int) Value of the configuration register read. -| For reads shorter than 4 bytes, return value -| is LSB-justified -+-----------------------------------------------------------------------------*/ -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width) -{ - unsigned int RegAddr; - - /*--------------------------------------------------------------------------+ - | bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) - +--------------------------------------------------------------------------*/ - RegAddr = 0x80000000 | ((Reg|BusDevFunc) & 0xFFFFFFFC); - - /*--------------------------------------------------------------------------+ - | Write reg to PCI Config Address - +--------------------------------------------------------------------------*/ - out32r(PCICFGADR, RegAddr); - - /*--------------------------------------------------------------------------+ - | Read reg value from PCI Config Data - +--------------------------------------------------------------------------*/ - switch (Width) - { - case 1: return ((unsigned int) in8(PCICFGDATA | (Reg & 0x3))); - case 2: return ((unsigned int) in16r(PCICFGDATA | (Reg & 0x3))); - case 4: return (in32r(PCICFGDATA | (Reg & 0x3))); - } - - return 0; /* not reached: just to satisfy the compiler */ -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: PCI_Write_CFG_Reg -| Description: Write a PCI configuration register. -| Inputs: -| BusDevFunc PCI Bus+Device+Function number -| Reg Configuration register number -| Value Configuration register value -| Width Number of bytes to write (1, 2, or 4) -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width) -{ - unsigned int RegAddr; - unsigned int msr; - - /*--------------------------------------------------------------------------+ - | Ensure interrupts disabled for pass2 errata #6. - +--------------------------------------------------------------------------*/ - msr = mfmsr(); - mtmsr(msr & ~(MSR_EE|MSR_CE)); - - /*--------------------------------------------------------------------------+ - | bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) - +--------------------------------------------------------------------------*/ - RegAddr = 0x80000000 | ((Reg|BusDevFunc) & 0xFFFFFFFC); - - /*--------------------------------------------------------------------------+ - | Write reg to PCI Config Address - +--------------------------------------------------------------------------*/ - out32r(PCICFGADR, RegAddr); +#endif - /*--------------------------------------------------------------------------+ - | Write reg value to PCI Config Data - +--------------------------------------------------------------------------*/ - switch (Width) - { - case 1: out8(PCICFGDATA | (Reg & 0x3), (unsigned char)(Value & 0xFF)); - break; - case 2: out16r(PCICFGDATA | (Reg & 0x3),(unsigned short)(Value & 0xFFFF)); - break; - case 4: out32r(PCICFGDATA | (Reg & 0x3), Value); - break; + hose->last_busno = pci_hose_scan(hose); } +#endif /* CONFIG_PCI_PNP */ - /*--------------------------------------------------------------------------+ - | Write PCI Config Address after writing PCICFGDATA for pass2 errata #6. - +--------------------------------------------------------------------------*/ - out32r(PCICFGADR, 0x00000000); - - /*--------------------------------------------------------------------------+ - | Restore msr (for pass2 errata #6). - +--------------------------------------------------------------------------*/ - mtmsr(msr); - - return (0); } -/*----------------------------------------------------------------------- -| -| Subroutine: PCI_Scan -| -| Prototype: void PCI_Scan(int BusNum) -| -| Description: Scan through all 16 allowable PCI IDs and configure -| those for which the vendor ID indicates there is a -| device present. -| -| Inputs: -| BusNum Bus number where scanning begins -| -| Return value: -| None -| -+----------------------------------------------------------------------*/ -void PCI_Scan(int BusNum) -{ - int Device; - int BusDevFunc; +/* + * + */ - /*--------------------------------------------------------------------------+ - | Start with device 0, the 405GP is device 0. sr: 09-07-2001 - +--------------------------------------------------------------------------*/ - for (Device = 0; Device < MAX_PCI_DEVICES; Device++) - { - BusDevFunc = (BusNum << 16) | (Device << 11); - - if (PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID,2) != 0xFFFF) - { -#ifdef DEBUG - printf("Device %d is present\n",Device); -#endif - switch( PCI_Read_CFG_Reg(BusDevFunc, PCICLASSCODE, 2) ) - { - - case 0x0604: /* PCI-PCI Bridge */ - PCI_Config_Device(BusDevFunc, 2); - PCI_Config_Bridge(BusDevFunc); - break; - - case 0x0300: /* VGA Display controller */ - case 0x0001: /* VGA Display controller (pre PCI rev 2.0)*/ - PCI_Config_VGA_Device(BusDevFunc, 6); - break; - - default: - PCI_Config_Device(BusDevFunc, 6); - } -#ifdef CONFIG_PCI_SCAN_SHOW - /* - * Don't print own pci regs (ppc405gp located @ bus 0, device 0) - */ - if ((BusNum != 0) || (Device != 0)) - { - printf(" %02x %02x %04x %04x %04x %02x\n", - BusNum, - Device, - PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID, 2), - PCI_Read_CFG_Reg(BusDevFunc, PCIDEVICEID, 2), - PCI_Read_CFG_Reg(BusDevFunc, PCICLASSCODE, 2), - PCI_Read_CFG_Reg(BusDevFunc, PCIINTLINE, 1)); - } -#endif - } - else - { -#ifdef DEBUG - printf("Device %d not present\n",Device); -#endif - } - } -} - -/*----------------------------------------------------------------------- -| Subroutine: PCI_Config_Device -| -| Description: Configure a PCI device by examining its I/O and memory -| address space needs and allocating address space to it by -| programming the address decoders in the Base Address Registers. -| -| Inputs: -| BusDevFunc Bus+Device+Function number -| NumBaseAddr Number of base address registers to -| configure -| Return value: -| None -+----------------------------------------------------------------------*/ -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) +void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - int AddrSlot; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val, int_line = 0; - - for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) - { - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 0xFFFFFFFF,4); - - AddrDesc = PCI_Read_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 4); - - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; /* 01/04/99 MCG */ - -#ifdef DEBUG - printf("Read Base Addr Reg %d = 0x%08x\n",AddrSlot,AddrDesc); -#endif - - if ((AddrDesc & 1) == 0) /* Memory */ - { - AddrDesc &= 0xFFFFFFF0; - - AddrDesc = ~AddrDesc + 1; - - if ((unsigned long)AddrDesc < 4096) - AddrDesc = 4096; -#ifdef DEBUG - printf(" PCI Memory space = 0x%x bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_MEMADDR1; AddrProg < LowestMemAddr1; AddrProg += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestMemAddr1 = AddrProg + AddrDesc; - } - else /* I/O */ - { - AddrDesc &= 0xFFFFFFFC; - - AddrDesc = ~AddrDesc + 1; - -#ifdef DEBUG - printf(" PCI I/O space = 0x%x bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_PCI_IOADDR; AddrProg < LowestIOAddr; AddrProg += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestIOAddr = AddrProg + AddrDesc; - } - - } - - Min_Gnt_Val = 0x80; - PCI_Write_CFG_Reg(BusDevFunc, PCILATENCYTIM, Min_Gnt_Val, 1); + unsigned char int_line = 0xff; /* * Write pci interrupt line register (cpci405 specific) */ - switch ((BusDevFunc >> 11) & 0x03) + switch (PCI_DEV(dev) & 0x03) { case 0: int_line = 27 + 2; @@ -481,451 +302,40 @@ void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) int_line = 27 + 1; break; } - PCI_Write_CFG_Reg(BusDevFunc, PCIINTLINE, int_line, 1); - - /* - * Enable i/o space, memory space and master on this device - */ - PCI_Write_CFG_Reg(BusDevFunc, PCICMD, 7, 2); - -} - -/*----------------------------------------------------------------------- -| Subroutine: PCI_Config_VGA_Device -| -| Description: Configure a PCI VGA device by examining its I/O and memory -| address space needs and allocating address space to it by -| programming the address decoders in the Base Address Registers. -| -| Inputs: -| BusDevFunc Bus+Device+Function number -| NumBaseAddr Number of base address registers to -| configure -| Return value: -| None -+----------------------------------------------------------------------*/ -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr) -{ - int AddrSlot; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val; - - for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) - { - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 0xFFFFFFFF,4); - - AddrDesc = PCI_Read_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot), 4); - - if (AddrDesc == 0) /* unimplemented, stop looking */ - continue; /* 01/04/99 MCG */ - -#ifdef DEBUG - printf("Read Base Addr Reg %d = 0x%08x\n",AddrSlot,AddrDesc); -#endif - - if ((AddrDesc & 1) == 0) /* Memory */ - { - AddrDesc &= 0xFFFFFFF0; - - AddrDesc = ~AddrDesc + 1; - - if ((unsigned long)AddrDesc < 4096) - AddrDesc = 4096; -#ifdef DEBUG - printf(" PCI Memory space = 0x%x bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_MEMADDR2; AddrProg < LowestMemAddr2; AddrProg += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestMemAddr2 = AddrProg + AddrDesc; - } - else /* I/O */ - { - AddrDesc &= 0xFFFFFFFC; - - AddrDesc = ~AddrDesc + 1; - -#ifdef DEBUG - printf(" PCI I/O space = 0x%x bytes \n",AddrDesc); -#endif - for (AddrProg = MIN_PCI_PCI_IOADDR; AddrProg < LowestIOAddr; AddrProg - += AddrDesc); - - PCI_Write_CFG_Reg(BusDevFunc, PCIBASEADDR0 + (4*AddrSlot),AddrProg,4); - LowestIOAddr = AddrProg + AddrDesc; - } - - } - - Min_Gnt_Val = 0x80; - PCI_Write_CFG_Reg(BusDevFunc, PCILATENCYTIM, Min_Gnt_Val, 1); -} - -/*----------------------------------------------------------------------- -| -| Subroutine: PCI_Config_Bridge -| -| Prototype: void PCI_Config_Bridge(int BusDevFunc) -| -| Description: Configure a PCI-PCI bridge -| -| Inputs: -| BusDevFunc Bus+Device+Function number -| -| Return value: -| None -| -+----------------------------------------------------------------------*/ -void PCI_Config_Bridge(int BusDevFunc) -{ - int SecondaryBus; - int PrimaryBus; - int CommandReg_Val; - int InitialLowestIOAddr, InitialLowestMemAddr; - int IOBase, MemBase; - int IOLimit, MemLimit; - - InitialLowestIOAddr = LowestIOAddr; - InitialLowestMemAddr = LowestMemAddr1; - - CommandReg_Val = PCI_Read_CFG_Reg(BusDevFunc, PCICMD, 2); - - /* Configure bridge's base address registers */ - - PCI_Config_Device(BusDevFunc, 2); - - if ( LowestIOAddr > InitialLowestIOAddr ) /* bridge uses IO space? */ - CommandReg_Val |= 0x01; /* enable I/O Space */ - - if ( LowestMemAddr1 > InitialLowestMemAddr ) /* bridge uses memory space? */ - CommandReg_Val |= 0x02; /* enable Memory Space */ - - PrimaryBus = (BusDevFunc >> 16) & 0xFF; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_PRIMARYBUS, PrimaryBus, 1); - - SecondaryBus = ++MaxBusNum; - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SECONDARYBUS, SecondaryBus, 1); - - /* Start with max. possible value for subordinate bus number */ - /* Later, after any additional child busses are found, we'll update this */ - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, 0xFF, 1); - - /* IO Base must be on 4Kb boundary. Adjust if needed */ - - if ((LowestIOAddr % 4096) != 0) - LowestIOAddr += 4096 - (LowestIOAddr % 4096); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOBASE, (LowestIOAddr>>8) & 0xF0, 1); - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOBASEUPPER16, (LowestIOAddr>>16) & 0xFFFF, 2); - - IOBase = LowestIOAddr; - - /* Mem Base must be on 1 MB boundary. adjust if needed */ - if ((LowestMemAddr1 % 0x100000) != 0) - LowestMemAddr1 += 0x100000 - (LowestMemAddr1 % 0x100000); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_MEMBASE, (LowestMemAddr1>>16) & 0xFFF0, 2); - MemBase = LowestMemAddr1; - - PCI_Scan(SecondaryBus); - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_SUBORDINATEBUS, MaxBusNum, 1); - - IOLimit = LowestIOAddr; - if (LowestIOAddr > IOBase) /* IO space used on secondary bus? */ - { - CommandReg_Val |= 0x01; /* enable IO Space */ - IOLimit--; /* IOLimit is highest used address */ - } - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOLIMIT, ((IOLimit)>>8) & 0xF0, 1); - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOLIMITUPPER16, ((IOLimit)>>16) & 0xFFFF, 2); - - /* IOLIMIT is the starting address of a 4K block forwarded by the bridge. */ - /* Round LowestIOAddr up to the next 4K boundary if IO space is enabled. */ - - if ((CommandReg_Val & 0x01) == 0x01) - LowestIOAddr = (IOLimit | 0xFFF) + 1; - - MemLimit = LowestMemAddr1; - if ( LowestMemAddr1 > MemBase ) /* mem. space is used on secondary bus? */ - { - CommandReg_Val |= 0x02; /* enable Memory Space */ - MemLimit--; /* MemLimit is highest used address */ - } - - PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_MEMLIMIT, ((MemLimit)>>16) & 0xFFF0, 2); - - /* MEMLIMIT is the starting address of a 1M block forwarded by the bridge. */ - /* Round LowestMemAddr up to the next 1M boundary if Memory space is enabled. */ - - if ( (CommandReg_Val & 0x02) == 0x02 ) - LowestMemAddr1 = (MemLimit | 0xFFFFF) + 1; - - /* Enable Bus Master on secondary bus */ - CommandReg_Val |= 0x04; - - PCI_Write_CFG_Reg(BusDevFunc, PCICMD, CommandReg_Val, 2); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, int_line); } -/*----------------------------------------------------------------------- -| Subroutine: PCI_Find_Device -| -| Prototype: int PCI_Find_Device(hword VendorID, hword DeviceID); -| -| Description: -| Locate a PCI device by vendor and device number -| -| Inputs: -| VendorID Value of the device's Vendor ID field -| DeviceID Value of the device's Device ID field -| -| Return value: -| < 0 Device not found -| (int) PCI Bus+Device+Function number -+----------------------------------------------------------------------*/ -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID) +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) { - int Device; - int BusDevFunc; - int BusNum; - - for (BusNum = MaxBusNum; BusNum >= 0; BusNum--) - for (Device = 0; Device < MAX_PCI_DEVICES; Device++) - { - BusDevFunc = (BusNum << 16) | (Device << 11); - - if (PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID, 2) == VendorID - && PCI_Read_CFG_Reg(BusDevFunc, PCIDEVICEID, 2) == DeviceID) - return (BusDevFunc); - } - - return (-1); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCI) - -int -do_pciinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - int bus_no = 0; - - if (argc == 2) - { - bus_no = (int)simple_strtoul(argv[1], NULL, 10); - } - - pciinfo(bus_no); - return 0; -} - - -/******************************************************************************* -* -* pciinfo - print information about PCI devices -* -*/ -void -pciinfo(int bus_no) -{ - int device_no; - unsigned short vendor_id; - int BusDevFunc; - int device_no_start = 0; - - printf ("Scanning function 0 of each PCI device on bus %d\n", bus_no); - - if (bus_no == 0) - device_no_start = 0; - for (device_no=device_no_start; device_no < MAX_PCI_DEVICES; device_no++) - { - BusDevFunc = (bus_no << 16) | (device_no << 11); - vendor_id = PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID, 2); - - if (vendor_id != 0xffff) - { - printf("\nFound PCI device %d:\n", device_no); - pciHeaderShow(BusDevFunc); - } - } + pciauto_setup_device(hose, dev, 6, hose->pci_fb, hose->pci_io); } +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) -/******************************************************************************* -* -* pciHeaderShow - print a header of the specified PCI device -* -* This routine prints a header of the PCI device specified by BusDevFunc. -* -*/ -void -pciHeaderShow(int BusDevFunc) -{ - PCI_HEADER_DEVICE headerDevice; - PCI_HEADER_BRIDGE headerBridge; - PCI_HEADER_DEVICE * pD = &headerDevice; - PCI_HEADER_BRIDGE * pB = &headerBridge; +static struct pci_config_table pci_405gp_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - if (pD->headerType & 0x01) /* PCI-to-PCI bridge */ - { - pB->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pB->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pB->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pB->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 2); - pB->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pB->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pB->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pB->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pB->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pB->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pB->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pB->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pB->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pB->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pB->priBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRIMARY_BUS, 1); - pB->secBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SECONDARY_BUS, 1); - pB->subBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBORDINATE_BUS, 1); - pB->secLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_LATENCY, 1); - pB->ioBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE, 1); - pB->ioLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT, 1); - pB->secStatus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_STATUS, 2); - pB->memBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_BASE, 2); - pB->memLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_LIMIT, 2); - pB->preBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE, 2); - pB->preLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT, 2); - pB->preBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE_U, 4); - pB->preLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT_U, 4); - pB->ioBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE_U, 2); - pB->ioLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT_U, 2); - pB->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_ROM_BASE, 4); - pB->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_LINE, 1); - pB->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_PIN, 1); - pB->control = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRIDGE_CONTROL, 2); - pciBheaderPrint(pB); - } - else /* PCI device */ - { - pD->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2); - pD->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2); - pD->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2); - pD->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 1); - pD->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1); - pD->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1); - pD->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1); - pD->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1); - pD->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1); - pD->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1); - pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1); - pD->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1); - pD->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4); - pD->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4); - pD->base2 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_2, 4); - pD->base3 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_3, 4); - pD->base4 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_4, 4); - pD->base5 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_5, 4); - pD->cis = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CIS, 4); - pD->subVendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_VENDER_ID, 2); - pD->subSystemId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_SYSTEM_ID, 2); - pD->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4); - pD->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 1); - pD->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1); - pD->minGrant = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MIN_GRANT, 1); - pD->maxLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MAX_LATENCY, 1); - pciDheaderPrint(pD); - } -} + { } +}; -/******************************************************************************* -* -* pciDheaderPrint - print a PCI device header -* -* This routine prints a PCI device header. -* -*/ -void -pciDheaderPrint(PCI_HEADER_DEVICE * pD) -{ - printf (" vendor ID = 0x%.4x\n", (ushort)pD->vendorId); - printf (" device ID = 0x%.4x\n", (ushort)pD->deviceId); - printf (" command register = 0x%.4x\n", (ushort)pD->command); - printf (" status register = 0x%.4x\n", (ushort)pD->status); - printf (" revision ID = 0x%.2x\n", (uchar)pD->revisionId); - printf (" class code = 0x%.2x\n", (uchar)pD->classCode); - printf (" sub class code = 0x%.2x\n", (uchar)pD->subClass); - printf (" programming interface = 0x%.2x\n", (uchar)pD->progIf); - printf (" cache line = 0x%.2x\n", (uchar)pD->cacheLine); - printf (" latency time = 0x%.2x\n", (uchar)pD->latency); - printf (" header type = 0x%.2x\n", (uchar)pD->headerType); - printf (" BIST = 0x%.2x\n", (uchar)pD->bist); - printf (" base address 0 = 0x%.8x\n", pD->base0); - printf (" base address 1 = 0x%.8x\n", pD->base1); - printf (" base address 2 = 0x%.8x\n", pD->base2); - printf (" base address 3 = 0x%.8x\n", pD->base3); - printf (" base address 4 = 0x%.8x\n", pD->base4); - printf (" base address 5 = 0x%.8x\n", pD->base5); - printf (" cardBus CIS pointer = 0x%.8x\n", pD->cis); - printf (" sub system vendor ID = 0x%.4x\n", (ushort)pD->subVendorId); - printf (" sub system ID = 0x%.4x\n", (ushort)pD->subSystemId); - printf (" expansion ROM base address = 0x%.8x\n", pD->romBase); - printf (" interrupt line = 0x%.2x\n", (uchar)pD->intLine); - printf (" interrupt pin = 0x%.2x\n", (uchar)pD->intPin); - printf (" min Grant = 0x%.2x\n", (uchar)pD->minGrant); - printf (" max Latency = 0x%.2x\n", (uchar)pD->maxLatency); -} +static struct pci_controller hose = { + fixup_irq: pci_405gp_fixup_irq, + config_table: pci_405gp_config_table, +}; -/******************************************************************************* -* -* pciBheaderPrint - print a PCI-to-PCI bridge header -* -* This routine prints a PCI-to-PCI bridge header. -* -*/ -void -pciBheaderPrint(PCI_HEADER_BRIDGE * pB) +void pci_init(bd_t *bd) { - printf (" vendor ID = 0x%.4x\n", (ushort)pB->vendorId); - printf (" device ID = 0x%.4x\n", (ushort)pB->deviceId); - printf (" command register = 0x%.4x\n", (ushort)pB->command); - printf (" status register = 0x%.4x\n", (ushort)pB->status); - printf (" revision ID = 0x%.2x\n", (uchar)pB->revisionId); - printf (" class code = 0x%.2x\n", (uchar)pB->classCode); - printf (" sub class code = 0x%.2x\n", (uchar)pB->subClass); - printf (" programming interface = 0x%.2x\n", (uchar)pB->progIf); - printf (" cache line = 0x%.2x\n", (uchar)pB->cacheLine); - printf (" latency time = 0x%.2x\n", (uchar)pB->latency); - printf (" header type = 0x%.2x\n", (uchar)pB->headerType); - printf (" BIST = 0x%.2x\n", (uchar)pB->bist); - printf (" base address 0 = 0x%.8x\n", pB->base0); - printf (" base address 1 = 0x%.8x\n", pB->base1); - printf (" primary bus number = 0x%.2x\n", (uchar)pB->priBus); - printf (" secondary bus number = 0x%.2x\n", (uchar)pB->secBus); - printf (" subordinate bus number = 0x%.2x\n", (uchar)pB->subBus); - printf (" secondary latency timer = 0x%.2x\n", (uchar)pB->secLatency); - printf (" IO base = 0x%.2x\n", (uchar)pB->ioBase); - printf (" IO limit = 0x%.2x\n", (uchar)pB->ioLimit); - printf (" secondary status = 0x%.4x\n", (ushort)pB->secStatus); - printf (" memory base = 0x%.4x\n", (ushort)pB->memBase); - printf (" memory limit = 0x%.4x\n", (ushort)pB->memLimit); - printf (" prefetch memory base = 0x%.4x\n", (ushort)pB->preBase); - printf (" prefetch memory limit = 0x%.4x\n", (ushort)pB->preLimit); - printf (" prefetch memory base upper = 0x%.8x\n", pB->preBaseUpper); - printf (" prefetch memory limit upper = 0x%.8x\n", pB->preLimitUpper); - printf (" IO base upper 16 bits = 0x%.4x\n", (ushort)pB->ioBaseUpper); - printf (" IO limit upper 16 bits = 0x%.4x\n", (ushort)pB->ioLimitUpper); - printf (" expansion ROM base address = 0x%.8x\n", pB->romBase); - printf (" interrupt line = 0x%.2x\n", (uchar)pB->intLine); - printf (" interrupt pin = 0x%.2x\n", (uchar)pB->intPin); - printf (" bridge control = 0x%.4x\n", (ushort)pB->control); + pci_405gp_init(bd, &hose); } -#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ +#endif #endif /* CONFIG_PCI */ #endif /* CONFIG_405GP */ - -#endif /* CONFIG_PIP405 */ diff --git a/drivers/Makefile b/drivers/Makefile new file mode 100644 index 0000000..13be050 --- /dev/null +++ b/drivers/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libdrivers.a + +OBJS = ns87308.o ns16550.o serial.o pci_auto.o pci.o pci_indirect.o \ + eepro100.o dc2114x.o w83c553f.o sym53c8xx.o +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pcippc2/dc2114x.c b/drivers/dc2114x.c similarity index 55% rename from board/pcippc2/dc2114x.c rename to drivers/dc2114x.c index bd01d69..8c03ec5 100644 --- a/board/pcippc2/dc2114x.c +++ b/drivers/dc2114x.c @@ -19,37 +19,33 @@ */ #include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_TULIP) + #include #include - -#include "pci.h" +#include #undef DEBUG +#undef DEBUG_SROM +#undef DEBUG_SROM2 -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_TULIP) +#undef UPDATE_SROM /* PCI Registers. */ #define PCI_CFDA_PSM 0x43 #define CFRV_RN 0x000000f0 /* Revision Number */ -#define CBIO_MASK 0xffffff80 #define WAKEUP 0x00 /* Power Saving Wakeup */ #define SLEEP 0x80 /* Power Saving Sleep Mode */ - -#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ -#define DC2114x_DID 0x0009 /* Unique Device ID # */ #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ -#define DC21142 (DC2114x_DID << 8 | 0x0010) -#define DC21143 (DC2114x_DID << 8 | 0x0030) - -#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) /* Ethernet chip registers. - */ + */ #define DE4X5_BMR 0x000 /* Bus Mode Register */ #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ @@ -60,7 +56,7 @@ #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ /* Register bits. - */ + */ #define BMR_SWR 0x00000001 /* Software Reset */ #define STS_TS 0x00700000 /* Transmit Process State */ #define STS_RS 0x000e0000 /* Receive Process State */ @@ -71,7 +67,7 @@ #define OMR_PM 0x00000080 /* Pass All Multicast */ /* Descriptor bits. - */ + */ #define R_OWN 0x80000000 /* Own Bit */ #define RD_RER 0x02000000 /* Receive End Of Ring */ #define RD_LS 0x00000100 /* Last Descriptor */ @@ -83,9 +79,17 @@ #define TD_ES 0x00008000 /* Error Summary */ #define TD_SET 0x08000000 /* Setup Packet */ +/* The EEPROM commands include the alway-set leading bit. */ +#define SROM_WRITE_CMD 5 +#define SROM_READ_CMD 6 +#define SROM_ERASE_CMD 7 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ #define SROM_RD 0x00004000 /* Read from Boot ROM */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x4801 +#define EE_WRITE_1 0x4805 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ #define SROM_SR 0x00000800 /* Select Serial ROM when set */ #define DT_IN 0x00000004 /* Serial Data In */ @@ -145,80 +149,121 @@ static int tx_new; /* TX descriptor ring pointer */ static char rxRingSize; static char txRingSize; -static void send_setup_frame(struct eth_device* dev, bd_t * bis); -static void read_hw_addr(struct eth_device* dev, bd_t * bis); -static short srom_rd(struct eth_device* dev, u_long address, u_char offset); -static void srom_latch(struct eth_device* dev, u_int command, u_long address); -static void srom_command(struct eth_device* dev, u_int command, u_long address); -static void srom_address(struct eth_device* dev, u_int command, u_long address, u_char offset); -static short srom_data(struct eth_device* dev, u_int command, u_long address); static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); static int getfrom_srom(struct eth_device* dev, u_long addr); +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len); +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len); +static int read_srom(struct eth_device *dev, u_long ioaddr, int index); +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); +static void update_srom(struct eth_device *dev, bd_t *bis); +#endif +static void read_hw_addr(struct eth_device* dev, bd_t * bis); +static void send_setup_frame(struct eth_device* dev, bd_t * bis); static int dc21x4x_init(struct eth_device* dev, bd_t* bis); static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); static int dc21x4x_recv(struct eth_device* dev); static void dc21x4x_halt(struct eth_device* dev); +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + static int INL(struct eth_device* dev, u_long addr) { - return le32_to_cpu(*(volatile u_long *)pci_mem_to_phys(addr + dev->iobase)); + return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); } static void OUTL(struct eth_device* dev, int command, u_long addr) { - *(volatile u_long *)pci_mem_to_phys(addr + dev->iobase) = cpu_to_le32(command); + *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); } +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, + { } +}; + int dc21x4x_initialize(bd_t *bis) { - int card_number, i, status = 0; - int device; + int idx=0; + int card_number = 0; int cfrv; unsigned char timer; - int devbusfn; - u_long iobase; + pci_dev_t devbusfn; + unsigned int iobase; + unsigned short status; struct eth_device* dev; - for(card_number=i=0; ; i++) { - devbusfn = PCI_Find_Device(DC2114x_VID, DC2114x_DID, i); + while(1) { + devbusfn = pci_find_devices(supported, idx++); if (devbusfn == -1) { break; } /* Get the chip configuration revision register. */ - cfrv = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_REVISION, 4); - - device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); + pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); - if (device != DC21143) { + if ((cfrv & CFRV_RN) < DC2114x_BRK ) { printf("Error: The chip is not DC21143.\n"); continue; } - status = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_COMMAND, 2); - status |= PCI_CMD_MASTER | PCI_CMD_IOEN | PCI_CMD_MEMEN; - PCI_Write_CFG_Reg(devbusfn, PCI_CFG_COMMAND, status, 2); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + status |= +#ifdef CONFIG_TULIP_USE_IO + PCI_COMMAND_IO | +#else + PCI_COMMAND_MEMORY | +#endif + PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, status); + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } /* Check the latency timer for values >= 0x60. */ - timer = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_LATENCY_TIMER, 1); + pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); if (timer < 0x60) { - PCI_Write_CFG_Reg(devbusfn, PCI_CFG_LATENCY_TIMER, 0x60, 1); + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); } +#ifdef CONFIG_TULIP_USE_IO + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_IO_MASK; +#else /* read BAR for memory space access */ - iobase = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_BASE_ADDRESS_1, 4); - iobase &= CBIO_MASK; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; +#endif #ifdef DEBUG - printf("dc21x4x: DEC 21142 PCI Device @0x%lx\n", iobase); + printf("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); #endif dev = (struct eth_device*) malloc(sizeof *dev); - sprintf(dev->name, "dc21x4x#%d", i); - dev->iobase = iobase; + sprintf(dev->name, "dc21x4x#%d", card_number); +#ifdef CONFIG_TULIP_USE_IO + dev->iobase = pci_io_to_phys(devbusfn, iobase); +#else + dev->iobase = pci_mem_to_phys(devbusfn, iobase); +#endif dev->priv = (void*) devbusfn; dev->init = dc21x4x_init; dev->halt = dc21x4x_halt; @@ -226,7 +271,7 @@ int dc21x4x_initialize(bd_t *bis) dev->recv = dc21x4x_recv; /* Ensure we're not sleeping. */ - PCI_Write_CFG_Reg(devbusfn, PCI_CFDA_PSM, WAKEUP, 1); + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); udelay(10 * 1000); @@ -246,7 +291,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) int devbusfn = (int) dev->priv; /* Ensure we're not sleeping. */ - PCI_Write_CFG_Reg(devbusfn, PCI_CFDA_PSM, WAKEUP, 1); + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); RESET_DE4X5(dev); @@ -260,7 +305,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) for (i = 0; i < NUM_RX_DESC; i++) { rx_ring[i].status = cpu_to_le32(R_OWN); rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); - rx_ring[i].buf = cpu_to_le32(pci_ram_to_mem((u32) NetRxPackets[i])); + rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); rx_ring[i].next = 0; } @@ -279,8 +324,8 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); /* Tell the adapter where the TX/RX rings are located. */ - OUTL(dev, pci_ram_to_mem((u32) &rx_ring), DE4X5_RRBA); - OUTL(dev, pci_ram_to_mem((u32) &tx_ring), DE4X5_TRBA); + OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); + OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); START_DE4X5(dev); @@ -309,7 +354,7 @@ static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int lengt } } - tx_ring[tx_new].buf = cpu_to_le32(pci_ram_to_mem((u32) packet)); + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); tx_ring[tx_new].status = cpu_to_le32(T_OWN); @@ -322,13 +367,13 @@ static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int lengt } } -#if 0 /* test-only */ if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { +#if 0 /* test-only */ printf("TX error status = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); +#endif goto Done; } -#endif status = length; @@ -387,48 +432,8 @@ static void dc21x4x_halt(struct eth_device* dev) STOP_DE4X5(dev); OUTL(dev, 0, DE4X5_SICR); - if (devbusfn > 0) { - PCI_Write_CFG_Reg(devbusfn, PCI_CFDA_PSM, SLEEP, 1); - } -} - -static void read_hw_addr(struct eth_device *dev, bd_t *bis) -{ - u_short tmp, *p = (short *)(&dev->enetaddr[0]); - int i, j = 0; - for (i = 0; i < (ETH_ALEN >> 1); i++) { - tmp = srom_rd(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i); - *p = le16_to_cpu(tmp); - j += *p++; - } - - if ((j == 0) || (j == 0x2fffd)) { - printf("Warning: can't read HW address from SROM.\n"); - goto Done; - } - -#ifdef DEBUG - for (i = 0; i < ETH_ALEN; i++) { - if (dev->enetaddr[i] != bis->bi_enetaddr[i]) { - printf("Warning: HW addresses don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - dev->enetaddr[0], dev->enetaddr[1], - dev->enetaddr[2], dev->enetaddr[3], - dev->enetaddr[4], dev->enetaddr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - goto Done; - } - } -#endif - -Done: - return; + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); } static void send_setup_frame(struct eth_device* dev, bd_t *bis) @@ -453,7 +458,7 @@ static void send_setup_frame(struct eth_device* dev, bd_t *bis) } } - tx_ring[tx_new].buf = cpu_to_le32(pci_ram_to_mem((u32) &setup_frame[0])); + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); tx_ring[tx_new].status = cpu_to_le32(T_OWN); @@ -473,89 +478,253 @@ Done: return; } -/* SROM Read. +/* SROM Read and write routines. */ -static short -srom_rd(struct eth_device* dev, u_long addr, u_char offset) -{ - sendto_srom(dev, SROM_RD | SROM_SR, addr); - - srom_latch(dev, SROM_RD | SROM_SR | DT_CS, addr); - srom_command(dev, SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - srom_address(dev, SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data(dev, SROM_RD | SROM_SR | DT_CS, addr); -} static void -srom_latch(struct eth_device* dev, u_int command, u_long addr) +sendto_srom(struct eth_device* dev, u_int command, u_long addr) { - sendto_srom(dev, command, addr); - sendto_srom(dev, command | DT_CLK, addr); - sendto_srom(dev, command, addr); + OUTL(dev, command, addr); + udelay(1); } -static void -srom_command(struct eth_device* dev, u_int command, u_long addr) +static int +getfrom_srom(struct eth_device* dev, u_long addr) { - srom_latch(dev, command, addr); - srom_latch(dev, command, addr); - srom_latch(dev, (command & 0x0000ff00) | DT_CS, addr); + s32 tmp; + + tmp = INL(dev, addr); + udelay(1); + + return tmp; } -static void -srom_address(struct eth_device *dev, u_int command, u_long addr, u_char offset) +/* Note: this routine returns extra data bits for size detection. */ +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) { int i; - signed char a; + unsigned retval = 0; + int read_cmd = location | (SROM_READ_CMD << addr_len); - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) { - srom_latch(dev, command | ((a < 0) ? DT_IN : 0), addr); + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM read at %d ", location); +#endif + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); + udelay(10); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); } - udelay(1); - i = (getfrom_srom(dev, addr) >> 3) & 0x01; + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); - return; +#ifdef DEBUG_SROM2 + printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); +#endif + + for (i = 16; i > 0; i--) { + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + udelay(10); + } + + /* Terminate the EEPROM access. */ + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" EEPROM value at %d is %5.5x.\n", location, retval); +#endif + + return retval; } -static short -srom_data(struct eth_device *dev, u_int command, u_long addr) +/* This executes a generic EEPROM command, typically a write or write enable. + It returns the data output from the EEPROM, and thus may also be used for + reads. */ +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) { - int i; - short word = 0; - s32 tmp; + unsigned retval = 0; + +#ifdef DEBUG_SROM + printf(" EEPROM op 0x%x: ", cmd); +#endif - for (i=0; i<16; i++) { - sendto_srom(dev, command | DT_CLK, addr); - tmp = getfrom_srom(dev, addr); - sendto_srom(dev, command, addr); + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); - word = (word << 1) | ((tmp >> 3) & 0x01); - } + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + sendto_srom(dev,dataval, ioaddr); + udelay(10); + +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev,ioaddr) & 15); +#endif + + sendto_srom(dev,dataval | DT_CLK, ioaddr); + udelay(10); + retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); + + /* Terminate the EEPROM access. */ + sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); - sendto_srom(dev, command & 0x0000ff00, addr); +#ifdef DEBUG_SROM + printf(" EEPROM result is 0x%5.5x.\n", retval); +#endif - return word; + return retval; } -static void -sendto_srom(struct eth_device* dev, u_int command, u_long addr) +static int read_srom(struct eth_device *dev, u_long ioaddr, int index) { - OUTL(dev, command, addr); - udelay(1); + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + + return do_eeprom_cmd(dev, ioaddr, + (((SROM_READ_CMD << ee_addr_size) | index) << 16) + | 0xffff, 3 + ee_addr_size + 16); } -static int -getfrom_srom(struct eth_device* dev, u_long addr) +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) { - s32 tmp; + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + int i; + unsigned short newval; - tmp = INL(dev, addr); - udelay(1); + udelay(10*1000); /* test-only */ - return tmp; +#ifdef DEBUG_SROM + printf("ee_addr_size=%d.\n", ee_addr_size); + printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); +#endif + + /* Enable programming modes. */ + do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); + + /* Do the actual write. */ + do_eeprom_cmd(dev, ioaddr, + (((SROM_WRITE_CMD<enetaddr[0]); + int i, j = 0; + + for (i = 0; i < (ETH_ALEN >> 1); i++) { + tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); + *p = le16_to_cpu(tmp); + j += *p++; + } + + if ((j == 0) || (j == 0x2fffd)) { + printf("Warning: can't read HW address from SROM.\n"); + goto Done; + } + +#ifdef DEBUG + for (i = 0; i < ETH_ALEN; i++) { + if (dev->enetaddr[i] != bis->bi_enetaddr[i]) { + printf("Warning: HW addresses don't match:\n"); + printf("Address in SROM is " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + dev->enetaddr[0], dev->enetaddr[1], + dev->enetaddr[2], dev->enetaddr[3], + dev->enetaddr[4], dev->enetaddr[5]); + printf("Address used by ppcboot is " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + bis->bi_enetaddr[0], bis->bi_enetaddr[1], + bis->bi_enetaddr[2], bis->bi_enetaddr[3], + bis->bi_enetaddr[4], bis->bi_enetaddr[5]); + + goto Done; + } + } +#endif + + return; + +Done: +#ifdef UPDATE_SROM + update_srom(dev, bis); +#endif + return; } +#ifdef UPDATE_SROM +static void update_srom(struct eth_device *dev, bd_t *bis) +{ + int i; + static unsigned short eeprom[0x40] = { + 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ + 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ + 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ + 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ + 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ + 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ + }; + + /* Ethernet Addr... */ + eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff); + eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff); + eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); + + for (i=0; i<0x40; i++) + { + write_srom(dev, DE4X5_APROM, i, eeprom[i]); + } +} +#endif + #endif diff --git a/board/pcippc2/eepro100.c b/drivers/eepro100.c similarity index 87% rename from board/pcippc2/eepro100.c rename to drivers/eepro100.c index a088a16..417da8d 100644 --- a/board/pcippc2/eepro100.c +++ b/drivers/eepro100.c @@ -25,19 +25,13 @@ #include #include #include - -#include "pci.h" +#include #undef DEBUG #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_EEPRO100) -/* Intel Ethernet */ -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 -#define PCI_DEVICE_ID_INTEL_82557 0x1229 - /* Ethernet chip registers. */ #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ @@ -222,8 +216,8 @@ static int rx_next; /* RX descriptor ring pointer */ static int tx_next; /* TX descriptor ring pointer */ static int tx_threshold; -static void init_rx_ring(void); -static void purge_tx_ring(void); +static void init_rx_ring(struct eth_device* dev); +static void purge_tx_ring(struct eth_device* dev); static void read_hw_addr(struct eth_device* dev, bd_t * bis); @@ -232,34 +226,22 @@ static int eepro100_send(struct eth_device* dev, volatile void *packet, int leng static int eepro100_recv(struct eth_device* dev); static void eepro100_halt(struct eth_device* dev); -static inline int INL(struct eth_device* dev, u_long addr) -{ - return le32_to_cpu(*(volatile u32 *)pci_mem_to_phys(addr + dev->iobase)); -} +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) static inline int INW(struct eth_device* dev, u_long addr) { - return le16_to_cpu(*(volatile u16 *)pci_mem_to_phys(addr + dev->iobase)); -} - -static inline int INB(struct eth_device* dev, u_long addr) -{ - return *(volatile u8 *)(pci_mem_to_phys(addr + dev->iobase)); -} - -static inline void OUTB(struct eth_device* dev, int command, u_long addr) -{ - *(volatile u8 *)(pci_mem_to_phys(addr + dev->iobase)) = command; + return le16_to_cpu(*(volatile u16 *)(addr + dev->iobase)); } static inline void OUTW(struct eth_device* dev, int command, u_long addr) { - *(volatile u16 *)(pci_mem_to_phys(addr + dev->iobase)) = cpu_to_le16(command); + *(volatile u16 *)((addr + dev->iobase)) = cpu_to_le16(command); } static inline void OUTL(struct eth_device *dev, int command, u_long addr) { - *(volatile u32 *)(pci_mem_to_phys(addr + dev->iobase)) = cpu_to_le32(command); + *(volatile u32 *)((addr + dev->iobase)) = cpu_to_le32(command); } /* Wait for the chip get the command. @@ -279,43 +261,52 @@ static int wait_for_eepro100(struct eth_device *dev) return 1; } +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER }, + { } +}; + int eepro100_initialize(bd_t *bis) { - int devno, i, card_number, status; + pci_dev_t devno; + int card_number = 0; struct eth_device* dev; - u_long iobase; + u32 iobase, status; + int idx = 0; - for(card_number=i=0; ; i++) + while (1) { /* Find PCI device */ - if ((devno = PCI_Find_Device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82559ER, i)) < 0) + if ((devno = pci_find_devices(supported, idx++)) < 0) { break; } - iobase = PCI_Read_CFG_Reg(devno, PCI_CFG_BASE_ADDRESS_0, 4) & ~0xf; + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; #ifdef DEBUG - printf("eepro100: Intel i82559 PCI EtherExpressPro @0x%lx\n", iobase); + printf("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", iobase); #endif - PCI_Write_CFG_Reg(devno, - PCI_CFG_COMMAND, - PCI_CMD_MEMEN | - PCI_CMD_MASTER, 4); + pci_write_config_dword(devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); /* Check if I/O accesses and Bus Mastering are enabled. */ - status = PCI_Read_CFG_Reg(devno, PCI_CFG_COMMAND, 4); - if (!(status & PCI_CMD_MEMEN)) + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { printf("Error: Can not enable MEM access.\n"); continue; } - if (!(status & PCI_CMD_MASTER)) + if (!(status & PCI_COMMAND_MASTER)) { printf("Error: Can not enable Bus Mastering.\n"); continue; @@ -323,8 +314,8 @@ int eepro100_initialize(bd_t *bis) dev = (struct eth_device*) malloc(sizeof *dev); - sprintf(dev->name, "i82559#%d", i); - dev->iobase = iobase; + sprintf(dev->name, "i82559#%d", card_number); + dev->iobase = bus_to_phys(iobase); dev->priv = (void*) devno; dev->init = eepro100_init; dev->halt = eepro100_halt; @@ -337,7 +328,7 @@ int eepro100_initialize(bd_t *bis) /* Set the latency timer for value. */ - PCI_Write_CFG_Reg(devno, PCI_CFG_LATENCY_TIMER, 0x20, 1); + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); udelay(10 * 1000); @@ -380,8 +371,8 @@ static int eepro100_init(struct eth_device* dev, bd_t *bis) /* Initialize Rx and Tx rings. */ - init_rx_ring(); - purge_tx_ring(); + init_rx_ring(dev); + purge_tx_ring(dev); /* Tell the adapter where the RX ring is located. */ @@ -391,7 +382,7 @@ static int eepro100_init(struct eth_device* dev, bd_t *bis) goto Done; } - OUTL(dev, pci_ram_to_mem((u32) &rx_ring[rx_next]), SCBPointer); + OUTL(dev, phys_to_bus((u32) &rx_ring[rx_next]), SCBPointer); OUTW(dev, SCB_M | RUC_START, SCBCmd); /* Send the Individual Address Setup frame @@ -402,7 +393,7 @@ static int eepro100_init(struct eth_device* dev, bd_t *bis) ias_cmd = (struct descriptor *)&tx_ring[tx_cur]; ias_cmd->command = cpu_to_le16((CFG_CMD_SUSPEND | CFG_CMD_IAS)); ias_cmd->status = 0; - ias_cmd->link = cpu_to_le32(pci_ram_to_mem((u32) &tx_ring[tx_next])); + ias_cmd->link = cpu_to_le32(phys_to_bus((u32) &tx_ring[tx_next])); memcpy(ias_cmd->params, bis->bi_enetaddr, 6); @@ -414,7 +405,7 @@ static int eepro100_init(struct eth_device* dev, bd_t *bis) goto Done; } - OUTL(dev, pci_ram_to_mem((u32) &tx_ring[tx_cur]), SCBPointer); + OUTL(dev, phys_to_bus((u32) &tx_ring[tx_cur]), SCBPointer); OUTW(dev, SCB_M | CU_START, SCBCmd); for (i=0; !(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_C); i++) @@ -457,9 +448,9 @@ static int eepro100_send(struct eth_device* dev, volatile void *packet, int leng TxCB_CMD_S | TxCB_CMD_EL); tx_ring[tx_cur].status = 0; tx_ring[tx_cur].count = cpu_to_le32(tx_threshold); - tx_ring[tx_cur].link = cpu_to_le32(pci_ram_to_mem((u32) &tx_ring[tx_next])); - tx_ring[tx_cur].tx_desc_addr = cpu_to_le32(pci_ram_to_mem((u32) &tx_ring[tx_cur].tx_buf_addr0)); - tx_ring[tx_cur].tx_buf_addr0 = cpu_to_le32(pci_ram_to_mem((u_long) packet)); + tx_ring[tx_cur].link = cpu_to_le32(phys_to_bus((u32) &tx_ring[tx_next])); + tx_ring[tx_cur].tx_desc_addr = cpu_to_le32(phys_to_bus((u32) &tx_ring[tx_cur].tx_buf_addr0)); + tx_ring[tx_cur].tx_buf_addr0 = cpu_to_le32(phys_to_bus((u_long) packet)); tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32(length); if (!wait_for_eepro100(dev)) @@ -470,7 +461,7 @@ static int eepro100_send(struct eth_device* dev, volatile void *packet, int leng /* Send the packet. */ - OUTL(dev, pci_ram_to_mem((u32) &tx_ring[tx_cur]), SCBPointer); + OUTL(dev, phys_to_bus((u32) &tx_ring[tx_cur]), SCBPointer); OUTW(dev, SCB_M | CU_START, SCBCmd); for(i = 0; !(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_C); i++) @@ -551,7 +542,7 @@ static int eepro100_recv(struct eth_device* dev) /* Reinitialize Rx ring. */ - init_rx_ring(); + init_rx_ring(dev); if (!wait_for_eepro100(dev)) { @@ -559,7 +550,7 @@ static int eepro100_recv(struct eth_device* dev) goto Done; } - OUTL(dev, pci_ram_to_mem((u32) &rx_ring[rx_next]), SCBPointer); + OUTL(dev, phys_to_bus((u32) &rx_ring[rx_next]), SCBPointer); OUTW(dev, SCB_M | RUC_START, SCBCmd); } @@ -634,7 +625,7 @@ static int read_eeprom(struct eth_device* dev, int location, int addr_len) return retval; } -static void init_rx_ring(void) +static void init_rx_ring(struct eth_device *dev) { int i; @@ -642,7 +633,7 @@ static void init_rx_ring(void) { rx_ring[i].status = 0; rx_ring[i].control = (i == NUM_RX_DESC-1) ? cpu_to_le16(RFD_CONTROL_S) : 0; - rx_ring[i].link = cpu_to_le32(pci_ram_to_mem((u32) &rx_ring[(i+1) % NUM_RX_DESC])); + rx_ring[i].link = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); rx_ring[i].rx_buf_addr = 0xffffffff; rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16); } @@ -650,7 +641,7 @@ static void init_rx_ring(void) rx_next = 0; } -static void purge_tx_ring(void) +static void purge_tx_ring(struct eth_device* dev) { int i; diff --git a/board/sandpoint/ns16550.c b/drivers/ns16550.c similarity index 55% rename from board/sandpoint/ns16550.c rename to drivers/ns16550.c index 756c3d0..6f818d7 100644 --- a/board/sandpoint/ns16550.c +++ b/drivers/ns16550.c @@ -5,28 +5,17 @@ */ #include -#include "ns16550.h" -#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ -#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ -#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ +#ifdef CFG_NS16550 -typedef struct NS16550 *NS16550_t; +#include -static const NS16550_t COM_PORTS[] = { - (NS16550_t) (CFG_ISA_IO + COM1), - (NS16550_t) (CFG_ISA_IO + COM2), -#ifdef CONFIG_MPC8245 - (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), - (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) -#endif -}; +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) +void NS16550_init (NS16550_t com_port, int baud_divisor) { - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; com_port->ier = 0x00; com_port->lcr = LCR_BKSE | LCRVAL; com_port->dll = baud_divisor & 0xff; @@ -34,10 +23,9 @@ volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) com_port->lcr = LCRVAL; com_port->mcr = MCRVAL; com_port->fcr = FCRVAL; - return (com_port); } -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) +void NS16550_reinit (NS16550_t com_port, int baud_divisor) { com_port->ier = 0x00; com_port->lcr = LCR_BKSE; @@ -48,19 +36,21 @@ void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) com_port->fcr = FCRVAL; } -void NS16550_putc (volatile struct NS16550 *com_port, char c) +void NS16550_putc (NS16550_t com_port, char c) { while ((com_port->lsr & LSR_THRE) == 0); com_port->thr = c; } -char NS16550_getc (volatile struct NS16550 *com_port) +char NS16550_getc (NS16550_t com_port) { while ((com_port->lsr & LSR_DR) == 0); return (com_port->rbr); } -int NS16550_tstc (volatile struct NS16550 *com_port) +int NS16550_tstc (NS16550_t com_port) { return ((com_port->lsr & LSR_DR) != 0); } + +#endif diff --git a/drivers/ns87308.c b/drivers/ns87308.c new file mode 100644 index 0000000..efce592 --- /dev/null +++ b/drivers/ns87308.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NS87308 + +#include + +void initialise_ns87308 (void) +{ +#ifdef CFG_NS87308_PS2MOD + unsigned char data; + + /* + * Switch floppy drive to PS/2 mode. + */ + read_pnp_config(SUPOERIO_CONF1, &data); + data &= 0xFB; + write_pnp_config(SUPOERIO_CONF1, data); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_KBC1) + PNP_SET_DEVICE_BASE(LDEV_KBC1, CFG_NS87308_KBC1_BASE); + write_pnp_config(LUN_CONFIG_REG, 0); + write_pnp_config(CBASE_HIGH, 0x00); + write_pnp_config(CBASE_LOW, 0x64); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_MOUSE) + PNP_ACTIVATE_DEVICE(LDEV_MOUSE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_RTC_APC) + PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CFG_NS87308_RTC_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_FDC) + PNP_SET_DEVICE_BASE(LDEV_FDC, CFG_NS87308_FDC_BASE); + write_pnp_config(LUN_CONFIG_REG, 0x40); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_RARP) + PNP_SET_DEVICE_BASE(LDEV_PARP, CFG_NS87308_LPT_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_UART1) + PNP_SET_DEVICE_BASE(LDEV_UART1, CFG_NS87308_UART1_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_UART2) + PNP_SET_DEVICE_BASE(LDEV_UART2, CFG_NS87308_UART2_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_GPIO) + PNP_SET_DEVICE_BASE(LDEV_GPIO, CFG_NS87308_GPIO_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_POWRMAN) +#ifndef CFG_NS87308_PWMAN_BASE + PNP_ACTIVATE_DEVICE(LDEV_POWRMAN); +#else + PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CFG_NS87308_PWMAN_BASE); + + /* + * Enable all units + */ + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER1, 0x7d); + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER2, 0x87); + +#ifdef CFG_NS87308_PMC1 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC1, CFG_NS87308_PMC1); +#endif + +#ifdef CFG_NS87308_PMC2 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC2, CFG_NS87308_PMC2); +#endif + +#ifdef CFG_NS87308_PMC3 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC3, CFG_NS87308_PMC3); +#endif +#endif +#endif + +#ifdef CFG_NS87308_CS0_BASE + PNP_PGCS_CSLINE_BASE(0, CFG_NS87308_CS0_BASE); + PNP_PGCS_CSLINE_CONF(0, CFG_NS87308_CS0_CONF); +#endif + +#ifdef CFG_NS87308_CS1_BASE + PNP_PGCS_CSLINE_BASE(1, CFG_NS87308_CS1_BASE); + PNP_PGCS_CSLINE_CONF(1, CFG_NS87308_CS1_CONF); +#endif + +#ifdef CFG_NS87308_CS2_BASE + PNP_PGCS_CSLINE_BASE(2, CFG_NS87308_CS2_BASE); + PNP_PGCS_CSLINE_CONF(2, CFG_NS87308_CS2_CONF); +#endif +} + +#endif diff --git a/drivers/pci.c b/drivers/pci.c new file mode 100644 index 0000000..0e4026e --- /dev/null +++ b/drivers/pci.c @@ -0,0 +1,484 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI routines + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +#include + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif /* DEBUG */ + +/* + * + */ + +#define PCI_HOSE_OP(rw, size, type) \ +int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, \ + int offset, type value) \ +{ \ + return hose->ops->rw##_##size(hose, dev, offset, value); \ +} + +PCI_HOSE_OP(read, byte, u8 *) +PCI_HOSE_OP(read, word, u16 *) +PCI_HOSE_OP(read, dword, u32 *) +PCI_HOSE_OP(write, byte, u8) +PCI_HOSE_OP(write, word, u16) +PCI_HOSE_OP(write, dword, u32) + +#define PCI_OP(rw, size, type, error_code) \ +int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ +{ \ + struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ + \ + if (!hose) \ + { \ + error_code; \ + return -1; \ + } \ + \ + return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ +} + +PCI_OP(read, byte, u8 *, *value = 0xff) +PCI_OP(read, word, u16 *, *value = 0xffff) +PCI_OP(read, dword, u32 *, *value = 0xffffffff) +PCI_OP(write, byte, u8, ) +PCI_OP(write, word, u16, ) +PCI_OP(write, dword, u32, ) + +#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ +int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose, \ + pci_dev_t dev, \ + int offset, type val) \ +{ \ + u32 val32; \ + \ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) \ + return -1; \ + \ + *val = (val32 >> ((offset & (int)off_mask) * 8)); \ + \ + return 0; \ +} + +#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ +int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose, \ + pci_dev_t dev, \ + int offset, type val) \ +{ \ + u32 val32, mask, ldata; \ + \ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) \ + return -1; \ + \ + mask = val_mask; \ + ldata = (((unsigned long)val) & mask) << ((offset & (int)off_mask) * 8);\ + mask <<= ((mask & (int)off_mask) * 8); \ + val32 = (val32 & ~mask) | ldata; \ + \ + if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0) \ + return -1; \ + \ + return 0; \ +} + +PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) +PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) +PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) +PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) + +/* + * + */ + +static struct pci_controller* hose_head = NULL; + +void pci_register_hose(struct pci_controller* hose) +{ + struct pci_controller **phose = &hose_head; + + while(*phose) + phose = &(*phose)->next; + + hose->next = NULL; + + *phose = hose; +} + +struct pci_controller* pci_bus_to_hose(int bus) +{ + struct pci_controller *hose; + + for (hose = hose_head; hose; hose = hose->next) + if (bus >= hose->first_busno && + bus <= hose->last_busno) + return hose; + + return NULL; +} + +pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) +{ + struct pci_controller * hose; + u16 vendor, device; + u8 header_type; + pci_dev_t bdf; + int i, bus, found_multi = 0; + + for (hose = hose_head; hose; hose = hose->next) + { +#if CFG_SCSI_SCAN_BUS_REVERSE + for (bus = hose->last_busno; bus >= hose->first_busno; bus--) +#else + for (bus = hose->first_busno; bus <= hose->last_busno; bus++) +#endif + for (bdf = PCI_BDF(bus,0,0); + bdf < PCI_BDF(bus+1,0,0); + bdf += PCI_BDF(0,0,1)) + { + if (!PCI_FUNC(bdf)) + { + pci_read_config_byte(bdf, + PCI_HEADER_TYPE, + &header_type); + + found_multi = header_type & 0x80; + } + else + { + if (!found_multi) + continue; + } + + pci_read_config_word(bdf, + PCI_VENDOR_ID, + &vendor); + pci_read_config_word(bdf, + PCI_DEVICE_ID, + &device); + + for (i=0; ids[i].vendor != 0; i++) + if (vendor == ids[i].vendor && + device == ids[i].device) + { + if (index <= 0) + return bdf; + + index--; + } + } + } + + return (-1); +} + +pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) +{ + static struct pci_device_id ids[2] = {{}, {0, 0}}; + + ids[0].vendor = vendor; + ids[0].device = device; + + return pci_find_devices(ids, index); +} + +/* + * + */ + +unsigned long pci_hose_phys_to_bus(struct pci_controller* hose, + unsigned long phys_addr, + unsigned long flags) +{ + struct pci_region *res; + unsigned long bus_addr; + int i; + + if (!hose) + { + printf("pci_hose_phys_to_bus: %s\n", "invalid hose"); + goto Done; + } + + for (i=0; iregion_count; i++) + { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + bus_addr = phys_addr - res->phys_start + res->bus_start; + + if (bus_addr >= res->bus_start && + bus_addr < res->bus_start + res->size) + { + return bus_addr; + } + } + + printf("pci_hose_phys_to_bus: %s\n", "invalid physical address"); + + Done: + return 0; +} + +unsigned long pci_hose_bus_to_phys(struct pci_controller* hose, + unsigned long bus_addr, + unsigned long flags) +{ + struct pci_region *res; + int i; + + if (!hose) + { + printf("pci_hose_bus_to_phys: %s\n", "invalid hose"); + goto Done; + } + + for (i=0; iregion_count; i++) + { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + if (bus_addr >= res->bus_start && + bus_addr < res->bus_start + res->size) + { + return bus_addr - res->bus_start + res->phys_start; + } + } + + printf("pci_hose_bus_to_phys: %s\n", "invalid physical address"); + + Done: + return 0; +} + +/* + * + */ + +int pci_hose_config_device(struct pci_controller *hose, + pci_dev_t dev, + unsigned long io, + unsigned long mem, + unsigned long command) +{ + unsigned int bar_response, bar_size, bar_value, old_command; + unsigned char pin; + int bar, found_mem64; + + DBG("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n", io, mem, command); + + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); + + for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) + { + pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); + pci_hose_read_config_dword(hose, dev, bar, &bar_response); + + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) + { + bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_value = io; + + io = ((io - 1) | (bar_size - 1)) + 1; + } + else + { + if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; + bar_value = mem; + + mem = ((mem - 1) | (bar_size - 1)) + 1; + } + + /* Write it out and update our limit */ + pci_hose_write_config_dword(hose, dev, bar, bar_value); + + if (found_mem64) + { + bar += 4; + pci_hose_write_config_dword(hose, dev, bar, 0x00000000); + } + } + + /* Configure Cache Line Size Register */ + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* Configure Latency Timer */ + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + + /* Disable interrupt line, if device says it wants to use interrupts */ + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); + if (pin != 0) + { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); + } + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, + (old_command & 0xffff0000) | command ); + + return 0; +} + +/* + * + */ + +struct pci_config_table *pci_find_config(struct pci_controller *hose, + unsigned short class, + unsigned int vendor, + unsigned int device, + unsigned int bus, + unsigned int dev, + unsigned int func) +{ + struct pci_config_table *table; + + for (table = hose->config_table; table && table->vendor; table++) + { + if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && + (table->device == PCI_ANY_ID || table->device == device) && + (table->class == PCI_ANY_ID || table->class == class) && + (table->bus == PCI_ANY_ID || table->bus == bus) && + (table->dev == PCI_ANY_ID || table->dev == dev) && + (table->func == PCI_ANY_ID || table->func == func)) + { + return table; + } + } + + return NULL; +} + +void pci_cfgfunc_config_device(struct pci_controller *hose, + pci_dev_t dev, + struct pci_config_table *entry) +{ + pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]); +} + +void pci_cfgfunc_do_nothing(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ +} + +/* + * + */ + +extern void pciauto_config_init(struct pci_controller *hose); +extern void pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); + +int pci_hose_scan_bus(struct pci_controller *hose, int bus) +{ + unsigned int sub_bus, found_multi=0; + unsigned short vendor, device, class; + unsigned char header_type; + struct pci_config_table *cfg; + pci_dev_t dev; + + sub_bus = bus; + + for (dev = PCI_BDF(bus,0,0); + dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); + dev += PCI_BDF(0,0,1)) + { + /* Skip our host bridge */ + if ( dev == PCI_BDF(hose->first_busno,0,0) ) + continue; + + if (PCI_FUNC(dev) && !found_multi) + continue; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80; + + pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); + + if (vendor != 0xffff && vendor != 0x0000) + { + DBG("PCI Scan: Found Bus %d, Device %d, Function %d\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) ); + + pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + cfg = pci_find_config(hose, class, vendor, device, + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); + if (cfg) + cfg->config_device(hose, dev, cfg); +#ifdef CONFIG_PCI_PNP + else + pciauto_config_device(hose, dev); +#endif + if (hose->fixup_irq) + hose->fixup_irq(hose, dev); + } + } + + return sub_bus; +} + +int pci_hose_scan(struct pci_controller *hose) +{ +#ifdef CONFIG_PCI_PNP + pciauto_config_init(hose); +#endif + return pci_hose_scan_bus(hose, hose->first_busno); +} + +#endif /* CONFIG_PCI */ diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c new file mode 100644 index 0000000..6d9558f --- /dev/null +++ b/drivers/pci_auto.c @@ -0,0 +1,319 @@ +/* + * arch/ppc/kernel/pci_auto.c + * + * PCI autoconfiguration library + * + * Author: Matt Porter + * + * Copyright 2000 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#ifdef CONFIG_PCI_PNP + +#include + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif /* DEBUG */ + +#define PCIAUTO_IDE_MODE_MASK 0x05 + +/* + * + */ + +void pciauto_region_init(struct pci_region* res) +{ + res->bus_lower = res->bus_start; +} + +void pciauto_region_align(struct pci_region *res, unsigned long size) +{ + res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; +} + +int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar) +{ + unsigned long addr; + + if (!res) + { + DBG("No resource"); + goto error; + } + + addr = ((res->bus_lower - 1) | (size - 1)) + 1; + + if (addr - res->bus_start + size > res->size) + { + DBG("No room in resource"); + goto error; + } + + res->bus_lower = addr + size; + + DBG("address=0x%lx", addr); + + *bar = addr; + return 0; + + error: + *bar = 0xffffffff; + return -1; +} + +/* + * + */ + +void pciauto_setup_device(struct pci_controller *hose, + pci_dev_t dev, int bars_num, + struct pci_region *mem, + struct pci_region *io) +{ + unsigned int bar_value, bar_response, bar_size; + unsigned int cmdstat = 0; + struct pci_region *bar_res; + int bar, bar_nr = 0; + int found_mem64 = 0; + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; + + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) + { + /* Tickle the BAR and get the response */ + pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); + pci_hose_read_config_dword(hose, dev, bar, &bar_response); + + /* If BAR is not implemented go to the next BAR */ + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) + { + bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_res = io; + + DBG("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); + } + else + { + if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; + bar_res = mem; + + DBG("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size); + } + + if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) + { + /* Write it out and update our limit */ + pci_hose_write_config_dword(hose, dev, bar, bar_value); + + /* + * If we are a 64-bit decoder then increment to the + * upper 32 bits of the bar and force it to locate + * in the lower 4GB of memory. + */ + if (found_mem64) + { + bar += 4; + pci_hose_write_config_dword(hose, dev, bar, 0x00000000); + } + + cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? + PCI_COMMAND_IO : PCI_COMMAND_MEMORY; + } + + DBG("\n"); + + bar_nr++; + } + + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); +} + +static void pciauto_prescan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus) +{ + struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_io = hose->pci_io; + unsigned int cmdstat; + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + + /* Configure bus number registers */ + pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); + pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus + 1); + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); + + if (pci_mem) + { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + /* Set up memory and I/O filter limits, assume 32-bit I/O space */ + pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, + (pci_mem->bus_lower & 0xfff00000) >> 16); + + cmdstat |= PCI_COMMAND_MEMORY; + } + + if (pci_io) + { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, + (pci_io->bus_lower & 0x0000f000) >> 8); + pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, + (pci_io->bus_lower & 0xffff0000) >> 16); + + cmdstat |= PCI_COMMAND_IO; + } + + /* We don't support prefetchable memory for now, so disable */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + + /* Enable memory and I/O accesses, enable bus master */ + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); +} + +static void pciauto_postscan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus) +{ + struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_io = hose->pci_io; + + /* Configure bus number registers */ + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); + + if (pci_mem) + { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, + (pci_mem->bus_lower-1) >> 16); + } + + if (pci_io) + { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, + ((pci_io->bus_lower-1) & 0x0000f000) >> 8); + pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, + ((pci_io->bus_lower-1) & 0xffff0000) >> 16); + } +} + +/* + * + */ + +void pciauto_config_init(struct pci_controller *hose) +{ + int i; + + hose->pci_io = hose->pci_mem = NULL; + + for (i=0; iregion_count; i++) + { + switch(hose->regions[i].flags) + { + case PCI_REGION_IO: + if (!hose->pci_io || + hose->pci_io->size < hose->regions[i].size) + hose->pci_io = hose->regions + i; + break; + case PCI_REGION_MEM: + if (!hose->pci_mem || + hose->pci_mem->size < hose->regions[i].size) + hose->pci_mem = hose->regions + i; + break; + } + } + + + + if (hose->pci_mem) + { + pciauto_region_init(hose->pci_mem); + + DBG("PCI Autoconfig: Memory region: [%lx-%lx]\n", + hose->pci_mem->bus_start, + hose->pci_mem->bus_start + hose->pci_mem->size - 1); + } + + if (hose->pci_io) + { + pciauto_region_init(hose->pci_io); + + DBG("PCI Autoconfig: I/O region: [%lx-%lx]\n", + hose->pci_io->bus_start, + hose->pci_io->bus_start + hose->pci_io->size - 1); + } +} + +void pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned int sub_bus; + unsigned short class; + unsigned char prg_iface; + + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + switch(class) + { + case PCI_CLASS_BRIDGE_PCI: + pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io); + + DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); + + pciauto_prescan_setup_bridge(hose, dev, PCI_BUS(dev)); + + sub_bus = pci_hose_scan_bus(hose, PCI_BUS(dev)+1); + + pciauto_postscan_setup_bridge(hose, dev, sub_bus); + break; + + case PCI_CLASS_STORAGE_IDE: + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); + if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) + { + DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n"); + return; + } + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + break; + + default: + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + break; + } +} + +#endif /* CONFIG_PCI_PNP */ diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c new file mode 100644 index 0000000..5283209 --- /dev/null +++ b/drivers/pci_indirect.c @@ -0,0 +1,77 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (C) 1998 Gabriel Paubert. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)) +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)) + +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} + +#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + unsigned int msr = mfmsr(); \ + mtmsr(msr & ~(MSR_EE | MSR_CE)); \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_le32(hose->cfg_addr, 0x00000000); \ + mtmsr(msr); \ + return 0; \ +} + +INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3) +INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2) +INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0) +#ifdef CONFIG_405GP +INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3) +INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2) +INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0) +#else +INDIRECT_PCI_OP(write, byte, u8, out_8, 3) +INDIRECT_PCI_OP(write, word, u16, out_le16, 2) +INDIRECT_PCI_OP(write, dword, u32, out_le32, 0) +#endif + +static struct pci_ops pci_indirect_ops = +{ + indirect_read_config_byte, + indirect_read_config_word, + indirect_read_config_dword, + indirect_write_config_byte, + indirect_write_config_word, + indirect_write_config_dword +}; + +void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +{ + hose->ops = &pci_indirect_ops; + hose->cfg_addr = (unsigned int *) cfg_addr; + hose->cfg_data = (unsigned char *) cfg_data; +} + +#endif diff --git a/board/cu824/serial.c b/drivers/serial.c similarity index 60% rename from board/cu824/serial.c rename to drivers/serial.c index f4ab1a8..3ea18ae 100644 --- a/board/cu824/serial.c +++ b/drivers/serial.c @@ -22,12 +22,22 @@ */ #include -#include "ns16550.h" + +#ifdef CFG_NS16550_SERIAL + +#include +#ifdef CFG_NS87308 +#include +#endif #if CONFIG_CONS_INDEX == 1 -static struct NS16550 *console = (struct NS16550 *)0xFE800080; +static NS16550_t console = (NS16550_t) CFG_NS16550_COM1; #elif CONFIG_CONS_INDEX == 2 -static struct NS16550 *console = (struct NS16550 *)0xFE8000C0; +static NS16550_t console = (NS16550_t) CFG_NS16550_COM2; +#elif CONFIG_CONS_INDEX == 3 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM3; +#elif CONFIG_CONS_INDEX == 4 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM4; #else #error no valid console defined #endif @@ -35,46 +45,51 @@ static struct NS16550 *console = (struct NS16550 *)0xFE8000C0; void serial_init (unsigned long dummy, int baudrate) { - int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / baudrate; + +#ifdef CFG_NS87308 + initialise_ns87308(); +#endif - NS16550_init(CONFIG_CONS_INDEX - 1, clock_divisor); + NS16550_init(console, clock_divisor); } void serial_putc(const char c) { - if (c == '\n') - { - serial_putc ('\r'); - } - NS16550_putc(console, c); + if (c == '\n') + NS16550_putc(console, '\r'); + + NS16550_putc(console, c); } void serial_puts (const char *s) { - while (*s) { - serial_putc (*s++); - } + while (*s) { + serial_putc (*s++); + } } int serial_getc(void) { - return NS16550_getc(console); + return NS16550_getc(console); } int serial_tstc(void) { - return NS16550_tstc(console); + return NS16550_tstc(console); } void serial_setbrg (unsigned long dummy, int baudrate) { - int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / baudrate; - NS16550_reinit(console, clock_divisor); + NS16550_reinit(console, clock_divisor); } + +#endif diff --git a/board/pcippc2/sym53c8xx.c b/drivers/sym53c8xx.c similarity index 97% rename from board/pcippc2/sym53c8xx.c rename to drivers/sym53c8xx.c index 4af3667..c224396 100644 --- a/board/pcippc2/sym53c8xx.c +++ b/drivers/sym53c8xx.c @@ -34,30 +34,16 @@ */ #include -#include -#include -// #include -#include "pci.h" -#include "cpc710_pci.h" +#ifdef CONFIG_SCSI_SYM53C8XX +#include +#include +#include #include -#include "sym53c8xx.h" - +#include #include - -unsigned long phys_to_bus(void *address) -{ - return (unsigned long) pci_ram_to_mem ((u32) address); -} - -void * bus_to_phys(unsigned long address) -{ - return (void *) pci_mem_to_phys ((u32) address); -} - - #undef SYM53C8XX_DEBUG #ifdef SYM53C8XX_DEBUG @@ -68,7 +54,6 @@ void * bus_to_phys(unsigned long address) #if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) - #undef SCSI_SINGLE_STEP /* * Single Step is only used for debug purposes @@ -116,6 +101,8 @@ static unsigned long script_error[2]; /* script for error handling */ static unsigned long int_stat[3]; /* interrupt status */ static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ +#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a)) +#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a)) #define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ @@ -198,24 +185,28 @@ void scsi_print_error(ccb *pccb) /****************************************************************************** * sets-up the SCSI controller - * the base memory address is retrived via the PCI_Read_CFG_Reg + * the base memory address is retrived via the pci_read_config_dword */ void scsi_low_level_init(int busdevfunc) { - unsigned long cmd; - unsigned long addr; + unsigned int cmd; + unsigned int addr; unsigned char vec; - vec=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_DEV_INT_LINE, 1); - addr= (unsigned long) bus_to_phys( (u32) PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_BASE_ADDRESS_1, 4) & ~0xF ); + + pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec); + pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr); + + addr = bus_to_phys(addr & ~0xf); /* * Enable bus mastering in case this has not been done, yet. */ - cmd=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_COMMAND, 4); - cmd |= PCI_CMD_MASTER; - PCI_Write_CFG_Reg(busdevfunc, PCI_CFG_COMMAND, cmd, 4); + pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd); + + scsi_mem_addr = addr; - scsi_mem_addr=addr; scsi_chip_init(); scsi_bus_reset(); } @@ -416,6 +407,7 @@ void scsi_print_script(void) void scsi_set_script(ccb *pccb) { + int busdevfunc = pccb->priv; int i; i=0; script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); @@ -598,6 +590,7 @@ void scsi_set_script(ccb *pccb) void scsi_issue(ccb *pccb) { + int busdevfunc = pccb->priv; int i; unsigned short sstat; int retrycnt; /* retry counter */ @@ -799,3 +792,4 @@ void scsi_chip_init(void) #endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ +#endif /* CONFIG_SCSI_SYM53C8XX */ diff --git a/board/eltec/bab750/w83c553f.c b/drivers/w83c553f.c similarity index 53% rename from board/eltec/bab750/w83c553f.c rename to drivers/w83c553f.c index c4cc742..ff4f88a 100644 --- a/board/eltec/bab750/w83c553f.c +++ b/drivers/w83c553f.c @@ -29,44 +29,50 @@ #include #include -#include + +#ifdef CFG_WINBOND_83C553 + +#include +#include #include #define EIEIO_SYNC __asm__ volatile ("eieio;sync") -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; +extern uint ide_bus_offset[CFG_IDE_MAXBUS]; void initialise_pic(void); void initialise_dma(void); void initialise_w83c553f(void) { - int regval = 0; - int devbusfn = 0; + pci_dev_t devbusfn; + unsigned char reg8; + unsigned short reg16; + unsigned int reg32; - devbusfn = PCI_Find_Device(W83C553F_VID, W83C553F_DID); + devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0); if (devbusfn == -1) { printf("Error: Cannot find W83C553F controller on any PCI bus."); - return; + return; } - regval = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_COMMAND, 2); - regval |= PCI_CMD_MASTER | PCI_CMD_IOEN | PCI_CMD_MEMEN; - PCI_Write_CFG_Reg(devbusfn, PCI_CFG_COMMAND, regval, 2); + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); - regval = PCI_Read_CFG_Reg(devbusfn, WINBOND_IPADCR, 1); + pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); /* 16 MB ISA memory space */ - regval |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); - regval &= ~IPADCR_MBE512; - PCI_Write_CFG_Reg(devbusfn, WINBOND_IPADCR, regval, 1); + reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); + reg8 &= ~IPADCR_MBE512; + pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); - regval = PCI_Read_CFG_Reg(devbusfn, WINBOND_CSCR, 1); + pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); /* switch off BIOS write protection */ - regval |= CSCR_UBIOSCSE; - regval &= ~CSCR_BIOSWP; - PCI_Write_CFG_Reg(devbusfn, WINBOND_CSCR, regval, 1); + reg8 |= CSCR_UBIOSCSE; + reg8 &= ~CSCR_BIOSWP; + pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); /* * Interrupt routing: @@ -76,35 +82,37 @@ void initialise_w83c553f(void) * - INTC -> IRQ 14 * - INTD -> IRQ 15 */ - PCI_Write_CFG_Reg(devbusfn, WINBOND_IDEIRCR, 0x90, 1); - PCI_Write_CFG_Reg(devbusfn, WINBOND_PCIIRCR, 0xABEF, 2); + pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90); + pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF); /* * Read IDE bus offsets from function 1 device. * We must unmask the LSB indicating that ist is an IO address. */ - devbusfn |= (1<<8); + devbusfn |= PCI_BDF(0,0,1); /* * Switch off legacy IRQ for IDE and IDE port 1. */ - PCI_Write_CFG_Reg(devbusfn, 0x09, 0x8F, 1); + pci_write_config_byte(devbusfn, 0x09, 0x8F); - regval = PCI_Read_CFG_Reg(devbusfn, WINDOND_IDECSR, 4); - regval &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); - PCI_Write_CFG_Reg(devbusfn, WINDOND_IDECSR, regval, 4); + pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); + reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); + pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); - ide_bus_offset[0] = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_BASE_ADDRESS_0, 4) & ~1; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); + ide_bus_offset[0] &= ~1; #if CFG_IDE_MAXBUS > 1 - ide_bus_offset[1] = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_BASE_ADDRESS_2, 4) & ~1; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); + ide_bus_offset[1] &= ~1; #endif /* * Enable function 1, IDE -> busmastering and IO space access */ - regval = PCI_Read_CFG_Reg(devbusfn, PCI_CFG_COMMAND, 2); - regval |= PCI_CMD_MASTER | PCI_CMD_IOEN; - PCI_Write_CFG_Reg(devbusfn, PCI_CFG_COMMAND, regval, 2); + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); /* * Initialise ISA interrupt controller @@ -144,47 +152,47 @@ void initialise_pic(void) void initialise_dma(void) { - unsigned int channel; - unsigned int rvalue1, rvalue2; + unsigned int channel; + unsigned int rvalue1, rvalue2; - /* perform a H/W reset of the devices */ + /* perform a H/W reset of the devices */ out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00); out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000); - /* initialise all channels to a sane state */ + /* initialise all channels to a sane state */ - for (channel = 0; channel < 4; channel++) { - /* - * dependent upon the channel, setup the specifics: - * - * demand - * address-increment - * autoinitialize-disable - * verify-transfer - */ + for (channel = 0; channel < 4; channel++) { + /* + * dependent upon the channel, setup the specifics: + * + * demand + * address-increment + * autoinitialize-disable + * verify-transfer + */ switch (channel) { - case 0: - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); - rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); - break; + case 0: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); + break; case 1: - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); - rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); - break; - case 2: - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); - rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); - break; - case 3: - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); - rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); - break; - default: - rvalue1 = 0x00; - rvalue2 = 0x00; - break; + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + break; + case 2: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + break; + case 3: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + break; + default: + rvalue1 = 0x00; + rvalue2 = 0x00; + break; } /* write to write mode registers */ @@ -193,20 +201,21 @@ void initialise_dma(void) out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF); } - /* enable all channels */ + /* enable all channels */ out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00); out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000); /* * initialize the global DMA configuration - * - * DACK# active low - * DREQ active high - * fixed priority - * channel group enable + * + * DACK# active low + * DREQ active high + * fixed priority + * channel group enable */ out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00); out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000); } +#endif /* CFG_WINBOND_83C553 */ diff --git a/include/405gp_pci.h b/include/405gp_pci.h index bf31178..3c1adec 100644 --- a/include/405gp_pci.h +++ b/include/405gp_pci.h @@ -1,76 +1,6 @@ #ifndef _405GP_PCI_H #define _405GP_PCI_H -typedef struct pciHeaderDevice - { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - int base2; /* base address 2 */ - int base3; /* base address 3 */ - int base4; /* base address 4 */ - int base5; /* base address 5 */ - int cis; /* cardBus CIS pointer */ - short subVendorId; /* sub system vendor ID */ - short subSystemId; /* sub system ID */ - int romBase; /* expansion ROM base address */ - int reserved0; /* reserved */ - int reserved1; /* reserved */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - char minGrant; /* min Grant */ - char maxLatency; /* max Latency */ - } PCI_HEADER_DEVICE; - -typedef struct pciHeaderBridge - { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - char priBus; /* primary bus number */ - char secBus; /* secondary bus number */ - char subBus; /* subordinate bus number */ - char secLatency; /* secondary latency timer */ - char ioBase; /* IO base */ - char ioLimit; /* IO limit */ - short secStatus; /* secondary status */ - short memBase; /* memory base */ - short memLimit; /* memory limit */ - short preBase; /* prefetchable memory base */ - short preLimit; /* prefetchable memory limit */ - int preBaseUpper; /* prefetchable memory base upper 32 bits */ - int preLimitUpper; /* prefetchable memory base upper 32 bits */ - short ioBaseUpper; /* IO base upper 16 bits */ - short ioLimitUpper; /* IO limit upper 16 bits */ - int reserved; /* reserved */ - int romBase; /* expansion ROM base address */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - short control; /* bridge control */ - } PCI_HEADER_BRIDGE; - /*----------------------------------------------------------------------------+ | 405GP PCI core memory map defines. +----------------------------------------------------------------------------*/ @@ -87,32 +17,6 @@ typedef struct pciHeaderBridge #define PCICFGADR 0xEEC00000 #define PCICFGDATA 0xEEC00004 -#define PCIVENDORID 0x00 -#define PCIDEVICEID 0x02 -#define PCICMD 0x04 - #define SERR_EN 0x0100 - #define BM_EN 0x0004 - #define MEM_EN 0x0002 - #define IO_EN 0x0001 -#define PCISTATUS 0x06 - #define CAPABLE_66MHZ 0x0020 -#define PCIREVID 0x08 -#define PCICLASSPI 0x09 -#define PCICLASSCODE 0x0A -#define PCICACHELINE 0x0C -#define PCILATENCYTIM 0x0D -#define PCIHEADERTYPE 0x0E -#define PCIBIST 0x0F -#define PCIBASEADDR0 0x10 -#define PCIBASEADDR1 0x14 -#define PCIBASEADDR2 0x18 -#define PCISSVENDORID 0x2C -#define PCISSDEVICEID 0x2E -#define PCIINTLINE 0x3C -#define PCIINTPIN 0x3D -#define PCIMINGRANT 0x3E -#define PCIMAXLATENCY 0x3F - #define PCIBUSNUM 0x40 /* 405GP specific parameters */ #define PCISUBBUSNUM 0x41 #define PCIDISCOUNT 0x42 @@ -143,95 +47,6 @@ typedef struct pciHeaderBridge #define PTM2MS 0xEF400038 #define PTM2LA 0xEF40003C -/*-----------------------------------------------------------------------------+ -| PCI-PCI bridge header -+-----------------------------------------------------------------------------*/ -#define PCIPCI_PRIMARYBUS 0x18 -#define PCIPCI_SECONDARYBUS 0x19 -#define PCIPCI_SUBORDINATEBUS 0x1A -#define PCIPCI_SECONDARYLATENCY 0x1B -#define PCIPCI_IOBASE 0x1C -#define PCIPCI_IOLIMIT 0x1D -#define PCIPCI_SECONDARYSTATUS 0x1E -#define PCIPCI_MEMBASE 0x20 -#define PCIPCI_MEMLIMIT 0x22 -#define PCIPCI_PREFETCHMEMBASE 0x24 -#define PCIPCI_PREFETCHMEMLIMIT 0x26 -#define PCIPCI_IOBASEUPPER16 0x30 -#define PCIPCI_IOLIMITUPPER16 0x32 - #define PCIDEVID_405GP 0x0 -/* Standard device configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDER_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - - -/* PCI-to-PCI bridge configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_PRIMARY_BUS 0x18 -#define PCI_CFG_SECONDARY_BUS 0x19 -#define PCI_CFG_SUBORDINATE_BUS 0x1a -#define PCI_CFG_SEC_LATENCY 0x1b -#define PCI_CFG_IO_BASE 0x1c -#define PCI_CFG_IO_LIMIT 0x1d -#define PCI_CFG_SEC_STATUS 0x1e -#define PCI_CFG_MEM_BASE 0x20 -#define PCI_CFG_MEM_LIMIT 0x22 -#define PCI_CFG_PRE_MEM_BASE 0x24 -#define PCI_CFG_PRE_MEM_LIMIT 0x26 -#define PCI_CFG_PRE_MEM_BASE_U 0x28 -#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c -#define PCI_CFG_IO_BASE_U 0x30 -#define PCI_CFG_IO_LIMIT_U 0x32 -#define PCI_CFG_ROM_BASE 0x38 -#define PCI_CFG_BRG_INT_LINE 0x3c -#define PCI_CFG_BRG_INT_PIN 0x3d -#define PCI_CFG_BRIDGE_CONTROL 0x3e - - - -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); -void PCI_Scan(int BusNum); -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_Bridge(int BusDevFunc); -void PCI_Dump_Device(int BusDevFunc); -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); -void pciHeaderShow(int BusDevFunc); -void pciDheaderPrint(PCI_HEADER_DEVICE * pD); -void pciBheaderPrint(PCI_HEADER_BRIDGE * pB); - #endif diff --git a/include/cmd_misc.h b/include/cmd_misc.h index 7c0620d..ba53861 100644 --- a/include/cmd_misc.h +++ b/include/cmd_misc.h @@ -27,24 +27,7 @@ #ifndef _CMD_MISC_H #define _CMD_MISC_H -#if (CONFIG_COMMANDS & CFG_CMD_PCI) - -#define CMD_TBL_PCIINFO MK_CMD_TBL_ENTRY( \ - "pciinfo", 3, 2, 1, do_pciinfo, \ - "pciinfo - print information about PCI devices\n", \ - "[ bus ]\n" \ - " - print information about PCI devices on PCI-Bus 'bus'\n" \ -), - -/* Implemented in $(BOARD)/pci.c */ -int do_pciinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_PCIINFO -#endif /* CFG_CMD_PCI */ - #if (CONFIG_COMMANDS & CFG_CMD_IRQ) - #define CMD_TBL_IRQINFO MK_CMD_TBL_ENTRY( \ "irqinfo", 3, 1, 1, do_irqinfo, \ "irqinfo - print information about IRQs\n", \ diff --git a/board/eltec/bab750/serial.h b/include/cmd_pci.h similarity index 58% rename from board/eltec/bab750/serial.h rename to include/cmd_pci.h index 94ab81e..821668f 100644 --- a/board/eltec/bab750/serial.h +++ b/include/cmd_pci.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com * * See file CREDITS for list of people who contributed to this * project. @@ -21,3 +21,24 @@ * MA 02111-1307 USA */ +/* + * MII Functions + */ +#ifndef _CMD_PCI_H +#define _CMD_PCI_H + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) +#define CMD_TBL_PCIINFO MK_CMD_TBL_ENTRY( \ + "pciinfo", 3, 2, 1, do_pciinfo, \ + "pciinfo - print information about PCI devices\n", \ + "[ bus ]\n" \ + " - print information about PCI devices on PCI-Bus 'bus'\n" \ +), + +int do_pciinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); + +#else +#define CMD_TBL_PCIINFO +#endif /* CFG_CMD_PCI */ + +#endif /* _CMD_PCI_H */ diff --git a/include/config_ADCIOP.h b/include/config_ADCIOP.h index bca85b9..a7ecdea 100644 --- a/include/config_ADCIOP.h +++ b/include/config_ADCIOP.h @@ -168,8 +168,15 @@ #endif /*----------------------------------------------------------------------- - * Network stuff (DEC21143) + * PCI stuff */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + #define CFG_ETH_DEV_FN 0x0000 #define CFG_ETH_IOBASE 0x0fff0000 diff --git a/include/config_BAB750.h b/include/config_BAB750.h index 4706f77..c9756af 100644 --- a/include/config_BAB750.h +++ b/include/config_BAB750.h @@ -208,6 +208,10 @@ #define CONFIG_PCI_HOST PCI_HOST_AUTO #define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + /* * Do NOT change the following table!!! Important mapping information!! */ @@ -270,9 +274,55 @@ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal ide controller */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ + #define CFG_NS87308_BADDR_10 1 -#define CFG_NS_PC87308UL 1 /* Nat Semi super-io controller on ISA bus */ +#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_KBC1 | \ + CFG_NS87308_MOUSE | \ + CFG_NS87308_FDC | \ + CFG_NS87308_RARP | \ + CFG_NS87308_GPIO | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#define CFG_NS87308_PS2MOD + +#define CFG_NS87308_GPIO_BASE 0x0220 +#define CFG_NS87308_PWMAN_BASE 0x0460 + +/* SuperI/O clock source is 24MHz via X1 */ +#define CFG_NS87308_PMC2 0x00 + +/* + * set up the NVRAM access registers + * NVRAM's controlled by the configurable CS line from the 87308 + */ +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x40 +#define CFG_NS87308_CS1_BASE 0x0070 +#define CFG_NS87308_CS1_CONF 0x1C +#define CFG_NS87308_CS2_BASE 0x0071 +#define CFG_NS87308_CS2_CONF 0x1C + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 1843200 + +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) #define CONFIG_RTC_MK48T59 diff --git a/include/config_CU824.h b/include/config_CU824.h index bd015c5..8a909fb 100644 --- a/include/config_CU824.h +++ b/include/config_CU824.h @@ -61,6 +61,7 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ 0/* CFG_CMD_DATE */ ) /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) @@ -134,6 +135,18 @@ #define CFG_INIT_RAM_END 0x1000 #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 4 + +#define CFG_NS16550_CLK (14745600 / 2) + +#define CFG_NS16550_COM1 0xFE800080 +#define CFG_NS16550_COM2 0xFE8000C0 /* * Low Level Configuration Settings @@ -143,13 +156,8 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_SERIAL_CLOCK (14745600 / 2) #define CFG_HZ 1000 -#define CFG_ETH_DEV_FN 0x7800 -#define CFG_ETH_IOBASE 0x00104000 - - /* Bit-field values for MCCR1. */ #define CFG_ROMNAL 0 @@ -221,8 +229,8 @@ #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (0xFE000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xFE000000 | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) #define CFG_DBAT0L CFG_IBAT0L #define CFG_DBAT0U CFG_IBAT0U @@ -279,5 +287,19 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP +#define CONFIG_TULIP_USE_IO + +#define CFG_ETH_DEV_FN 0x7800 +#define CFG_ETH_IOBASE 0x00104000 #endif /* __CONFIG_H */ diff --git a/include/config_DASA_SIM.h b/include/config_DASA_SIM.h index d5731b5..227fccf 100644 --- a/include/config_DASA_SIM.h +++ b/include/config_DASA_SIM.h @@ -167,6 +167,13 @@ /*----------------------------------------------------------------------- * PCI stuff */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + #define CFG_ETH_DEV_FN 0x0000 #define CFG_ETH_IOBASE 0x0fff0000 #define CFG_PCI9054_DEV_FN 0x0800 diff --git a/include/config_EVB64260.h b/include/config_EVB64260.h index f003686..23713dc 100644 --- a/include/config_EVB64260.h +++ b/include/config_EVB64260.h @@ -297,6 +297,18 @@ #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) #define CFG_PCI1_IO_SPACE_PCI 0x00000000 +/* + * NS16550 Configuration + */ +#define CFG_NS16550 + +#define CFG_NS16550_REG_SIZE -4 + +#define CFG_NS16550_CLK 3686400 + +#define CFG_NS16550_COM1 (CFG_DUART_IO + 0) +#define CFG_NS16550_COM2 (CFG_DUART_IO + 0x20) + /*---------------------------------------------------------------------- * Initial BAT mappings */ diff --git a/include/config_IAD210.h b/include/config_IAD210.h index 8d4aa05..a13b480 100644 --- a/include/config_IAD210.h +++ b/include/config_IAD210.h @@ -107,15 +107,18 @@ /* * Software (bit-bang) I2C driver configuration */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ diff --git a/include/config_ICU862.h b/include/config_ICU862.h index 325af02..e6bb118 100644 --- a/include/config_ICU862.h +++ b/include/config_ICU862.h @@ -98,14 +98,17 @@ /* * Software (bit-bang) I2C driver configuration */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ diff --git a/include/config_IP860.h b/include/config_IP860.h index cd6aa17..b1a062d 100644 --- a/include/config_IP860.h +++ b/include/config_IP860.h @@ -181,7 +181,7 @@ #undef CFG_ENV_IS_IN_FLASH #undef CFG_ENV_IS_IN_NVRAM #define CFG_ENV_IS_IN_NVRAM -//#define CFG_ENV_IS_IN_EEPROM 1 +#undef CFG_ENV_IS_IN_EEPROM #ifdef CFG_ENV_IS_IN_NVRAM #define CFG_ENV_ADDR 0x20000000 /* use SRAM */ diff --git a/include/config_MHPC.h b/include/config_MHPC.h index 9745838..2f38167 100644 --- a/include/config_MHPC.h +++ b/include/config_MHPC.h @@ -77,14 +77,17 @@ /* * Software (bit-bang) I2C driver configuration */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ diff --git a/include/config_MIP405.h b/include/config_MIP405.h index b1a8a8b..69d15e1 100644 --- a/include/config_MIP405.h +++ b/include/config_MIP405.h @@ -169,16 +169,22 @@ * PCI stuff *----------------------------------------------------------------------- */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + #define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST /* configure as pci-host */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ #define CONFIG_PCI_PNP /* pci plug-and-play */ /* resource configuration */ #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0x00000000 /* disabled */ #define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -307,6 +313,7 @@ #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ +#define CFG_SCSI_SPIN_UP_TIME 2 #endif /* CONFIG_SCSI_SYM53C8XX */ /************************************************************ * DISK Partition support diff --git a/include/config_MOUSSE.h b/include/config_MOUSSE.h index 400e7b4..d60a161 100644 --- a/include/config_MOUSSE.h +++ b/include/config_MOUSSE.h @@ -49,7 +49,6 @@ #define CONFIG_MPC8240 1 #define CONFIG_MOUSSE 1 #define CFG_ADDR_MAP_B 1 -#define CONFIG_PCI 1 #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 9600 #if 1 @@ -121,6 +120,17 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 18432000 + +#define CFG_NS16550_COM1 0xFFE08080 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) @@ -306,6 +316,17 @@ #define CONFIG_SERVERIP 209.128.93.133 #endif +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + #endif /* __CONFIG_H */ diff --git a/include/config_MUSENKI.h b/include/config_MUSENKI.h index 098db14..1dad78c 100644 --- a/include/config_MUSENKI.h +++ b/include/config_MUSENKI.h @@ -62,7 +62,7 @@ /* * Miscellaneous configurable options */ -/* #define CFG_LONGHELP /X* undef to save memory */ +#undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -78,6 +78,12 @@ *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 #define PCI_ENET1_IOADDR 0x81000000 @@ -121,6 +127,18 @@ #define CFG_RAMBOOT #endif +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area diff --git a/include/config_PIP405.h b/include/config_PIP405.h index 54ce3da..ac9b592 100644 --- a/include/config_PIP405.h +++ b/include/config_PIP405.h @@ -166,16 +166,22 @@ * PCI stuff *----------------------------------------------------------------------- */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + #define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST /* configure as pci-host */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ /* resource configuration */ #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0x00000000 /* disabled */ #define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -298,6 +304,7 @@ #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ +#define CFG_SCSI_SPIN_UP_TIME 2 /************************************************************ * Disk-On-Chip configuration diff --git a/include/config_SXNI855T.h b/include/config_SXNI855T.h index c409c73..4c1c16d 100644 --- a/include/config_SXNI855T.h +++ b/include/config_SXNI855T.h @@ -95,15 +95,18 @@ /* * Software (bit-bang) I2C driver configuration */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00010010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ # define CFG_I2C_SPEED 50000 # define CFG_I2C_SLAVE 0xFE diff --git a/include/config_Sandpoint8240.h b/include/config_Sandpoint8240.h index 8d525ec..2b08912 100644 --- a/include/config_Sandpoint8240.h +++ b/include/config_Sandpoint8240.h @@ -53,7 +53,8 @@ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_SDRAM | \ - CFG_CMD_EEPROM ) + CFG_CMD_EEPROM | \ + CFG_CMD_PCI ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -76,6 +77,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP #define CONFIG_NET_MULTI /* Multi ethernet cards support */ @@ -185,10 +187,43 @@ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ + #define CFG_NS87308_BADDR_10 1 +#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#undef CFG_NS87308_PS2MOD + +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x30 +#define CFG_NS87308_CS1_BASE 0x0075 +#define CFG_NS87308_CS1_CONF 0x30 +#define CFG_NS87308_CS2_BASE 0x0074 +#define CFG_NS87308_CS2_CONF 0x30 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 1843200 -#define CFG_NS_PC87308UL 1 /* Nat Semi super-io controller on ISA bus */ +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) /* * Low Level Configuration Settings diff --git a/include/config_Sandpoint8245.h b/include/config_Sandpoint8245.h index 58bfacf..df20767 100644 --- a/include/config_Sandpoint8245.h +++ b/include/config_Sandpoint8245.h @@ -52,7 +52,8 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) + CFG_CMD_EEPROM | \ + CFG_CMD_PCI ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -75,9 +76,12 @@ *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP #define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_EEPRO100 + #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 #define PCI_ENET1_IOADDR 0x81000000 @@ -183,10 +187,45 @@ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ + #define CFG_NS87308_BADDR_10 1 +#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#undef CFG_NS87308_PS2MOD + +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x30 +#define CFG_NS87308_CS1_BASE 0x0075 +#define CFG_NS87308_CS1_CONF 0x30 +#define CFG_NS87308_CS2_BASE 0x0074 +#define CFG_NS87308_CS2_CONF 0x30 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 1843200 -#define CFG_NS_PC87308UL 1 /* Nat Semi super-io controller on ISA bus */ +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) +#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) /* * Low Level Configuration Settings diff --git a/include/config_lwmon.h b/include/config_lwmon.h index 809e538..d9899f3 100644 --- a/include/config_lwmon.h +++ b/include/config_lwmon.h @@ -110,15 +110,18 @@ /* * Software (bit-bang) I2C driver configuration */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ diff --git a/include/mpc106.h b/include/mpc106.h index 1a53a57..9f22ce1 100644 --- a/include/mpc106.h +++ b/include/mpc106.h @@ -24,84 +24,11 @@ #ifndef _MPC106_PCI_H #define _MPC106_PCI_H -#ifndef DEFS_ONLY -typedef struct pciHeaderDevice { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - int base2; /* base address 2 */ - int base3; /* base address 3 */ - int base4; /* base address 4 */ - int base5; /* base address 5 */ - int cis; /* cardBus CIS pointer */ - short subVendorId; /* sub system vendor ID */ - short subSystemId; /* sub system ID */ - int romBase; /* expansion ROM base address */ - int reserved0; /* reserved */ - int reserved1; /* reserved */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - char minGrant; /* min Grant */ - char maxLatency; /* max Latency */ -} PCI_HEADER_DEVICE; - -typedef struct pciHeaderBridge { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - char priBus; /* primary bus number */ - char secBus; /* secondary bus number */ - char subBus; /* subordinate bus number */ - char secLatency; /* secondary latency timer */ - char ioBase; /* IO base */ - char ioLimit; /* IO limit */ - short secStatus; /* secondary status */ - short memBase; /* memory base */ - short memLimit; /* memory limit */ - short preBase; /* prefetchable memory base */ - short preLimit; /* prefetchable memory limit */ - int preBaseUpper; /* prefetchable memory base upper 32 bits */ - int preLimitUpper; /* prefetchable memory base upper 32 bits */ - short ioBaseUpper; /* IO base upper 16 bits */ - short ioLimitUpper; /* IO limit upper 16 bits */ - int reserved; /* reserved */ - int romBase; /* expansion ROM base address */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - short control; /* bridge control */ -} PCI_HEADER_BRIDGE; - -#endif /* DEFS_ONLY */ - - /* * Defines for the MPC106 PCI Config address and data registers followed by * defines for the standard PCI device configuration header. */ - -#define PCIDEVID_MPC106 0x0 +#define PCIDEVID_MPC106 0x0 /* * MPC106 Registers @@ -109,155 +36,104 @@ typedef struct pciHeaderBridge { #define MPC106_REG 0x80000000 #ifdef CFG_ADDRESS_MAP_A -#define MPC106_REG_ADDR 0x80000cf8 -#define MPC106_REG_DATA 0x80000cfc +#define MPC106_REG_ADDR 0x80000cf8 +#define MPC106_REG_DATA 0x80000cfc +#define MPC106_ISA_IO_PHYS 0x80000000 +#define MPC106_ISA_IO_BUS 0x00000000 +#define MPC106_ISA_IO_SIZE 0x00800000 +#define MPC106_PCI_IO_PHYS 0x81000000 +#define MPC106_PCI_IO_BUS 0x01000000 +#define MPC106_PCI_IO_SIZE 0x3e800000 +#define MPC106_PCI_MEM_PHYS 0xc0000000 +#define MPC106_PCI_MEM_BUS 0x00000000 +#define MPC106_PCI_MEM_SIZE 0x3f000000 +#define MPC106_PCI_MEMORY_PHYS 0x00000000 +#define MPC106_PCI_MEMORY_BUS 0x80000000 +#define MPC106_PCI_MEMORY_SIZE 0x80000000 #else -#define MPC106_REG_ADDR 0xfec00cf8 -#define MPC106_REG_DATA 0xfee00cfc +#define MPC106_REG_ADDR 0xfec00cf8 +#define MPC106_REG_DATA 0xfee00cfc +#define MPC106_ISA_MEM_PHYS 0xfd000000 +#define MPC106_ISA_MEM_BUS 0x00000000 +#define MPC106_ISA_MEM_SIZE 0x01000000 +#define MPC106_ISA_IO_PHYS 0xfe000000 +#define MPC106_ISA_IO_BUS 0x00000000 +#define MPC106_ISA_IO_SIZE 0x00800000 +#define MPC106_PCI_IO_PHYS 0xfe800000 +#define MPC106_PCI_IO_BUS 0x00800000 +#define MPC106_PCI_IO_SIZE 0x00400000 +#define MPC106_PCI_MEM_PHYS 0x80000000 +#define MPC106_PCI_MEM_BUS 0x80000000 +#define MPC106_PCI_MEM_SIZE 0x7d000000 +#define MPC106_PCI_MEMORY_PHYS 0x00000000 +#define MPC106_PCI_MEMORY_BUS 0x00000000 +#define MPC106_PCI_MEMORY_SIZE 0x40000000 #endif -#define CMD_SERR 0x0100 -#define PCI_CMD_MASTER 0x0004 -#define PCI_CMD_MEMEN 0x0002 -#define PCI_CMD_IOEN 0x0001 +#define CMD_SERR 0x0100 +#define PCI_CMD_MASTER 0x0004 +#define PCI_CMD_MEMEN 0x0002 +#define PCI_CMD_IOEN 0x0001 -#define PCI_STAT_NO_RSV_BITS 0xffff +#define PCI_STAT_NO_RSV_BITS 0xffff -#define PCI_BUSNUM 0x40 -#define PCI_SUBBUSNUM 0x41 -#define PCI_DISCOUNT 0x42 +#define PCI_BUSNUM 0x40 +#define PCI_SUBBUSNUM 0x41 +#define PCI_DISCOUNT 0x42 #define PCI_PICR1 0xA8 -#define PICR1_CF_CBA(value) ((value & 0xff) << 24) -#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) -#define PICR1_PROC_TYPE_603 0x40000 -#define PICR1_PROC_TYPE_604 0x60000 -#define PICR1_MCP_EN 0x800 -#define PICR1_CF_DPARK 0x200 -#define PICR1_CF_LOOP_SNOOP 0x10 -#define PICR1_CF_APARK 0x8 -#define PICR1_ADDRESS_MAP 0x10000 -#define PICR1_XIO_MODE 0x80000 +#define PICR1_CF_CBA(value) ((value & 0xff) << 24) +#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) +#define PICR1_PROC_TYPE_603 0x40000 +#define PICR1_PROC_TYPE_604 0x60000 +#define PICR1_MCP_EN 0x800 +#define PICR1_CF_DPARK 0x200 +#define PICR1_CF_LOOP_SNOOP 0x10 +#define PICR1_CF_APARK 0x8 +#define PICR1_ADDRESS_MAP 0x10000 +#define PICR1_XIO_MODE 0x80000 #define PCI_PICR2 0xAC -#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) -#define PICR2_CF_FLUSH_L2 0x10000000 -#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) -#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) +#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) +#define PICR2_CF_FLUSH_L2 0x10000000 +#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) +#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) #define PICR2_L2_EN 0x40000000 -#define PICR2_L2_UPDATE_EN 0x80000000 - -/* - * PCI-PCI bridge header - */ -#define PCIPCI_PRIMARYBUS 0x18 -#define PCIPCI_SECONDARYBUS 0x19 -#define PCIPCI_SUBORDINATEBUS 0x1A -#define PCIPCI_SECONDARYLATENCY 0x1B -#define PCIPCI_IOBASE 0x1C -#define PCIPCI_IOLIMIT 0x1D -#define PCIPCI_SECONDARYSTATUS 0x1E -#define PCIPCI_MEMBASE 0x20 -#define PCIPCI_MEMLIMIT 0x22 -#define PCIPCI_PREFETCHMEMBASE 0x24 -#define PCIPCI_PREFETCHMEMLIMIT 0x26 -#define PCIPCI_IOBASEUPPER16 0x30 -#define PCIPCI_IOLIMITUPPER16 0x32 - -/* - * Standard device configuration register offsets - * Note that only modulo-4 addresses are written to the address register - */ -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDER_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - - -/* - * PCI-to-PCI bridge configuration register offsets - * Note that only modulo-4 addresses are written to the address register - */ -#define PCI_CFG_PRIMARY_BUS 0x18 -#define PCI_CFG_SECONDARY_BUS 0x19 -#define PCI_CFG_SUBORDINATE_BUS 0x1a -#define PCI_CFG_SEC_LATENCY 0x1b -#define PCI_CFG_IO_BASE 0x1c -#define PCI_CFG_IO_LIMIT 0x1d -#define PCI_CFG_SEC_STATUS 0x1e -#define PCI_CFG_MEM_BASE 0x20 -#define PCI_CFG_MEM_LIMIT 0x22 -#define PCI_CFG_PRE_MEM_BASE 0x24 -#define PCI_CFG_PRE_MEM_LIMIT 0x26 -#define PCI_CFG_PRE_MEM_BASE_U 0x28 -#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c -#define PCI_CFG_IO_BASE_U 0x30 -#define PCI_CFG_IO_LIMIT_U 0x32 -#define PCI_CFG_ROM_BASE 0x38 -#define PCI_CFG_BRG_INT_LINE 0x3c -#define PCI_CFG_BRG_INT_PIN 0x3d -#define PCI_CFG_BRIDGE_CONTROL 0x3e - +#define PICR2_L2_UPDATE_EN 0x80000000 /* * Memory controller */ -#define MPC106_MCCR1 0xF0 -#define MCCR1_TYPE_EDO 0x00020000 -#define MCCR1_BK0_9BITS 0x0 -#define MCCR1_BK0_10BITS 0x1 -#define MCCR1_BK0_11BITS 0x2 -#define MCCR1_BK0_12BITS 0x3 -#define MCCR1_BK1_9BITS 0x0 -#define MCCR1_BK1_10BITS 0x4 -#define MCCR1_BK1_11BITS 0x8 -#define MCCR1_BK1_12BITS 0xC -#define MCCR1_BK2_9BITS 0x00 -#define MCCR1_BK2_10BITS 0x10 -#define MCCR1_BK2_11BITS 0x20 -#define MCCR1_BK2_12BITS 0x30 -#define MCCR1_BK3_9BITS 0x00 -#define MCCR1_BK3_10BITS 0x40 -#define MCCR1_BK3_11BITS 0x80 -#define MCCR1_BK3_12BITS 0xC0 +#define MPC106_MCCR1 0xF0 +#define MCCR1_TYPE_EDO 0x00020000 +#define MCCR1_BK0_9BITS 0x0 +#define MCCR1_BK0_10BITS 0x1 +#define MCCR1_BK0_11BITS 0x2 +#define MCCR1_BK0_12BITS 0x3 +#define MCCR1_BK1_9BITS 0x0 +#define MCCR1_BK1_10BITS 0x4 +#define MCCR1_BK1_11BITS 0x8 +#define MCCR1_BK1_12BITS 0xC +#define MCCR1_BK2_9BITS 0x00 +#define MCCR1_BK2_10BITS 0x10 +#define MCCR1_BK2_11BITS 0x20 +#define MCCR1_BK2_12BITS 0x30 +#define MCCR1_BK3_9BITS 0x00 +#define MCCR1_BK3_10BITS 0x40 +#define MCCR1_BK3_11BITS 0x80 +#define MCCR1_BK3_12BITS 0xC0 #define MCCR1_MEMGO 0x00080000 -#define MPC106_MCCR2 0xF4 -#define MPC106_MCCR3 0xF8 -#define MPC106_MCCR4 0xFC +#define MPC106_MCCR2 0xF4 +#define MPC106_MCCR3 0xF8 +#define MPC106_MCCR4 0xFC -#define MPC106_MSAR1 0x80 -#define MPC106_EMSAR1 0x88 -#define MPC106_EMSAR2 0x8C -#define MPC106_MEAR1 0x90 -#define MPC106_EMEAR1 0x98 -#define MPC106_EMEAR2 0x9C +#define MPC106_MSAR1 0x80 +#define MPC106_EMSAR1 0x88 +#define MPC106_EMSAR2 0x8C +#define MPC106_MEAR1 0x90 +#define MPC106_EMEAR1 0x98 +#define MPC106_EMEAR2 0x9C #define MPC106_MBER 0xA0 #define MBER_BANK0 0x1 @@ -265,28 +141,5 @@ typedef struct pciHeaderBridge { #define MBER_BANK2 0x4 #define MBER_BANK3 0x8 - -#ifndef DEFS_ONLY - -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); -int PCI_Scan(int BusNum); -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_Bridge(int BusDevFunc); -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); -void PCI_Header_Show(int BusDevFunc); -void PCI_Dheader_Print(PCI_HEADER_DEVICE * pD); -void PCI_Bheader_Print(PCI_HEADER_BRIDGE * pB); - -/* - * memory mapping functions - */ -unsigned long phys_to_bus(void*); -void *bus_to_phys(unsigned long); - -#endif /* DEFS_ONLY */ - - #endif diff --git a/include/mpc824x.h b/include/mpc824x.h index 11a3d5a..318629f 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -52,33 +52,60 @@ */ /* Kahlua/MPC8240 defines */ -#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */ -#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */ -#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */ -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ -#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ -#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ -#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ -#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ -#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */ -#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */ -#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */ -#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ -#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ -#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ -#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ -#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ -#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ -#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ -#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ -#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/ -#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */ -#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */ -#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */ +#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */ +#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */ +#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */ +#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */ +#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */ +#define CHRP_ISA_MEM_PHYS 0xfd000000 +#define CHRP_ISA_MEM_BUS 0x00000000 +#define CHRP_ISA_MEM_SIZE 0x01000000 +#define CHRP_ISA_IO_PHYS 0xfe000000 +#define CHRP_ISA_IO_BUS 0x00000000 +#define CHRP_ISA_IO_SIZE 0x00800000 +#define CHRP_PCI_IO_PHYS 0xfe800000 +#define CHRP_PCI_IO_BUS 0x00800000 +#define CHRP_PCI_IO_SIZE 0x00400000 +#define CHRP_PCI_MEM_PHYS 0x80000000 +#define CHRP_PCI_MEM_BUS 0x80000000 +#define CHRP_PCI_MEM_SIZE 0x7d000000 +#define CHRP_PCI_MEMORY_PHYS 0x00000000 +#define CHRP_PCI_MEMORY_BUS 0x00000000 +#define CHRP_PCI_MEMORY_SIZE 0x40000000 +#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ +#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ +#define PREP_ISA_IO_PHYS 0x80000000 +#define PREP_ISA_IO_BUS 0x00000000 +#define PREP_ISA_IO_SIZE 0x00800000 +#define PREP_PCI_IO_PHYS 0x81000000 +#define PREP_PCI_IO_BUS 0x01000000 +#define PREP_PCI_IO_SIZE 0x3e800000 +#define PREP_PCI_MEM_PHYS 0xc0000000 +#define PREP_PCI_MEM_BUS 0x00000000 +#define PREP_PCI_MEM_SIZE 0x3f000000 +#define PREP_PCI_MEMORY_PHYS 0x00000000 +#define PREP_PCI_MEMORY_BUS 0x80000000 +#define PREP_PCI_MEMORY_SIZE 0x80000000 +#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ +#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ +#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ +#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ +#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ +#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */ +#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */ +#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */ +#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ +#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ +#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ +#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ +#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ +#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ +#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ +#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ +#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/ +#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */ +#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */ +#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */ /*----------------------------------------------------------------------- * Exception offsets (PowerPC standard) @@ -497,6 +524,7 @@ #define PCISWAP(x) LONGSWAP(x) #ifndef __ASSEMBLY__ + /* * MPC107 Support * @@ -513,6 +541,11 @@ unsigned int mpc824x_eummbar_read(unsigned int regNum); void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal); unsigned long get_gclk_freq(void); +#ifdef CONFIG_PCI +struct pci_controller; +void pci_cpm824x_init(struct pci_controller* hose); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __MPC824X_H__ */ diff --git a/include/ns16550.h b/include/ns16550.h new file mode 100644 index 0000000..c83298d --- /dev/null +++ b/include/ns16550.h @@ -0,0 +1,112 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + */ + +#if (CFG_NS16550_REG_SIZE == 1) +struct NS16550 { + unsigned char rbr; /* 0 */ + unsigned char ier; /* 1 */ + unsigned char fcr; /* 2 */ + unsigned char lcr; /* 3 */ + unsigned char mcr; /* 4 */ + unsigned char lsr; /* 5 */ + unsigned char msr; /* 6 */ + unsigned char scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 2) +struct NS16550 { + unsigned short rbr; /* 0 */ + unsigned short ier; /* 1 */ + unsigned short fcr; /* 2 */ + unsigned short lcr; /* 3 */ + unsigned short mcr; /* 4 */ + unsigned short lsr; /* 5 */ + unsigned short msr; /* 6 */ + unsigned short scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 4) +struct NS16550 { + unsigned long rbr; /* 0 */ + unsigned long ier; /* 1 */ + unsigned long fcr; /* 2 */ + unsigned long lcr; /* 3 */ + unsigned long mcr; /* 4 */ + unsigned long lsr; /* 5 */ + unsigned long msr; /* 6 */ + unsigned long scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == -4) +struct NS16550 { + unsigned char rbr; /* 0 */ + int pad1:24; + unsigned long ier; /* 1 */ + int pad2:24; + unsigned long fcr; /* 2 */ + int pad3:24; + unsigned long lcr; /* 3 */ + int pad4:24; + unsigned long mcr; /* 4 */ + int pad5:24; + unsigned long lsr; /* 5 */ + int pad6:24; + unsigned long msr; /* 6 */ + int pad7:24; + unsigned long scr; /* 7 */ + int pad8:24; +} __attribute__ ((packed)); +#else +#error "Please define NS16550 registers size." +#endif + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef volatile struct NS16550 *NS16550_t; + +#define FCR_FIFO_EN 0x01 /* Fifo enable */ +#define FCR_RXSR 0x02 /* Receiver soft reset */ +#define FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + +#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble */ +#define LCR_EPS 0x10 /* Even Parity Select */ +#define LCR_STKP 0x20 /* Stick Parity */ +#define LCR_SBRK 0x40 /* Set Break */ +#define LCR_BKSE 0x80 /* Bank select enable */ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +/* useful defaults for LCR */ +#define LCR_8N1 0x03 + +void NS16550_init (NS16550_t com_port, int baud_divisor); +void NS16550_putc (NS16550_t com_port, char c); +char NS16550_getc (NS16550_t com_port); +int NS16550_tstc (NS16550_t com_port); +void NS16550_reinit (NS16550_t com_port, int baud_divisor); diff --git a/board/eltec/bab750/ns87308.h b/include/ns87308.h similarity index 86% rename from board/eltec/bab750/ns87308.h rename to include/ns87308.h index 6e78b85..feeb940 100644 --- a/board/eltec/bab750/ns87308.h +++ b/include/ns87308.h @@ -46,12 +46,6 @@ struct GPIO unsigned char puc2; /* 7 pull-up control port 2 */ }; -#define GPIO_BASE 0x0220 -#define LPT_BASE 0x0278 -#define KBC1_BASE 0x0060 -#define FDC_BASE 0x03F0 - -#define PWMAN_BASE 0x460 /* * The following represents the power management registers on the NS87308/NS97307 */ @@ -133,11 +127,22 @@ struct GPIO #define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/ #define LDEV_FDC 0x03 /*floppy disk controller*/ #define LDEV_PARP 0x04 /*Parallel port*/ -#define LDEV_UART1 0x06 #define LDEV_UART2 0x05 +#define LDEV_UART1 0x06 #define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/ #define LDEV_POWRMAN 0x08 /*Power Managment*/ +#define CFG_NS87308_KBC1 (1 << LDEV_KBC1) +#define CFG_NS87308_KBC2 (1 << LDEV_KBC2) +#define CFG_NS87308_MOUSE (1 << LDEV_MOUSE) +#define CFG_NS87308_RTC_APC (1 << LDEV_RTC_APC) +#define CFG_NS87308_FDC (1 << LDEV_FDC) +#define CFG_NS87308_PARP (1 << LDEV_PARP) +#define CFG_NS87308_UART2 (1 << LDEV_UART2) +#define CFG_NS87308_UART1 (1 << LDEV_UART1) +#define CFG_NS87308_GPIO (1 << LDEV_GPIO) +#define CFG_NS87308_POWRMAN (1 << LDEV_POWRMAN) + /*some functions and macro's for doing configuration */ static inline void read_pnp_config(unsigned char index, unsigned char *data) @@ -157,6 +162,12 @@ static inline void pnp_set_device(unsigned char dev) write_pnp_config(LOGICAL_DEVICE, dev); } +static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data) +{ + pci_writeb(index, CFG_ISA_IO + base); + eieio(); + pci_writeb(data, CFG_ISA_IO + base + 1); +} /*void write_pnp_config(unsigned char index, unsigned char data); void pnp_set_device(unsigned char dev); @@ -214,5 +225,26 @@ static inline void write_pgcs_config(unsigned char index, unsigned char data) #define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */ #define FCR_TXFTH1 0x20 /* for interrupt trigger */ +/* + * Default NS87308 configuration + */ +#ifndef CFG_NS87308_KBC1_BASE +#define CFG_NS87308_KBC1_BASE 0x0060 +#endif +#ifndef CFG_NS87308_RTC_BASE +#define CFG_NS87308_RTC_BASE 0x0070 +#endif +#ifndef CFG_NS87308_FDC_BASE +#define CFG_NS87308_FDC_BASE 0x03F0 +#endif +#ifndef CFG_NS87308_LPT_BASE +#define CFG_NS87308_LPT_BASE 0x0278 +#endif +#ifndef CFG_NS87308_UART1_BASE +#define CFG_NS87308_UART1_BASE 0x03F8 +#endif +#ifndef CFG_NS87308_UART2_BASE +#define CFG_NS87308_UART2_BASE 0x02F8 +#endif #endif /*_NS87308_H_*/ diff --git a/include/pci.h b/include/pci.h new file mode 100644 index 0000000..5377a17 --- /dev/null +++ b/include/pci.h @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aloong with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCI_H +#define _PCI_H + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 + revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ +#define PCI_CLASS_CODE 0x0b /* Device class code */ +#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) +#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) + +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +/* 0x35-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1d +#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ +#define PCI_IO_RANGE_TYPE_16 0x00 +#define PCI_IO_RANGE_TYPE_32 0x01 +#define PCI_IO_RANGE_MASK ~0x0f +#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f +#define PCI_MEMORY_RANGE_MASK ~0x0f +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_RANGE_TYPE_MASK 0x0f +#define PCI_PREF_RANGE_TYPE_32 0x00 +#define PCI_PREF_RANGE_TYPE_64 0x01 +#define PCI_PREF_RANGE_MASK ~0x0f +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2c +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +/* 0x34 same as for htype 0 */ +/* 0x35-0x3b is reserved */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_BRIDGE_CONTROL 0x3e +#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ +#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ +#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ + +/* Header type 2 (CardBus bridges) */ +#define PCI_CB_CAPABILITY_LIST 0x14 +/* 0x15 reserved */ +#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ +#define PCI_CB_MEMORY_BASE_0 0x1c +#define PCI_CB_MEMORY_LIMIT_0 0x20 +#define PCI_CB_MEMORY_BASE_1 0x24 +#define PCI_CB_MEMORY_LIMIT_1 0x28 +#define PCI_CB_IO_BASE_0 0x2c +#define PCI_CB_IO_BASE_0_HI 0x2e +#define PCI_CB_IO_LIMIT_0 0x30 +#define PCI_CB_IO_LIMIT_0_HI 0x32 +#define PCI_CB_IO_BASE_1 0x34 +#define PCI_CB_IO_BASE_1_HI 0x36 +#define PCI_CB_IO_LIMIT_1 0x38 +#define PCI_CB_IO_LIMIT_1_HI 0x3a +#define PCI_CB_IO_RANGE_MASK ~0x03 +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_CB_BRIDGE_CONTROL 0x3e +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_SERR 0x02 +#define PCI_CB_BRIDGE_CTL_ISA 0x04 +#define PCI_CB_BRIDGE_CTL_VGA 0x08 +#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 +#define PCI_CB_SUBSYSTEM_ID 0x42 +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 0x48-0x7f reserved */ + +/* Capability lists */ + +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_ID_PM 0x01 /* Power Management */ +#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ +#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ +#define PCI_CAP_SIZEOF 4 + +/* Power Management Registers */ + +#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ +#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ +#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ +#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ +#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ +#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ +#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ +#define PCI_PM_CTRL 4 /* PM control and status register */ +#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ +#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ +#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ +#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ +#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ +#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ +#define PCI_PM_DATA_REGISTER 7 /* (??) */ +#define PCI_PM_SIZEOF 8 + +/* AGP registers */ + +#define PCI_AGP_VERSION 2 /* BCD version number */ +#define PCI_AGP_RFU 3 /* Rest of capability flags */ +#define PCI_AGP_STATUS 4 /* Status register */ +#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ +#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ +#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ +#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ +#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ +#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ +#define PCI_AGP_COMMAND 8 /* Control register */ +#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ +#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ +#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ +#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ +#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ +#define PCI_AGP_SIZEOF 12 + +/* Slot Identification */ + +#define PCI_SID_ESR 2 /* Expansion Slot Register */ +#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ +#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ +#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ + +/* Message Signalled Interrupts registers */ + +#define PCI_MSI_FLAGS 2 /* Various flags */ +#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ +#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ +#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ +#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ +#define PCI_MSI_RFU 3 /* Rest of capability flags */ +#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ +#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ +#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ + +#define PCI_MAX_PCI_DEVICES 32 +#define PCI_MAX_PCI_FUNCTIONS 8 + +/* Include the ID list */ + +#include + +struct pci_region { + unsigned long bus_start; /* Start on the bus */ + unsigned long phys_start; /* Start in physical address space */ + unsigned long size; /* Size */ + unsigned long flags; /* Resource flags */ + + unsigned long bus_lower; +}; + +#define PCI_REGION_MEM 0x00000000 /* PCI memory space */ +#define PCI_REGION_IO 0x00000001 /* PCI IO space */ +#define PCI_REGION_TYPE 0x00000001 + +#define PCI_REGION_MEMORY 0x00000100 /* System memory */ +#define PCI_REGION_RO 0x00000200 /* Read-only memory */ + +extern __inline__ void pci_set_region(struct pci_region *reg, + unsigned long bus_start, + unsigned long phys_start, + unsigned long size, + unsigned long flags) { + reg->bus_start = bus_start; + reg->phys_start = phys_start; + reg->size = size; + reg->flags = flags; +} + +typedef int pci_dev_t; + +#define PCI_BUS(d) (((d) >> 16) & 0xff) +#define PCI_DEV(d) (((d) >> 11) & 0x1f) +#define PCI_FUNC(d) (((d) >> 8) & 0x7) +#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) + +#define PCI_ANY_ID (~0) + +struct pci_device_id { + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ +}; + +struct pci_controller; + +struct pci_config_table { + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ + unsigned int class; /* Class ID, or PCI_ANY_ID */ + unsigned int bus; /* Bus number, or PCI_ANY_ID */ + unsigned int dev; /* Device number, or PCI_ANY_ID */ + unsigned int func; /* Function number, or PCI_ANY_ID */ + + void (*config_device)(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); + unsigned long priv[3]; +}; + +extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); +extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); + +/* Low-level architecture-dependent routines */ + +struct pci_ops { + int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *val); + int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *val); + int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *val); + int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8 val); + int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16 val); + int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32 val); +}; + +#define MAX_PCI_REGIONS 7 + +/* + * Structure of a PCI controller (host bridge) + */ +struct pci_controller { + struct pci_controller *next; + + int first_busno; + int last_busno; + + struct pci_ops *ops; + volatile unsigned int *cfg_addr; + volatile unsigned char *cfg_data; + + struct pci_region regions[MAX_PCI_REGIONS]; + int region_count; + + struct pci_config_table *config_table; + + void (*fixup_irq)(struct pci_controller *, pci_dev_t); + + /* Used by auto config */ + struct pci_region *pci_mem, *pci_io; + + /* Used by ppc405 autoconfig*/ + struct pci_region *pci_fb; +}; + +extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); + +extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose, + unsigned long addr, unsigned long flags); +extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose, + unsigned long addr, unsigned long flags); + +#define pci_phys_to_bus(dev, addr, flags) \ + pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) +#define pci_bus_to_phys(dev, addr, flags) \ + pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) + +#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) +#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) + +extern int pci_hose_read_config_byte(struct pci_controller *hose, + pci_dev_t dev, int where, u8 *val); +extern int pci_hose_read_config_word(struct pci_controller *hose, + pci_dev_t dev, int where, u16 *val); +extern int pci_hose_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u32 *val); +extern int pci_hose_write_config_byte(struct pci_controller *hose, + pci_dev_t dev, int where, u8 val); +extern int pci_hose_write_config_word(struct pci_controller *hose, + pci_dev_t dev, int where, u16 val); +extern int pci_hose_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u32 val); + +extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); +extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); +extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); +extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); +extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); +extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); + +extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u8 *val); +extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u16 *val); +extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u8 val); +extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u16 val); + +extern void pci_register_hose(struct pci_controller* hose); +extern struct pci_controller* pci_bus_to_hose(int bus); + +extern int pci_hose_scan(struct pci_controller *hose); +extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); + +extern void pciauto_region_init(struct pci_region* res); +extern void pciauto_region_align(struct pci_region *res, unsigned long size); +extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); +extern void pciauto_setup_device(struct pci_controller *hose, + pci_dev_t dev, int bars_num, + struct pci_region *mem, + struct pci_region *io); +void pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); + +extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); +extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); + +extern int pci_hose_config_device(struct pci_controller *hose, + pci_dev_t dev, + unsigned long io, + unsigned long mem, + unsigned long command); + +#ifdef CONFIG_MPC824X +extern void pci_mpc824x_init (bd_t *bd, struct pci_controller *hose); +#endif + +#endif /* _PCI_H */ diff --git a/include/pci_ids.h b/include/pci_ids.h new file mode 100644 index 0000000..2104965 --- /dev/null +++ b/include/pci_ids.h @@ -0,0 +1,1515 @@ +/* + * PCI Class, Vendor and Device IDs + * + * Please keep sorted. + */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_SP_DPIO 0x1100 +#define PCI_CLASS_SP_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. Sort key: vendor first, device next. */ + +#define PCI_VENDOR_ID_DYNALINK 0x0675 +#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 + +#define PCI_VENDOR_ID_BERKOM 0x0871 +#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 +#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 +#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 +#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 + +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_6010 0x6010 +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 +#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C1510 0x0010 +#define PCI_DEVICE_ID_NCR_53C875J 0x008f +#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 + +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215LG 0x4c47 +#define PCI_DEVICE_ID_ATI_264LT 0x4c54 +#define PCI_DEVICE_ID_ATI_264VT 0x5654 +#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 +#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 +#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b +#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c +#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 +#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 +#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 +#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87560_LIO 0x000e +#define PCI_DEVICE_ID_NS_87560_USB 0x0012 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 +#define PCI_DEVICE_ID_DEC_21153 0x0025 +#define PCI_DEVICE_ID_DEC_21154 0x0026 +#define PCI_DEVICE_ID_DEC_21285 0x1065 +#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_PYTHON 0x002d +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_CPC700 0x00f9 +#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc +#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105 +#define PCI_DEVICE_ID_IBM_405GP 0x0156 +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff + +#define PCI_VENDOR_ID_COMPEX2 0x101a // pci.ids says "AT&T GIS (NCR)" +#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 + +#define PCI_VENDOR_ID_AMI 0x101e +#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 +#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 +#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 +#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 +#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 +#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404 +#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408 +#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 +#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B +#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 +#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 +#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_939A 0x939A +#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 +#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 +#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 +#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 +#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 +#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 +#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 +#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_VIA 0x4536 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 +#define PCI_DEVICE_ID_CT_69000 0x00c0 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 +#define PCI_DEVICE_ID_NEC_NILE4 0x005a + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_300 0x0300 +#define PCI_DEVICE_ID_SI_530 0x0530 +#define PCI_DEVICE_ID_SI_540 0x0540 +#define PCI_DEVICE_ID_SI_540_VGA 0x5300 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_620 0x0620 +#define PCI_DEVICE_ID_SI_630 0x0630 +#define PCI_DEVICE_ID_SI_730 0x0730 +#define PCI_DEVICE_ID_SI_630_VGA 0x6300 +#define PCI_DEVICE_ID_SI_730_VGA 0x7300 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5300 0x5300 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_5598 0x5598 +#define PCI_DEVICE_ID_SI_5600 0x5600 +#define PCI_DEVICE_ID_SI_6300 0x6300 +#define PCI_DEVICE_ID_SI_6306 0x6306 +#define PCI_DEVICE_ID_SI_6326 0x6326 +#define PCI_DEVICE_ID_SI_7001 0x7001 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C861 0xc861 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_ELSA 0x1048 +#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 +#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_1130 0xac12 +#define PCI_DEVICE_ID_TI_1031 0xac13 +#define PCI_DEVICE_ID_TI_1131 0xac15 +#define PCI_DEVICE_ID_TI_1250 0xac16 +#define PCI_DEVICE_ID_TI_1220 0xac17 +#define PCI_DEVICE_ID_TI_1221 0xac19 +#define PCI_DEVICE_ID_TI_1210 0xac1a +#define PCI_DEVICE_ID_TI_1450 0xac1b +#define PCI_DEVICE_ID_TI_1225 0xac1c +#define PCI_DEVICE_ID_TI_1251A 0xac1d +#define PCI_DEVICE_ID_TI_1211 0xac1e +#define PCI_DEVICE_ID_TI_1251B 0xac1f +#define PCI_DEVICE_ID_TI_1420 0xac51 + +#define PCI_VENDOR_ID_SONY 0x104d +#define PCI_DEVICE_ID_SONY_CXD3222 0x8039 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a +#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 + +#define PCI_VENDOR_ID_ANIGMA 0x1051 +#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 + +#define PCI_VENDOR_ID_EFAR 0x1055 +#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462 +#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 +#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 +#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 +#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 +#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e +#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 +#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 + +#define PCI_VENDOR_ID_YAMAHA 0x1073 +#define PCI_DEVICE_ID_YAMAHA_724 0x0004 +#define PCI_DEVICE_ID_YAMAHA_724F 0x000d +#define PCI_DEVICE_ID_YAMAHA_740 0x000a +#define PCI_DEVICE_ID_YAMAHA_740C 0x000c +#define PCI_DEVICE_ID_YAMAHA_744 0x0010 +#define PCI_DEVICE_ID_YAMAHA_754 0x0012 + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 +#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_648 0x0648 +#define PCI_DEVICE_ID_CMD_649 0x0649 +#define PCI_DEVICE_ID_CMD_670 0x0670 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e +#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_DEVICE_ID_SGI_IOC3 0x0003 + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_R685 0x1030 +#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a +#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 +#define PCI_DEVICE_ID_PLX_1077 0x1077 +#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 +#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 +#define PCI_DEVICE_ID_PLX_R753 0x1152 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C985 0x0001 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M1541 0x1541 +#define PCI_DEVICE_ID_AL_M1543 0x1543 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M5243 0x5243 +#define PCI_DEVICE_ID_AL_M5451 0x5451 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_TCONRAD 0x10da +#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 +#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 +#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 +#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C +#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 +#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 +#define PCI_DEVICE_ID_INTERG_2000 0x2000 +#define PCI_DEVICE_ID_INTERG_2010 0x2010 +#define PCI_DEVICE_ID_INTERG_5000 0x5000 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_CREATIVE 0x1102 // duplicate: ECTIVA +#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 + +#define PCI_VENDOR_ID_ECTIVA 0x1102 // duplicate: CREATIVE +#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 +#define PCI_DEVICE_ID_TTI_HPT366 0x0004 + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_8363_0 0x0305 +#define PCI_DEVICE_ID_VIA_8371_0 0x0391 +#define PCI_DEVICE_ID_VIA_8501_0 0x0501 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C596 0x0596 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 +#define PCI_DEVICE_ID_VIA_8601_0 0x0601 +#define PCI_DEVICE_ID_VIA_8605_0 0x0605 +#define PCI_DEVICE_ID_VIA_82C680 0x0680 +#define PCI_DEVICE_ID_VIA_82C686 0x0686 +#define PCI_DEVICE_ID_VIA_82C691 0x0691 +#define PCI_DEVICE_ID_VIA_82C693 0x0693 +#define PCI_DEVICE_ID_VIA_82C693_1 0x0698 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C416 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_6305 0x3044 +#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 +#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 +#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 +#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 +#define PCI_DEVICE_ID_VIA_8233_5 0x3059 +#define PCI_DEVICE_ID_VIA_8233_7 0x3065 +#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 +#define PCI_DEVICE_ID_VIA_8233_0 0x3074 +#define PCI_DEVICE_ID_VIA_8633_0 0x3091 +#define PCI_DEVICE_ID_VIA_8367_0 0x3099 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_8231 0x8231 +#define PCI_DEVICE_ID_VIA_8231_4 0x8235 +#define PCI_DEVICE_ID_VIA_8365_1 0x8305 +#define PCI_DEVICE_ID_VIA_8371_1 0x8391 +#define PCI_DEVICE_ID_VIA_8501_1 0x8501 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 +#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 +#define PCI_DEVICE_ID_VIA_8601_1 0x8601 +#define PCI_DEVICE_ID_VIA_8505_1 0X8605 +#define PCI_DEVICE_ID_VIA_8633_1 0xB091 +#define PCI_DEVICE_ID_VIA_8367_1 0xB099 + +#define PCI_VENDOR_ID_SMC2 0x1113 +#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 + +#define PCI_VENDOR_ID_IDT 0x111d +#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 + +#define PCI_VENDOR_ID_EICON 0x1133 +#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001 +#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 +#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003 +#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 +#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 +#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 +#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 +#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 +#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SYSKONNECT 0x1148 +#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000 +#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 +#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 +#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 +#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 +#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 +#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 +#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 + +#define PCI_VENDOR_ID_SBE 0x1176 +#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 +#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 +#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 +#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 +#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 +#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 +#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 +#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 +#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 +#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 +#define PCI_DEVICE_ID_ARTOP_8060 0x8060 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 + +#define PCI_VENDOR_ID_GALILEO 0x11ab +#define PCI_DEVICE_ID_GALILEO_GT64011 0x4146 +#define PCI_DEVICE_ID_GALILEO_GT64111 0x4146 +#define PCI_DEVICE_ID_GALILEO_GT96100 0x9652 +#define PCI_DEVICE_ID_GALILEO_GT96100A 0x9653 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V350 0x0001 +#define PCI_DEVICE_ID_V3_V961 0x0002 +#define PCI_DEVICE_ID_V3_V351 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 +#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 +#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 +#define PCI_DEVICE_ID_PC300_RX_2 0x0300 +#define PCI_DEVICE_ID_PC300_RX_1 0x0301 +#define PCI_DEVICE_ID_PC300_TE_2 0x0310 +#define PCI_DEVICE_ID_PC300_TE_1 0x0311 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 +#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 +#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_DEVICE_ID_AVM_B1 0x0700 +#define PCI_DEVICE_ID_AVM_C4 0x0800 +#define PCI_DEVICE_ID_AVM_A1 0x0a00 +#define PCI_DEVICE_ID_AVM_T1 0x1200 + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 +#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 +#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000 +#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 + +#define PCI_VENDOR_ID_ROCKWELL 0x127A + +#define PCI_VENDOR_ID_ITE 0x1283 +#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 +#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 + +/* formerly Platform Tech */ +#define PCI_VENDOR_ID_ESS_OLD 0x1285 +#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_VENDOR_ID_USR 0x12B9 + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 +#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 + +#define PCI_VENDOR_ID_AUREAL 0x12eb +#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 +#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 +#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 +#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 +#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 +#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 +#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 +#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 +#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 +#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 +#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 +#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 +#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 +#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 +#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 +#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 +#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 +#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 +#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 +#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 +#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 +#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 +#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 + +#define PCI_VENDOR_ID_DOMEX 0x134a +#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 + +#define PCI_VENDOR_ID_QUATECH 0x135C +#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 +#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 +#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 +#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 + +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 +#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 +#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 + +#define PCI_VENDOR_ID_HYPERCOPE 0x1365 +#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 +#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 +#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 +#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 +#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 +#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109 + +#define PCI_VENDOR_ID_LMC 0x1376 +#define PCI_DEVICE_ID_LMC_HSSI 0x0003 +#define PCI_DEVICE_ID_LMC_DS3 0x0004 +#define PCI_DEVICE_ID_LMC_SSI 0x0005 +#define PCI_DEVICE_ID_LMC_T1 0x0006 + +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a + +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 + +#define PCI_VENDOR_ID_MOXA 0x1393 +#define PCI_DEVICE_ID_MOXA_C104 0x1040 +#define PCI_DEVICE_ID_MOXA_C168 0x1680 +#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 +#define PCI_DEVICE_ID_MOXA_C218 0x2180 +#define PCI_DEVICE_ID_MOXA_C320 0x3200 + +#define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 +#define PCI_DEVICE_ID_CCD_B000 0xb000 +#define PCI_DEVICE_ID_CCD_B006 0xb006 +#define PCI_DEVICE_ID_CCD_B007 0xb007 +#define PCI_DEVICE_ID_CCD_B008 0xb008 +#define PCI_DEVICE_ID_CCD_B009 0xb009 +#define PCI_DEVICE_ID_CCD_B00A 0xb00a +#define PCI_DEVICE_ID_CCD_B00B 0xb00b +#define PCI_DEVICE_ID_CCD_B00C 0xb00c +#define PCI_DEVICE_ID_CCD_B100 0xb100 + +#define PCI_VENDOR_ID_3WARE 0x13C1 +#define PCI_DEVICE_ID_3WARE_1000 0x1000 + +#define PCI_VENDOR_ID_ABOCOM 0x13D1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 + +#define PCI_VENDOR_ID_CMEDIA 0x13f6 +#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 +#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 +#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 +#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 + +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ +#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ +#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ +#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ +#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ +#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 + +#define PCI_VENDOR_ID_TIMEDIA 0x1409 +#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 + +#define PCI_VENDOR_ID_OXSEMI 0x1415 +#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 +#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x950A +#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 + +#define PCI_VENDOR_ID_AIRONET 0x14b9 +#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001 +#define PCI_DEVICE_ID_AIRONET_4800 0x4500 // values switched? see +#define PCI_DEVICE_ID_AIRONET_4500 0x4800 // drivers/net/aironet4500_card.c + +#define PCI_VENDOR_ID_TITAN 0x14D2 +#define PCI_DEVICE_ID_TITAN_100 0xA001 +#define PCI_DEVICE_ID_TITAN_200 0xA005 +#define PCI_DEVICE_ID_TITAN_400 0xA003 +#define PCI_DEVICE_ID_TITAN_800B 0xA004 + +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 + +#define PCI_VENDOR_ID_AFAVLAB 0x14db +#define PCI_DEVICE_ID_AFAVLAB_TK9902 0x2120 + +#define PCI_VENDOR_ID_SYBA 0x1592 +#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 +#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 + +#define PCI_VENDOR_ID_MORETON 0x15aa +#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 + +#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 +#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 + +#define PCI_VENDOR_ID_GENROCO 0x5555 +#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_21145 0x0039 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_82559 0x1030 +#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 +#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 +#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412 +#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 +#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 +#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 +#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 +#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 +#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422 +#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 +#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 +#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 +#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 +#define PCI_DEVICE_ID_INTEL_82820FW_0 0x2440 +#define PCI_DEVICE_ID_INTEL_82820FW_1 0x2442 +#define PCI_DEVICE_ID_INTEL_82820FW_2 0x2443 +#define PCI_DEVICE_ID_INTEL_82820FW_3 0x2444 +#define PCI_DEVICE_ID_INTEL_82820FW_4 0x2449 +#define PCI_DEVICE_ID_INTEL_82820FW_5 0x244b +#define PCI_DEVICE_ID_INTEL_82820FW_6 0x244e +#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 +#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 +#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 +#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 +#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a +#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b +#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600 +#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 +#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602 +#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603 +#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 +#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca + +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 +#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 +#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e +#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 +#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 +#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 +#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 +#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 +#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f +#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 +#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 +#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 +#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f +#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 +#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 +#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 +#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_SUBVENDOR_ID_EXSYS 0xd84d +#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 +#define PCI_DEVICE_ID_TIGERJET_100 0x0002 + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +#define PCI_VENDOR_ID_MICROGATE 0x13c0 +#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 +#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020 +#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 + +#define PCI_VENDOR_ID_SIS 0x1039 +#define PCI_DEVICE_ID_SIS_300 0x0300 +#define PCI_DEVICE_ID_SIS_540 0x5300 +#define PCI_DEVICE_ID_SIS_630 0x6300 diff --git a/include/scsi.h b/include/scsi.h index ee4c535..8929318 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -40,6 +40,8 @@ typedef struct SCSI_cmd_block{ unsigned char sensecmd[6]; /* Sense command */ unsigned long contr_stat; /* Controller Status */ unsigned long trans_bytes; /* tranfered bytes */ + + unsigned int priv; }ccb; /*----------------------------------------------------------- diff --git a/board/eltec/bab750/sym53c8xx.h b/include/sym53c8xx.h similarity index 100% rename from board/eltec/bab750/sym53c8xx.h rename to include/sym53c8xx.h