From: wdenk Date: Sun, 12 Nov 2000 00:42:24 +0000 (+0000) Subject: * Cleanup of PCMCIA / IDE code (thanks to Stefan Röse) X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=cf6c70d854de7ed8b2b8c2fa7781271e4b82f564;p=users%2Frw%2Fppcboot.git * Cleanup of PCMCIA / IDE code (thanks to Stefan Röse) * Added configuration for IVMS8 boards (Speech Design) * Added configuration for SM850 "Service Module" which has a MPC850 with Ethernet on SCC3 WARNING: you CANNOT use SMC1 when Ethernet is on SCC3 - parameter RAM conflicts! * Allow to use '\' to escape control characters (';' and '$') while parsing input - needed to be able to enter a `bootcmd' which contains more than one command and/or references to variables, which are resolved not before when running the command. * MBX8xx support (thanks to Marius Gröger) * Fix violation of BOOTP message format. * Allow for configurations which don't define some environment variables. * Unified handling of (default) load address. * Changed compiler options to reduce code size. --- diff --git a/CHANGELOG b/CHANGELOG index c08d9b6..9aa491d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -53,11 +53,17 @@ To do: (and it uses default address). ====================================================================== -Modifications since 0.6.0: +Modifications for 0.6.1: ====================================================================== +* Cleanup of PCMCIA / IDE code (thanks to Stefan Röse) + +* Added configuration for IVMS8 boards (Speech Design) + * Added configuration for SM850 "Service Module" which has a MPC850 with Ethernet on SCC3 + WARNING: you CANNOT use SMC1 when Ethernet is on SCC3 - parameter + RAM conflicts! * Allow to use '\' to escape control characters (';' and '$') while parsing input - needed to be able to enter a `bootcmd' which diff --git a/CREDITS b/CREDITS index 568b9ba..fbf7034 100644 --- a/CREDITS +++ b/CREDITS @@ -18,10 +18,6 @@ N: Andre Beaudin E: D: PCMCIA, Ethernet, TFTP -N: Roland Borde -E: 100.130266@germanynet.de -D: Ethernet, TFTP / BOOTP - N: Raphael Bossek E: raphael.bossek@solutions4linux.de D: 8xxrom-0.3.0 diff --git a/Makefile b/Makefile index 3965708..de5e12b 100644 --- a/Makefile +++ b/Makefile @@ -125,6 +125,14 @@ SPD823TS_config: unconfig echo "CPU = mpc8xx" >>config.mk ; \ echo "#include " >config.h +IVMS8_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = ivms8" >>config.mk ; \ + echo "CPU = mpc8xx" >>config.mk ; \ + echo "#include " >config.h + SM850_config : unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd include ; \ diff --git a/README b/README index 51a30d4..32a99fe 100644 --- a/README +++ b/README @@ -59,8 +59,10 @@ Directory Hierarchy: ==================== - common Misc architecture independend functions +- doc Documentation (don't expect too much) - examples Example code for standalone applications, etc. - include Header Files +- disk Harddisk interface code - net Networking code - ppc Files generic to PowerPC architecture - tools Tools to build S-Record or PPCBoot images, etc. @@ -73,6 +75,9 @@ Directory Hierarchy: - tqm8xx Files specific to TQM8xxL boards - etx094 Files specific to ETX_094 boards - spd8xx Files specific to SPD8xxTS boards +- ivms8 Files specific to IVMS8 boards +- SM850 Files specific to SM850 boards +- genietv Files specific to GENIETV boards - cogent Files specific to Cogent boards (need further configuration) - fads Files specific to Motorola FADS boards diff --git a/common/board.c b/common/board.c index 593fbcf..117e93b 100644 --- a/common/board.c +++ b/common/board.c @@ -319,7 +319,11 @@ void board_init_r (bd_t *bd, ulong dest_addr) printf (" FLASH: "); if ((flash_size = flash_init ()) > 0) { - printf ("%2ld MB\n", flash_size >> 20); + if (flash_size >= (1 << 20)) { + printf ("%2ld MB\n", flash_size >> 20); + } else { + printf ("%2ld kB\n", flash_size >> 10); + } } else { printf (failed); hang(); @@ -412,6 +416,13 @@ void board_init_r (bd_t *bd, ulong dest_addr) pcmcia_init(); #endif +#ifdef CONFIG_PCI_PNP + /* + * Do pci plug-n-play configuration + */ + pci_init(); +#endif + bd->bi_mon_fnc->malloc = malloc; bd->bi_mon_fnc->free = free; diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 367ebb5..36dd565 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -30,6 +30,9 @@ #include /* for PIO mode selection */ #include #include +#ifdef CONFIG_IDE_PCMCIA +#include +#endif #include #include #include @@ -94,6 +97,7 @@ static int pio_mode = CFG_PIO_MODE; /* ------------------------------------------------------------------------- */ +#ifdef CONFIG_IDE_PCMCIA /* * Allow configuration to select PCMCIA slot, * or try to generate a useful default @@ -190,16 +194,20 @@ typedef struct { */ /* ------------------------------------------------------------------------- */ +#endif /* CONFIG_IDE_PCMCIA */ + /* Current I/O Device */ static int curr_device = -1; /* Current offset for IDE0 / IDE1 bus access */ -static ulong bus_offset[IDE_MAXBUS] = { +static ulong bus_offset[CFG_IDE_MAXBUS] = { CFG_ATA_IDE0_OFFSET, +#ifdef CFG_ATA_IDE1_OFFSET CFG_ATA_IDE1_OFFSET, +#endif }; -#define ATA_CURR_BASE(dev) (ATA_IO_BASE+bus_offset[IDE_BUS(dev)]) +#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+bus_offset[IDE_BUS(dev)]) typedef struct ide_dev_id { ulong size; @@ -207,13 +215,23 @@ typedef struct ide_dev_id { uchar serial_no[20]; } ide_dev_id_t; -static int ide_bus_ok[IDE_MAXBUS]; -static ide_dev_id_t ide_device[IDE_MAXDEVICE]; +static int ide_bus_ok[CFG_IDE_MAXBUS]; +static ide_dev_id_t ide_device[CFG_IDE_MAXDEVICE]; /* ------------------------------------------------------------------------- */ +#ifdef CONFIG_IDE_LED static void ide_led (uchar led, uchar status); +#else +#define ide_led(a,b) /* dummy */ +#endif + +#ifdef CONFIG_IDE_RESET static void ide_reset (void); +#else +#define ide_reset() /* dummy */ +#endif + static void ide_ident (int device); static void ide_print (int device); static uchar ide_wait (int dev, ulong t); @@ -224,7 +242,12 @@ static void input_swap_data(int dev, ulong *sect_buf, int words); static void input_data(int dev, ulong *sect_buf, int words); static void output_data(int dev, ulong *sect_buf, int words); static void trim_trail (unsigned char *str, unsigned int len); + +#ifdef CONFIG_IDE_PCMCIA static void set_pcmcia_timing (int pmode); +#else +#define set_pcmcia_timing(a) /* dummy */ +#endif /* ------------------------------------------------------------------------- */ @@ -237,7 +260,11 @@ void do_ide (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) return; case 2: if (strncmp(argv[1],"res",3) == 0) { - puts ("\nReset IDE on PCMCIA " PCMCIA_SLOT_MSG ": "); + puts ("\nReset IDE" +#ifdef CONFIG_IDE_PCMCIA + " on PCMCIA " PCMCIA_SLOT_MSG +#endif + ": "); ide_init(bd); return; @@ -246,14 +273,14 @@ void do_ide (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) putc ('\n'); - for (i=0; i= IDE_MAXDEVICE)) { + if ((curr_device < 0) || (curr_device >= CFG_IDE_MAXDEVICE)) { puts ("\nno IDE devices available\n"); return; } @@ -263,7 +290,7 @@ void do_ide (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } else if (strncmp(argv[1],"part",4) == 0) { int dev, ok; - for (ok=0, dev=0; dev= IDE_MAXDEVICE) { + if (dev >= CFG_IDE_MAXDEVICE) { puts ("unknown device\n"); return; } @@ -481,8 +508,10 @@ void do_diskboot (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) void ide_init (bd_t *bd) { +#ifdef CONFIG_IDE_PCMCIA volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); +#endif unsigned char c; int i, bus; @@ -510,8 +539,10 @@ void ide_init (bd_t *bd) ide_led ((LED_IDE1 | LED_IDE2), 1); /* LED's on */ ide_reset (); +#ifdef CONFIG_IDE_PCMCIA /* PCMCIA / IDE initialization for common mem space */ pcmp->pcmc_pgcrb = 0; +#endif /* start in PIO mode 0 - most relaxed timings */ pio_mode = 0; @@ -521,8 +552,8 @@ void ide_init (bd_t *bd) * Wait for IDE to get ready. * According to spec, this can take up to 31 seconds! */ - for (bus=0; bus (ATA_RESET_TIME * 100)) { + if (i > (CFG_ATA_RESET_TIME * 100)) { puts ("** Timeout **\n"); ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */ return; @@ -564,8 +595,10 @@ void ide_init (bd_t *bd) ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */ curr_device = -1; - for (i=0; i -#ifdef CONFIG_FLASH_ENV_ADDR +#ifdef CFG_FLASH_ENV_ADDR .set env_not_stored_with_text, 1 #else @@ -67,4 +67,4 @@ env_size: .globl env_offset .set env_offset, CFG_FLASH_ENV_OFFSET -#endif /* CONFIG_FLASH_ENV_ADDR */ +#endif /* CFG_FLASH_ENV_ADDR */ diff --git a/cpci405/config.mk b/cpci405/config.mk index 1114324..83f07fe 100644 --- a/cpci405/config.mk +++ b/cpci405/config.mk @@ -25,8 +25,5 @@ # esd ADCIOP boards # -# FLASH: -TEXT_BASE = 0xFFFE0000 - -# SDRAM: -#TEXT_BASE = 0x00FE0000 +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 diff --git a/cpci405/cpci405.c b/cpci405/cpci405.c index fd5d7ab..43ac8e9 100644 --- a/cpci405/cpci405.c +++ b/cpci405/cpci405.c @@ -28,7 +28,6 @@ #define _NOT_USED_ 0xFFFFFFFF -void pci_init(void); /* ------------------------------------------------------------------------- */ @@ -49,7 +48,7 @@ int checkboard (void) int l_type; if (!s || strncmp(s, "CPCI405", 7)) { - printf ("### No HW ID - assuming CPCI405"); + printf ("### No HW ID - assuming CPCI405\n"); return (1); } @@ -63,11 +62,7 @@ int checkboard (void) for ( ; sflash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; @@ -228,7 +226,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info) for (i = 4; i < info->sector_count; i++) { info->start[i] = base + (i * 0x00010000) - 0x00030000; } - } else { + } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00004000; @@ -237,8 +235,8 @@ static void flash_get_offsets (ulong base, flash_info_t *info) for (; i >= 0; i--) { info->start[i] = base + i * 0x00010000; } + } } - } /*----------------------------------------------------------------------- @@ -449,13 +447,11 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) } /* set up sector start adress table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; @@ -464,7 +460,7 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) for (i = 4; i < info->sector_count; i++) { info->start[i] = base + (i * 0x00010000) - 0x00030000; } - } else { + } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00004000; @@ -473,6 +469,7 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) for (; i >= 0; i--) { info->start[i] = base + i * 0x00010000; } + } } /* check for protected sectors */ @@ -484,7 +481,7 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) info->protect[i] = addr2[4] & 1; #else addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if (info->flash_id & FLASH_MAN_SST) + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) info->protect[i] = 0; else info->protect[i] = addr2[2] & 1; @@ -562,27 +559,24 @@ void flash_erase (flash_info_t *info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - if (info->flash_id & FLASH_MAN_SST) - { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(50000); /* wait 50 ms */ - } - else - { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + udelay(50000); /* wait 50 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; } } diff --git a/etx094/flash.c b/etx094/flash.c index 7f6b832..6df2909 100644 --- a/etx094/flash.c +++ b/etx094/flash.c @@ -203,7 +203,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info) return; } - if (info->flash_id & FLASH_MAN_SST) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { for (i = 0; i < info->sector_count; i++) { info->start[i] = base + (i * 0x00002000); } @@ -423,7 +423,7 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) info->sector_count = CFG_MAX_FLASH_SECT; } - if (info->flash_id & FLASH_MAN_SST) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { for (i = 0; i < info->sector_count; i++) { info->start[i] = base + (i * 0x00002000); } diff --git a/include/asm/processor.h b/include/asm/processor.h index a0a96d9..7f8d7bf 100644 --- a/include/asm/processor.h +++ b/include/asm/processor.h @@ -453,6 +453,9 @@ #define PVR_403GC 0x00200200 #define PVR_403GCX 0x00201400 #define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/ata.h b/include/ata.h index 4474c3b..0f708cf 100644 --- a/include/ata.h +++ b/include/ata.h @@ -35,17 +35,9 @@ /* Register addressing depends on the hardware design; for instance, * 8-bit (register) and 16-bit (data) accesses might use different - * address spaces. This is implemented bythe following definitions. + * address spaces. This is implemented by the following definitions. */ -#define CFG_ATA_BASE_ADDR 0xFE100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_IDE1_OFFSET 0x0C00 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - #define ATA_IO_DATA(x) (CFG_ATA_DATA_OFFSET+(x)) #define ATA_IO_REG(x) (CFG_ATA_REG_OFFSET +(x)) #define ATA_IO_ALT(x) (CFG_ATA_ALT_OFFSET +(x)) @@ -122,8 +114,6 @@ #define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */ #define ATA_SECTORWORDS (512 / sizeof(unsigned long)) -#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */ - /* ------------------------------------------------------------------------- */ diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h index d804db4..e01ca1c 100644 --- a/include/config_CPCI405.h +++ b/include/config_CPCI405.h @@ -38,6 +38,7 @@ #define CONFIG_CPUCLOCK 200 #define CONFIG_BUSCLOCK 100 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #define CONFIG_BAUDRATE 9600 #if 0 @@ -68,8 +69,13 @@ #define CONFIG_PCI_PNP 1 /* include pci plug-and-play */ +#if 1 +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_IDE) & ~(CFG_CMD_ENV)) +#else #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ) & ~(CFG_CMD_ENV)) +#endif /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -108,20 +114,36 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +#define CFG_ATA_RESET_TIME 1 /* just try for 0.5 seconds */ + /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#if 1 -#define CFG_FLASH_BASE 0xFFFE0000 -#else -#define CFG_FLASH_BASE 0x00FE0000 -#endif +#define CFG_FLASH_BASE 0xFFFD0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data diff --git a/include/config_IVMS8.h b/include/config_IVMS8.h new file mode 100644 index 0000000..0eb58ef --- /dev/null +++ b/include/config_IVMS8.h @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +//#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 19200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/LinuxPPC " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if 0 +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */ +#else +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL & ~(CFG_CMD_NET)) +#endif /* 0 */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ +#define CONFIG_ETHADDR 00:d0:93:00:01:cb +#define CONFIG_IPADDR 10.0.0.98 +#define CONFIG_SERVERIP 10.0.0.1 +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000" +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ +#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ + +#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ +#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ +#define CFG_FLASH_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +#define CFG_FLASH_ENV_ADDR (CFG_FLASH_BASE+CFG_FLASH_ENV_OFFSET) +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +/* EARB, DBGC and DBPC are initialised by the HCW */ +/* => 0x000000C0 */ +#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00B0C0C0 */ +#define CFG_PLPRCR \ + ( (11 << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800014 */ +#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD101 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* 0x00C2 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* TIMEP=2 */ +#define CFG_RCCR 0x0200 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +/* EPROMs are 512kb */ +#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) + * + */ +#define SRAM_BASE 0xFE200000 /* SRAM bank */ +#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ + +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#define PER8_BASE 0xFE000000 /* PER8 bank */ +#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ + +#define SHARC_BASE 0xFE400000 /* SHARC bank */ +#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ + +/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ + +#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ +#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) +#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ + +#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ +#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) + +#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ +#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) +#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ +#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) +#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTB 204 + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MBMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ + MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 | \ + MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/config_SM850.h b/include/config_SM850.h index 636a954..2092d28 100644 --- a/include/config_SM850.h +++ b/include/config_SM850.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ + /* * High Level Configuration Options * (easy to change) @@ -36,8 +38,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_SM850 1 /*...on a MPC850 Service Module */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */ +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 #if 0 @@ -177,9 +179,16 @@ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ +#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#define CFG_PLPRCR \ + ( (5-1)< /*----------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:d0:93:00:01:cb -#define CONFIG_IPADDR 10.0.0.98 -#define CONFIG_SERVERIP 10.0.0.1 -#undef CONFIG_BOOTCOMMAND +#define CONFIG_ETHADDR 00:D0:93:00:01:CB +#define CONFIG_IPADDR 10.0.0.98 +#define CONFIG_SERVERIP 10.0.0.1 +#undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000" /*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ @@ -108,32 +107,32 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 #ifdef DEBUG -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ #else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #endif #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ @@ -143,8 +142,8 @@ #define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_FLASH_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ +#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_FLASH_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ /*----------------------------------------------------------------------- * Cache Configuration */ @@ -197,7 +196,7 @@ /* 0x00b0c0c0 */ #define CFG_PLPRCR \ ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ + PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ ) @@ -212,7 +211,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -273,12 +272,33 @@ #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) /*----------------------------------------------------------------------- - * + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_IDE_PCMCIA 1 /* PCMCIA interface required */ +#define CONFIG_IDE_LED 1 /* LED for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xFE100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_IDE1_OFFSET 0x0C00 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ + +#define CFG_ATA_RESET_TIME 60 /* spec allows up to 31 seconds */ + +/*----------------------------------------------------------------------- + * *----------------------------------------------------------------------- * */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 /* * Init Memory Controller: @@ -320,7 +340,7 @@ #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ #define PER8_BASE 0xFE000000 /* PER8 bank */ #define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ @@ -331,8 +351,8 @@ /* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ -#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) -#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) +#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ @@ -341,12 +361,12 @@ #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) #define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ -#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) -#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) +#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) #define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ -#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) -#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) +#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) +#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) /* * Memory Periodic Timer Prescaler */ @@ -376,7 +396,7 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #endif /* __CONFIG_H */ diff --git a/include/config_TQM855L.h b/include/config_TQM855L.h index 43adab4..814f4eb 100644 --- a/include/config_TQM855L.h +++ b/include/config_TQM855L.h @@ -179,7 +179,7 @@ * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * - * This is a 80 MHz CPU, so set PLL multiplication factor to 5 (5*16=80)! + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ #ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ #define CFG_PLPRCR \ diff --git a/include/flash.h b/include/flash.h index 64efb29..a81dc08 100644 --- a/include/flash.h +++ b/include/flash.h @@ -40,7 +40,7 @@ typedef struct { ulong size; /* total bank size in bytes */ ushort sector_count; /* number of erase units */ - ushort flash_id; /* combined device & manufacturer code */ + ulong flash_id; /* combined device & manufacturer code */ ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */ uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */ } flash_info_t; @@ -61,6 +61,10 @@ void flash_erase (flash_info_t *, int, int); #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */ #define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */ +#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */ + +#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ +#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ #define AMD_ID_F040B 0xA4 /* 29F040B ID ( 4 M, bottom boot sect) */ #define AMD_ID_F080B 0xD5 /* 29F0B0 ID ( 1 M) */ @@ -89,38 +93,42 @@ void flash_erase (flash_info_t *, int, int); * Internal FLASH identification codes */ -#define FLASH_AM040T 0x00 /* AMD AM29F040 */ -#define FLASH_AM040B 0x01 -#define FLASH_AM400T 0x02 /* AMD AM29LV400 */ -#define FLASH_AM400B 0x03 -#define FLASH_AM800T 0x04 /* AMD AM29LV800 */ -#define FLASH_AM800B 0x05 -#define FLASH_AM160T 0x06 /* AMD AM29LV160 */ -#define FLASH_AM160B 0x07 -#define FLASH_AM320T 0x08 /* AMD AM29LV320 */ -#define FLASH_AM320B 0x09 +#define FLASH_AM040T 0x0000 /* AMD AM29F040 */ +#define FLASH_AM040B 0x0001 +#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */ +#define FLASH_AM400B 0x0003 +#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */ +#define FLASH_AM800B 0x0005 +#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */ +#define FLASH_AM160B 0x0007 +#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ +#define FLASH_AM320B 0x0009 + +#define FLASH_SST200A 0x000A /* SST 39xF200A ID ( 2M = 128K x 16 ) */ +#define FLASH_SST400A 0x000B /* SST 39xF400A ID ( 4M = 256K x 16 ) */ +#define FLASH_SST800A 0x000C /* SST 39xF800A ID ( 8M = 512K x 16 ) */ +#define FLASH_SST160A 0x000D /* SST 39xF160A ID (16M = 1M x 16 ) */ -#define FLASH_SST200A 0x0A /* SST 39xF200A ID ( 2M = 128K x 16 ) */ -#define FLASH_SST400A 0x0B /* SST 39xF400A ID ( 4M = 256K x 16 ) */ -#define FLASH_SST800A 0x0C /* SST 39xF800A ID ( 8M = 512K x 16 ) */ -#define FLASH_SST160A 0x0D /* SST 39xF160A ID (16M = 1M x 16 ) */ +#define FLASH_STM800AB 0x0010 /* STM M29WF800AB ID ( 8M = 512K x 16 ) */ -#define FLASH_28F008S5 0x0E /* Intel 28F008S5 ( 1M = 64K x 16 ) */ +#define FLASH_28F008S5 0x0020 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ -#define FLASH_STM800AB 0x0F /* STM M29WF800AB ID ( 8M = 512K x 16 ) */ +#define FLASH_28F400_T 0x0022 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ +#define FLASH_28F400_B 0x0023 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ -#define FLASH_UNKNOWN 0xFF /* unknown flash type */ +#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ -#define FLASH_MAN_AMD 0x00 /* manufacturer offsets */ -#define FLASH_MAN_FUJ 0x10 -#define FLASH_MAN_SST 0x20 -#define FLASH_MAN_STM 0x40 -#define FLASH_MAN_INTEL 0x80 +#define FLASH_MAN_AMD 0x00000000 /* manufacturer offsets */ +#define FLASH_MAN_FUJ 0x00010000 +#define FLASH_MAN_SST 0x00020000 +#define FLASH_MAN_STM 0x00030000 +#define FLASH_MAN_INTEL 0x00040000 +#define FLASH_MAN_MT 0x00050000 -#define FLASH_TYPEMASK 0x0F /* extract FLASH type information */ -#define FLASH_VENDMASK 0xF0 /* extract FLASH vendor information */ +#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ +#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ #define FLASH_AMD_COMP 0x4F /* Up to this ID, FLASH is compatible */ /* with AMD, Fujitsu and SST */ @@ -131,7 +139,7 @@ void flash_erase (flash_info_t *, int, int); /*----------------------------------------------------------------------- * Timeout constants: * - * We can't find any spcifications for maximum chip erase times, + * We can't find any specifications for maximum chip erase times, * so these values are guestimates. */ #define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ diff --git a/include/ide.h b/include/ide.h index cca9a43..aa1f6dc 100644 --- a/include/ide.h +++ b/include/ide.h @@ -24,122 +24,10 @@ #ifndef _IDE_H #define _IDE_H -/* - * Definitions for PCMCIA control registers to operate in IDE mode - * - * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) - * to be done later (depending on CPU clock) - */ - -/* Window 0: - * Base: 0x04100000 CS1 - * Port Size: 2 Bytes - * Port Size: 16 Bit - * Common Memory Space - */ - -#define CFG_PCMCIA_PBR0 0xFE100000 -#define CFG_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ - | PCMCIA_PPS_16 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_PSLOT_B \ - | PCMCIA_PV \ - ) - -/* Window 1: - * Base: 0x04100080 CS1 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CFG_PCMCIA_PBR1 0xFE100080 -#define CFG_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_PSLOT_B \ - | PCMCIA_PV \ - ) - -/* Window 2: - * Base: 0x04100100 CS2 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CFG_PCMCIA_PBR2 0xFE100100 -#define CFG_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_PSLOT_B \ - | PCMCIA_PV \ - ) - -/* Window 3: - * not used - */ -#define CFG_PCMCIA_PBR3 0 -#define CFG_PCMCIA_POR3 0 - -/* Window 4: - * Base: 0x041000C00 CS1 - * Port Size: 2 Bytes - * Port Size: 16 Bit - * Common Memory Space - */ - -#define CFG_PCMCIA_PBR4 0xFE100C00 -#define CFG_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ - | PCMCIA_PPS_16 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_PSLOT_B \ - | PCMCIA_PV \ - ) - -/* Window 5: - * Base: 0x04100C80 CS1 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CFG_PCMCIA_PBR5 0xFE100C80 -#define CFG_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_PSLOT_B \ - | PCMCIA_PV \ - ) - -/* Window 6: - * Base: 0x04100D00 CS2 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CFG_PCMCIA_PBR6 0xFE100D00 -#define CFG_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_PSLOT_B \ - | PCMCIA_PV \ - ) - -/* Window 7: - * not used - */ -#define CFG_PCMCIA_PBR7 0 -#define CFG_PCMCIA_POR7 0 - - -#define ATA_IO_BASE CFG_PCMCIA_PBR0 - -#define IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define IDE_MAXDEVICE (IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ #define IDE_BUS(dev) (dev >> 1) +#ifdef CONFIG_IDE_LED + /* * LED Port */ @@ -147,6 +35,9 @@ #define LED_IDE1 0x01 #define LED_IDE2 0x02 #define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */ + +#endif /* CONFIG_IDE_LED */ + /* * Function Prototypes */ diff --git a/include/pcmcia.h b/include/pcmcia.h new file mode 100644 index 0000000..1f03376 --- /dev/null +++ b/include/pcmcia.h @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCMCIA_H +#define _PCMCIA_H + +/* + * Definitions for PCMCIA control registers to operate in IDE mode + * + * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) + * to be done later (depending on CPU clock) + */ + +/* Window 0: + * Base: 0x04100000 CS1 + * Port Size: 2 Bytes + * Port Size: 16 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR0 0xFE100000 +#define CFG_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ + | PCMCIA_PPS_16 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_PSLOT_B \ + | PCMCIA_PV \ + ) + +/* Window 1: + * Base: 0x04100080 CS1 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR1 0xFE100080 +#define CFG_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_PSLOT_B \ + | PCMCIA_PV \ + ) + +/* Window 2: + * Base: 0x04100100 CS2 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR2 0xFE100100 +#define CFG_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_PSLOT_B \ + | PCMCIA_PV \ + ) + +/* Window 3: + * not used + */ +#define CFG_PCMCIA_PBR3 0 +#define CFG_PCMCIA_POR3 0 + +/* Window 4: + * Base: 0x041000C00 CS1 + * Port Size: 2 Bytes + * Port Size: 16 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR4 0xFE100C00 +#define CFG_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ + | PCMCIA_PPS_16 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_PSLOT_B \ + | PCMCIA_PV \ + ) + +/* Window 5: + * Base: 0x04100C80 CS1 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR5 0xFE100C80 +#define CFG_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_PSLOT_B \ + | PCMCIA_PV \ + ) + +/* Window 6: + * Base: 0x04100D00 CS2 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR6 0xFE100D00 +#define CFG_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_PSLOT_B \ + | PCMCIA_PV \ + ) + +/* Window 7: + * not used + */ +#define CFG_PCMCIA_PBR7 0 +#define CFG_PCMCIA_POR7 0 + +#endif /* _PCMCIA_H */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 9cb212e..118d229 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -47,10 +47,10 @@ #define tcr 0x3da /* timer control register */ #define pit 0x3db /* programmable interval timer */ #define sgr 0x3b9 /* storage guarded reg */ - #define dcwr 0x3ba /* data cache write-thru reg*/ + #define dcwr 0x3ba /* data cache write-thru reg*/ #define sler 0x3bb /* storage little-endian reg */ #define cdbcr 0x3d7 /* cache debug cntrl reg */ - #define icdbdr 0x3d3 /* instr cache dbug data reg*/ + #define icdbdr 0x3d3 /* instr cache dbug data reg*/ #define ccr0 0x3b3 /* core configuration register */ #define dvc1 0x3b6 /* data value compare register 1 */ #define dvc2 0x3b7 /* data value compare register 2 */ @@ -81,22 +81,22 @@ #define DMA_DCR_BASE 0x100 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ @@ -173,7 +173,7 @@ /****************************************************************************** * Decompression Controller ******************************************************************************/ -#define DECOMP_DCR_BASE 0x14 +#define DECOMP_DCR_BASE 0x14 #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ /* values for kiar register - indirect addressing of these regs */ @@ -240,6 +240,64 @@ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +/* Bit definitions */ +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PCI_ARBIT_EN 0x00000400 + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 400 +#define VCO_MAX 800 + /****************************************************************************** * Memory Access Layer ******************************************************************************/ @@ -262,7 +320,7 @@ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ /*----------------------------------------------------------------------------- -| IIC Register Offsets +| IIC Register Offsets '----------------------------------------------------------------------------*/ #define IICMDBUF 0x00 #define IICSDBUF 0x02 @@ -283,11 +341,11 @@ /*----------------------------------------------------------------------------- | UART Register Offsets '----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 +#define DATA_REG 0x00 +#define DL_LSB 0x00 #define DL_MSB 0x01 #define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 +#define FIFO_CONTROL 0x02 #define LINE_CONTROL 0x03 #define MODEM_CONTROL 0x04 #define LINE_STATUS 0x05 @@ -303,5 +361,24 @@ #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long pllFwdDiv; + unsigned long pllFbkDiv; + unsigned long pllPlbDiv; + unsigned long pllPciDiv; + unsigned long pllExtBusDiv; + unsigned long pllOpbDiv; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long freqProcessor; + unsigned long freqPLB; + unsigned long freqPCI; + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pciClkSync; /* PCI clock is synchronous */ +} PPC405_SYS_INFO; + +#endif /* _ASMLANGUAGE */ #endif /* __PPC4XX_H__ */ diff --git a/include/ppcboot.h b/include/ppcboot.h index a12cb20..98bf5f7 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -36,9 +36,13 @@ #ifdef CONFIG_8xx #include #endif +#ifdef CONFIG_4xx +#include +#endif typedef unsigned char uchar; typedef volatile unsigned long vu_long; +typedef volatile unsigned short vu_short; #include #include @@ -221,6 +225,8 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); void udelay (unsigned long); +unsigned long usec2ticks (unsigned long usec); +unsigned long ticks2usec (unsigned long ticks); #if defined(CONFIG_WATCHDOG) void watchdog_reset(void); #endif /* CONFIG_WATCHDOG */ @@ -228,6 +234,9 @@ void watchdog_reset(void); /* $(CPU)/speed.c */ ulong get_gclk_freq (void); ulong get_bus_freq (ulong); +#ifdef CONFIG_PPC405GP +void get_sys_info (PPC405_SYS_INFO *); +#endif /* $(CPU)/cpu_init.c */ #ifdef CONFIG_8xx diff --git a/include/version.h b/include/version.h index 8ea6ba1..6636317 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define PPCBOOT_VERSION "ppcboot 0.6.0" +#define PPCBOOT_VERSION "ppcboot 0.6.1" #endif /* __VERSION_H__ */ diff --git a/ivms8/Makefile b/ivms8/Makefile new file mode 100644 index 0000000..408115a --- /dev/null +++ b/ivms8/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/ivms8/config.mk b/ivms8/config.mk new file mode 100644 index 0000000..95f036c --- /dev/null +++ b/ivms8/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IVMS8 boards +# + +TEXT_BASE = 0xFF000000 diff --git a/ivms8/flash.c b/ivms8/flash.c new file mode 100644 index 0000000..55bc365 --- /dev/null +++ b/ivms8/flash.c @@ -0,0 +1,732 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/*----------------------------------------------------------------------- + * Functions + */ +ulong flash_get_size (vu_long *addr, flash_info_t *info); + +int flash_write (uchar *, ulong, ulong); +flash_info_t *addr2info (ulong); + +static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); +static int write_data (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); +static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ + BR_MS_GPCM | BR_PS_16 | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b0; + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); + +#ifdef CFG_FLASH_ENV_ADDR + /* ENV protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_ENV_ADDR, + CFG_FLASH_ENV_ADDR+CFG_FLASH_ENV_SIZE-1, + &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + * Check or set protection status for monitor sectors + * + * The monitor always occupies the _first_ part of the _first_ Flash bank. + */ +static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info) +{ + int rc = 0; + int first = -1; + int last = -1; + int i; + ulong b_end; + + if ((info->flash_id == FLASH_UNKNOWN) && + (to < info->start[0]) ) { + return (0); + } + + b_end = info->start[0] + info->size - 1; /* bank end address */ + + for (i=0; isector_count; ++i) { + ulong end; /* last address in current sect */ + short s_end; + + s_end = info->sector_count - 1; + + end = (i == s_end) ? b_end : info->start[i + 1] - 1; + + if (from > end) { + continue; + } + if (to < info->start[i]) { + continue; + } + + if (from == info->start[i]) { + first = i; + if (last < 0) { + last = s_end; + } + } + if (to == end) { + last = i; + if (first < 0) { + first = 0; + } + } + } + + for (i=first; i<=last; ++i) { + if (flag & FLAG_PROTECT_CLEAR) { + info->protect[i] = 0; + } else if (flag & FLAG_PROTECT_SET) { + info->protect[i] = 1; + } + if (info->protect[i]) { + rc = 1; + } + } + return (rc); +} + + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_MT: + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * 0x00020000); + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + return; + + case FLASH_MAN_SST: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00002000); + } + return; + + case FLASH_MAN_AMD: + case FLASH_MAN_FUJ: + + /* set up sector start adress table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + return; + default: + printf ("Don't know sector ofsets for flash type 0x%lx\n", + info->flash_id); + return; + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("Fujitsu "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_MT: printf ("MT "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); + break; + case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); + break; + case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); + break; + case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); + break; + case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n"); + break; + case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n"); + break; + case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + ushort value; + vu_short *saddr = (vu_short *)addr; + + /* Read Manufacturer ID */ + saddr[0] = 0x0090; + value = saddr[0]; + + switch (value) { + case (AMD_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (SST_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_SST; + break; + case (STM_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_STM; + break; + case (MT_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_MT; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + saddr[0] = 0x00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = saddr[1]; /* device ID */ + + switch (value) { + case (AMD_ID_LV400T & 0xFFFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & 0xFFFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & 0xFFFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & 0xFFFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160T & 0xFFFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & 0xFFFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFFFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & 0xFFFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + case (SST_ID_xF200A & 0xFFFF): + info->flash_id += FLASH_SST200A; + info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ + info->size = 0x00080000; + break; + case (SST_ID_xF400A & 0xFFFF): + info->flash_id += FLASH_SST400A; + info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ + info->size = 0x00100000; + break; + case (SST_ID_xF800A & 0xFFFF): + info->flash_id += FLASH_SST800A; + info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ + info->size = 0x00200000; + break; /* => 2 MB */ + case (STM_ID_x800AB & 0xFFFF): + info->flash_id += FLASH_STM800AB; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + case (MT_ID_28F400_T & 0xFFFF): + info->flash_id += FLASH_28F400_T; + info->sector_count = 7; + info->size = 0x00080000; + break; /* => 512 kB */ + case (MT_ID_28F400_B & 0xFFFF): + info->flash_id += FLASH_28F400_B; + info->sector_count = 7; + info->size = 0x00080000; + break; /* => 512 kB */ + default: + info->flash_id = FLASH_UNKNOWN; + saddr[0] = 0x00FF; /* restore read mode */ + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + saddr[0] = 0x00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +void flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) { + printf ("Can erase only MT flash types - aborted\n"); + return; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *)(info->start[sect]); + unsigned short status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x0050; /* clear status register */ + *addr = 0x0020; /* erase setup */ + *addr = 0x00D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & 0x0080) == 0) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00FF; /* reset to read mode */ + return; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = 0x00FF; /* reset to read mode */ + } + } + printf (" done\n"); +} + +/*----------------------------------------------------------------------- + */ + +flash_info_t *addr2info (ulong addr) +{ + flash_info_t *info; + int i; + + for (i=0, info=&flash_info[0]; i= info->start[0]) && + (addr < (info->start[0] + info->size)) ) { + return ((info->flash_id == FLASH_UNKNOWN) ? NULL : info); + } + } + + return (NULL); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - target range includes protected sectors + * 8 - target address not in Flash memory + */ +int flash_write (uchar *src, ulong addr, ulong cnt) +{ + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info (addr); + flash_info_t *info_last = addr2info (end ); + flash_info_t *info; + + if (cnt == 0) { + return (0); + } + + if (!info_first || !info_last) { + return (8); + } + + for (info = info_first; info <= info_last; ++info) { + ulong b_end = info->start[0] + info->size; /* bank end addr */ + short s_end = info->sector_count - 1; + for (i=0; isector_count; ++i) { + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if ((end >= info->start[i]) && (addr < e_addr) && + (info->protect[i] != 0) ) { + return (4); + } + } + } + + /* finally write data to flash */ + for (info = info_first; info <= info_last && cnt>0; ++info) { + ulong len; + + len = info->start[0] + info->size - addr; + if (len > cnt) + len = cnt; + if ((i = write_buff(info, src, addr, len)) != 0) { + return (i); + } + cnt -= len; + addr += len; + src += len; + } + return (0); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 2 /* flash bus width in bytes */ + +static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i CFG_FLASH_WRITE_TOUT) { + *addr = 0x00FF; /* restore read mode */ + return (1); + } + } + + *addr = 0x00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/ivms8/ivms8.c b/ivms8/ivms8.c new file mode 100644 index 0000000..a3d7569 --- /dev/null +++ b/ivms8/ivms8.c @@ -0,0 +1,312 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +/* + * 50 MHz SHARC access using UPM A + */ +const uint sharc_table[] = +{ + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +/* + * 50 MHz SDRAM access using UPM B + */ +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */ + _NOT_USED_, + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00, + 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00, + 0xE1BBBC04, 0x1FF77C45, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84, + 0xFFFFFC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ + printf ("IVMS8\n"); + return (1); +} + +/* ------------------------------------------------------------------------- */ + +long int +initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + long int size_b0; + + /* this a ugly hack: DRAM init needs udelay() */ + /* unlock */ + immr->im_sitk.sitk_tbk = KAPWR_KEY; + /* write value */ + immr->im_sit.sit_tbscr |= TBSCR_TBE; + + /* enable SDRAM clock ("switch on" SDRAM */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */ + immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE ; /* output */ + immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE ; /* assert SDRAM CLKE */ + udelay(1); + +#if 0 + /* + * Map controller bank 2 to the SRAM bank at preliminary address. + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; +#endif + + /* + * Map controller bank 4 to the PER8 bank. + */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; + +#if 0 + /* Configure SHARC at UMA */ + upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint)); + /* Map controller bank 5 to the SHARC */ + memctl->memc_or5 = CFG_OR5; + memctl->memc_br5 = CFG_BR5; +#endif + + memctl->memc_mamr = 0x00001000; + + /* Configure SDRAM at UMB */ + upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + + udelay(200); + memctl->memc_mcr = 0x80806105; + udelay(1); + memctl->memc_mcr = 0x80806130; + udelay(1); + memctl->memc_mcr = 0x80806130; + udelay(1); + memctl->memc_mcr = 0x80806106; + + memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */ + + /* + * Check Bank 0 Memory Size for re-configuration + */ + size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + + memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE; + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + volatile long int *addr; + long int cnt, val; + + memctl->memc_mbmr = mamr_value; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + return (0); + } + + for (cnt = 1; ; cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + + if (val != (~cnt)) { + return (cnt * sizeof(long)); + } + } + /* NOTREACHED */ +} + +/* ------------------------------------------------------------------------- */ + +void reset_phy() +{ + immap_t *immr = (immap_t *)CFG_IMMR; + ushort sreg; + + /* De-assert Ethernet Powerdown */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */ + immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN ; /* output */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* assert SDRAM CLKE */ + udelay(1); + + /* + * RESET is implemented by a positive pulse of at least 1 us + * at the reset pin. + * + * Configure RESET pins for NS DP83843 PHY, and RESET chip. + * + * Note: The RESET pin is high active, but there is an + * inverter on the SPD823TS board... + */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET); + immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET; + /* assert RESET signal of PHY */ + immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET); + udelay (10); + /* de-assert RESET signal of PHY */ + immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET; + udelay (10); +} diff --git a/ivms8/ppcboot.lds b/ivms8/ppcboot.lds new file mode 100644 index 0000000..ec9e649 --- /dev/null +++ b/ivms8/ppcboot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/ivms8/ppcboot.lds.debug b/ivms8/ppcboot.lds.debug new file mode 100644 index 0000000..dadf55f --- /dev/null +++ b/ivms8/ppcboot.lds.debug @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/mbx8xx/flash.c b/mbx8xx/flash.c index 5dfabee..c236da3 100644 --- a/mbx8xx/flash.c +++ b/mbx8xx/flash.c @@ -167,7 +167,7 @@ void flash_print_info (flash_info_t *info) return; } - switch (info->flash_id >> 8) { + switch (info->flash_id >> 16) { case 0x1: printf ("AMD "); break; @@ -176,7 +176,7 @@ void flash_print_info (flash_info_t *info) break; } - switch (info->flash_id & 0xff) { + switch (info->flash_id & FLASH_TYPEMASK) { case AMD_ID_F040B: printf ("AM29F040B (4 Mbit)\n"); break; @@ -230,12 +230,12 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) devid &= 0xff; if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 8 | devid; + info->flash_id = vendor << 16 | devid; info->sector_count = 8; info->size = info->sector_count * 0x10000; } else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 8 | devid; + info->flash_id = vendor << 16 | devid; info->sector_count = 4; info->size = 4 * info->sector_count * 0x10000; } diff --git a/mpc8xx/cpu.c b/mpc8xx/cpu.c index 5a91811..0eb4727 100644 --- a/mpc8xx/cpu.c +++ b/mpc8xx/cpu.c @@ -75,6 +75,7 @@ static int check_CPU(long clock, uint pvr, uint immr) case 0x00300065 : printf("X" ID_STR "SRZPnnC"); break; case 0x00310065 : printf("X" ID_STR "SRZPnnC1"); m = 1; break; case 0x05010000 : printf("X" ID_STR "xxZPnnD3"); m = 1; break; + case 0x05020000 : printf("X" ID_STR "xxZPnnD4"); m = 1; break; /* this value is not documented anywhere */ @@ -333,12 +334,34 @@ void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* ------------------------------------------------------------------------- */ -/* - * We implement the delay by converting the delay (the number of - * microseconds to wait) into a number of time base ticks; then we - * watch the time base until it has incremented by that amount. - */ -void udelay(unsigned long usec) +unsigned long ticks2usec(unsigned long ticks) +{ + ulong tbclk; + /* Pointer to initial global data area */ + init_data_t *idata=(init_data_t *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET); + + if (((volatile immap_t *)CFG_IMMR)->im_clkrst.car_sccr & SCCR_TBS) { + tbclk = idata->cpu_speed / 16; + } else { + ulong oscclk = idata->cpu_speed / + ((((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT)+1); + tbclk = oscclk / 4; + } + /* usec = ticks * 1000000 / tbclk + * Multiplication would overflow at ~4.2e3 ticks, + * so we break it up into + * usec = ( ( ticks * 1000) / tbclk ) * 1000; + */ + ticks *= 1000L; + ticks /= tbclk; + ticks *= 1000L; + + return ((ulong)ticks); +} + +/* ------------------------------------------------------------------------- */ + +unsigned long usec2ticks(unsigned long usec) { ulong tbclk; ulong ticks; @@ -354,6 +377,20 @@ void udelay(unsigned long usec) } ticks = ((usec * (tbclk/1000)) + 500) / 1000; + return (ticks); +} + +/* ------------------------------------------------------------------------- */ + +/* + * We implement the delay by converting the delay (the number of + * microseconds to wait) into a number of time base ticks; then we + * watch the time base until it has incremented by that amount. + */ +void udelay(unsigned long usec) +{ + ulong ticks = usec2ticks (usec); + wait_ticks (ticks); } diff --git a/mpc8xx/cpu_init.c b/mpc8xx/cpu_init.c index 449a38e..c39d94c 100644 --- a/mpc8xx/cpu_init.c +++ b/mpc8xx/cpu_init.c @@ -107,7 +107,8 @@ cpu_init_f (volatile immap_t *immr) * has been determined */ -#if defined(CONFIG_SPD823TS) || (defined(CONFIG_MPC860T) && defined(CONFIG_FADS)) +#if defined(CONFIG_SPD823TS) || defined(CONFIG_IVMS8) || \ + (defined(CONFIG_MPC860T) && defined(CONFIG_FADS)) /* XXX - FIXME - XXX * I still don't understand why some systems work only with this * statement here, and others work only without it. @@ -127,7 +128,7 @@ cpu_init_f (volatile immap_t *immr) memctl->memc_br0 = CFG_BR0_PRELIM; memctl->memc_or0 = CFG_OR0_PRELIM; -#ifndef CONFIG_GENIETV +#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) memctl->memc_or1 = CFG_OR1_PRELIM; memctl->memc_br1 = CFG_BR1_PRELIM; #endif diff --git a/mpc8xx/fec.c b/mpc8xx/fec.c new file mode 100644 index 0000000..a38e102 --- /dev/null +++ b/mpc8xx/fec.c @@ -0,0 +1,480 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define BD_OFFSET 0x860 /* offset to begin of DPRAM + allocation for serial IF*/ + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 1000000 + +/* static char rxbuf[PKTBUFSRX][ DBUF_LENGTH ]; */ +static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx; + + +int eth_send(volatile void *packet, int length) +{ + int i, j=0; +#if 0 + volatile char *in, *out; +#endif + + /* section 16.9.23.3 + * Wait for ready + */ +#if 0 + while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); + out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); + in = packet; + for(i = 0; i < length; i++) { + *out++ = *in++; + } + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); + while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; + +#ifdef ET_DEBUG + printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); +#endif + i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; + + /* wrap around buffer index when necessary */ + if (txIdx >= TX_BUF_CNT) txIdx = 0; +#endif + + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX not ready\n"); + rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX timeout\n"); +#ifdef ET_DEBUG + printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); +#endif + i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; + return i; +} + +int eth_rx(void) +{ + int length; + + for (;;) + { + /* section 16.9.23.2 */ + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) + { +#ifdef ET_DEBUG + printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); +#endif + } + else + { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the FEC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } + else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + } + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ + +int eth_init(bd_t *bis) +{ + + int i; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile fec_t *fecp = &(immr->im_cpm.cp_fec); + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routinewhich is + * still in progress. + */ + fecp->fec_ecntrl = 1; + udelay (20); + + /* We use striclty polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any outstanding interrupt. + */ + fecp->fec_ievent = 0xffc0; + + /* Reset all multicast. + */ + fecp->fec_hash_table_high = 0; + fecp->fec_hash_table_low = 0; + + /* Set maximum receive buffer size. + */ + fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; + fecp->fec_r_hash = PKT_MAXBUF_SIZE; + + /* Configure all of port D for MII. + */ + immr->im_ioport.iop_pdpar = 0x1fff; + + /* Bits moved from Rev. D onward */ + if ((_get_IMMR() & 0xffff) < 0x0501) { + immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ + } else { + immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ + } + + /* Set MII speed to 2.5 MHz + */ + fecp->fec_mii_speed = fep->phy_speed = + ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e; + + + rxIdx = 0; + txIdx = 0; + + /* assign static pointer to BD area */ + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + BD_OFFSET); + + /* Set receive and transmit descriptor base + */ + fecp->fec_r_des_start = (unsigned int)(&rtx->rxbd[0]); + fecp->fec_x_des_start = (unsigned int)(&rtx->txbd[0]); + + +#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) + /* Configure port A pins for Txd and Rxd. + */ + immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); + immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); + immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; +#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) + /* Configure port B pins for Txd and Rxd. + */ + immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); + immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); + immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; +#else +#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined +#endif + +#if defined(PC_ENET_LBK) + /* Configure port C pins to disable External Loopback + */ + immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; + immr->im_ioport.iop_pcdir |= PC_ENET_LBK; + immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; + immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ +#endif /* PC_ENET_LBK */ + + /* Configure port C pins to enable CLSN and RENA. + */ + immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); + immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); + immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port A for TCLK and RCLK. + */ + immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); + immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); + + /* + * Configure Serial Interface clock routing -- see section 16.7.5.3 + * First, clear all FEC bits to zero, then set the ones we want. + */ + + immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; + immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; + + + /* + * Initialize SDCR -- see section 16.9.23.7 + * SDMA configuration register + */ + immr->im_siu_conf.sc_sdcr = 0x01; + + + /* + * Setup FEC Ethernet Parameter RAM + */ + + pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ + pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ + + pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ + + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + + for (i = 0; i < PKTBUFSRX; i++) + { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + } + + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Add PADs to Short FRAMES, Wrap, Last, Tx CRC + */ + + for (i = 0; i < TX_BUF_CNT; i++) + { + rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; + } + + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* + * Enter Command: Initialize Rx Params for FEC + */ + + do { /* Spin until ready to issue command */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* Issue command */ + immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + + /* + * Ethernet Specific Parameter RAM + * see table 13-16, pg. 660, + * pg. 681 (example with suggested settings) + */ + + pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ + pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ + pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ + pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ + pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ + pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ + + pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ + pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ + pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ + + pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ + pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ + + pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ + pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ + pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ + pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ + +#define ea bis->bi_enetaddr + pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + + pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ + pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ + pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ + pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ + pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ + pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ + pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ + pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ + + /* + * Enter Command: Initialize Tx Params for FEC + */ + + do { /* Spin until ready to issue command */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* Issue command */ + immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + + /* + * Mask all Events in SCCM - we use polling mode + */ + immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; + + /* + * Clear Events in SCCE -- Clear bits by writing 1's + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); + + + /* + * Initialize GSMR High 32-Bits + * Settings: Normal Mode + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; + + /* + * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive + * Settings: + * TCI = Invert + * TPL = 48 bits + * TPP = Repeating 10's + * MODE = Ethernet + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \ + SCC_GSMRL_TPL_48 | \ + SCC_GSMRL_TPP_10 | \ + SCC_GSMRL_MODE_ENET); + + /* + * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; + + /* + * Initialize the PSMR + * Settings: + * CRC = 32-Bit CCITT + * NIB = Begin searching for SFD 22 bits after RENA + * BRO = Reject broadcast packets + * PROMISCOUS = Catch all packets regardless of dest. MAC adress + */ + immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22 + /* | SCC_PMSR_BRO | SCC_PMSR_PRO */); + + /* + * Configure Ethernet TENA Signal + */ + +#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) + immr->im_ioport.iop_pcpar |= PC_ENET_TENA; + immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; +#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) + immr->im_cpm.cp_pbpar |= PB_ENET_TENA; + immr->im_cpm.cp_pbdir |= PB_ENET_TENA; +#else +#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined +#endif + +#if defined(CONFIG_FADS) && defined(CONFIG_MPC860T) + /* + * Port C is used to control the PHY,MC68160. + */ + immr->im_ioport.iop_pcdir |= + (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); + + immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; + immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#endif /* FADS860T */ + +#ifdef CONFIG_MBX + board_ether_init(); +#endif + + /* + * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + return 1; +} + + + +void eth_halt(void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); +} + +#if 0 +void restart(void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); +} +#endif + +#endif /* CFG_CMD_NET */ diff --git a/mpc8xx/interrupts.c b/mpc8xx/interrupts.c index 1e2962a..6ba6299 100644 --- a/mpc8xx/interrupts.c +++ b/mpc8xx/interrupts.c @@ -281,7 +281,6 @@ cpm_interrupt_init (void) /****************************************************************************/ - volatile ulong timestamp = 0; /* @@ -313,19 +312,26 @@ void timer_interrupt(struct pt_regs *regs) /****************************************************************************/ +static unsigned long timer_base; + void reset_timer (void) { - timestamp = 0; + timer_base = 0; } ulong get_timer (ulong base) { - return (timestamp - base); + unsigned long usec; + extern unsigned long long get_ticks(void); + + usec = ticks2usec((unsigned long)get_ticks()); + + return (timer_base - base + (usec / 1000)); /* millisec timer */ } void set_timer (ulong t) { - timestamp = t; + timer_base = t; } /****************************************************************************/ diff --git a/mpc8xx/scc.h b/mpc8xx/scc.h deleted file mode 100644 index 25d5217..0000000 --- a/mpc8xx/scc.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * The number of receive packet buffers, and the required packet buffer - * alignment in memory. - */ -#define PKTBUFSRX 4 -#define PKTALIGN 32 diff --git a/mpc8xx/serial.c b/mpc8xx/serial.c index 2f2fa74..86dc233 100644 --- a/mpc8xx/serial.c +++ b/mpc8xx/serial.c @@ -74,12 +74,18 @@ serial_init (ulong cpu_clock, int baudrate) */ im->im_siu_conf.sc_sdcr = 1; -#ifdef CFG_SDSR + /* clear error conditions */ +#ifdef CFG_SDSR im->im_sdma.sdma_sdsr = CFG_SDSR; +#else + im->im_sdma.sdma_sdsr = 0x83; #endif -#ifdef CFG_SDMR + /* clear SDMA interrupt mask */ +#ifdef CFG_SDMR im->im_sdma.sdma_sdmr = CFG_SDMR; +#else + im->im_sdma.sdma_sdmr = 0x00; #endif #if defined(CONFIG_8xx_CONS_SMC1) diff --git a/mpc8xx/start.S b/mpc8xx/start.S index d41e7a2..dba72f0 100644 --- a/mpc8xx/start.S +++ b/mpc8xx/start.S @@ -89,6 +89,8 @@ version_string: . = EXC_OFF_SYS_RESET .globl _start _start: + lis r3, CFG_IMMR@h /* position IMMR */ + mtspr 638, r3 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ b boot_cold @@ -159,9 +161,7 @@ in_flash: /* initialize some SPRs that are hard to access from C */ /*----------------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* position IMMR and */ - mtspr 638, r3 /* pass r3 as arg1 to C routine */ - + lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */ ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ /* @@ -450,6 +450,17 @@ wait_ticks: blt 2b 3: blr +/* + * read timebase as "long long" + */ + .globl get_ticks +get_ticks: +1: mftbu r3 + mftb r4 + mftbu r5 + cmp 0,r3,r5 + bne 1b + blr /* * unsigned int get_immr (unsigned int mask) diff --git a/ppc4xx/405gp_pci.c b/ppc4xx/405gp_pci.c index 91e80b6..caae0f9 100644 --- a/ppc4xx/405gp_pci.c +++ b/ppc4xx/405gp_pci.c @@ -27,6 +27,7 @@ #ifdef CONFIG_PPC405GP +#ifdef CONFIG_PCI_PNP /*#define DEBUG*/ @@ -229,12 +230,8 @@ int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width) /*--------------------------------------------------------------------------+ | Ensure interrupts disabled for pass2 errata #6. +--------------------------------------------------------------------------*/ -#if 0 /* test-only */ - msr = ppcAndMsr(~(ppcMsrEE|ppcMsrCE)); -#else msr = get_msr(); set_msr(msr & ~(MSR_EE|MSR_CE)); -#endif /*--------------------------------------------------------------------------+ | bit 31 must be 1 and bits 1:0 must be 0 (note Little Endian bit notation) @@ -267,11 +264,7 @@ int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width) /*--------------------------------------------------------------------------+ | Restore msr (for pass2 errata #6). +--------------------------------------------------------------------------*/ -#if 0 /* test-only */ - (void)ppcMtmsr(msr); -#else set_msr(msr); -#endif return (0); } @@ -353,7 +346,7 @@ void PCI_Scan(int BusNum) void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) { int AddrSlot, i; - unsigned long AddrDesc, AddrProg, Min_Gnt_Val; + unsigned long AddrDesc, AddrProg, Min_Gnt_Val, int_line; for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++) { @@ -409,9 +402,30 @@ void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) Min_Gnt_Val = 0x80; PCI_Write_CFG_Reg(BusDevFunc, PCILATENCYTIM, Min_Gnt_Val, 1); -#if 1 /* test-only */ + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch ((BusDevFunc >> 11) & 0x03) + { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + PCI_Write_CFG_Reg(BusDevFunc, PCIINTLINE, int_line, 1); + + /* + * Enable i/o space, memory space and master on this device + */ PCI_Write_CFG_Reg(BusDevFunc, PCICMD, 7, 2); -#endif } @@ -853,4 +867,6 @@ pciBheaderPrint(PCI_HEADER_BRIDGE * pB) #endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ +#endif /* CONFIG_PCI_PNP */ + #endif /* CONFIG_PPC405GP */ diff --git a/ppc4xx/cpu.c b/ppc4xx/cpu.c index 73814c2..0db37e9 100644 --- a/ppc4xx/cpu.c +++ b/ppc4xx/cpu.c @@ -36,6 +36,8 @@ #include #include #include +#include + /* ------------------------------------------------------------------------- */ @@ -45,11 +47,53 @@ int checkcpu(long clock) uint pvr = get_pvr(); #ifdef CONFIG_PPC405GP - printf("IBM PPC405GP (PVR=%08x)", pvr); - printf(" at %lu MHz:", clock); - printf(" %u kB I-Cache", 16); - printf(" %u kB D-Cache", 8); + PPC405_SYS_INFO sys_info; + + get_sys_info(&sys_info); + + printf("IBM PowerPC 405GP Rev. "); + switch (pvr) + { + case PVR_405GP_RB: + putc('B'); + break; + case PVR_405GP_RC: + putc('C'); + break; + case PVR_405GP_RD: + putc('D'); + break; + default: + printf("? (PVR=%08x)", pvr); + break; + } + + printf(" at %lu MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", clock, + sys_info.freqPLB / 1000000, + sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, + sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); + + if (mfdcr(strap) & PSR_PCI_ASYNC_EN) + printf(" PCI async ext clock used, "); + else + printf(" PCI sync clock at %lu MHz, ", + sys_info.freqPLB / sys_info.pllPciDiv / 1000000); + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + printf("internal PCI arbiter enabled\n"); + else + printf("external PCI arbiter enabled\n"); + + switch (pvr) + { + case PVR_405GP_RB: + case PVR_405GP_RC: + case PVR_405GP_RD: + printf(" 16 kB I-Cache 8 kB D-Cache"); + break; + } + #endif + #ifdef CONFIG_IOP480 printf("PLX IOP480 (PVR=%08x)", pvr); printf(" at %lu MHz:", clock); diff --git a/ppc4xx/speed.c b/ppc4xx/speed.c index c9e8376..063726a 100644 --- a/ppc4xx/speed.c +++ b/ppc4xx/speed.c @@ -23,11 +23,15 @@ #include #include +#include #include #include "speed.h" /* ------------------------------------------------------------------------- */ +#define ONE_BILLION 1000000000 + + #ifdef CONFIG_CPCI405 #if 0 @@ -164,18 +168,184 @@ static void fpga_boot(void) #endif +void get_sys_info (PPC405_SYS_INFO *sysInfo) +{ + unsigned long pllmr; + unsigned long sysClkPeriodNs = ONE_BILLION / CONFIG_SYS_CLK_FREQ; + + /* + * Read PLL Mode register + */ + pllmr = mfdcr(pllmd); + + /* + * Determine FWD_DIV. + */ + switch (pllmr & PLLMR_FWD_DIV_MASK) + { + case PLLMR_FWD_DIV_BYPASS: + sysInfo->pllFwdDiv = 1; + break; + case PLLMR_FWD_DIV_3: + sysInfo->pllFwdDiv = 3; + break; + case PLLMR_FWD_DIV_4: + sysInfo->pllFwdDiv = 4; + break; + case PLLMR_FWD_DIV_6: + sysInfo->pllFwdDiv = 6; + break; + default: + printf("\nInvalid FWDDIV bits in PLL Mode reg: %8.8lx\a\n", pllmr); + hang(); + } + + /* + * Determine FBK_DIV. + */ + switch (pllmr & PLLMR_FB_DIV_MASK) + { + case PLLMR_FB_DIV_1: + sysInfo->pllFbkDiv = 1; + break; + case PLLMR_FB_DIV_2: + sysInfo->pllFbkDiv = 2; + break; + case PLLMR_FB_DIV_3: + sysInfo->pllFbkDiv = 3; + break; + case PLLMR_FB_DIV_4: + sysInfo->pllFbkDiv = 4; + break; + } + + /* + * Determine PLB_DIV. + */ + switch (pllmr & PLLMR_CPU_TO_PLB_MASK) + { + case PLLMR_CPU_PLB_DIV_1: + sysInfo->pllPlbDiv = 1; + break; + case PLLMR_CPU_PLB_DIV_2: + sysInfo->pllPlbDiv = 2; + break; + case PLLMR_CPU_PLB_DIV_3: + sysInfo->pllPlbDiv = 3; + break; + case PLLMR_CPU_PLB_DIV_4: + sysInfo->pllPlbDiv = 4; + break; + } + + /* + * Determine PCI_DIV. + */ + switch (pllmr & PLLMR_PCI_TO_PLB_MASK) + { + case PLLMR_PCI_PLB_DIV_1: + sysInfo->pllPciDiv = 1; + break; + case PLLMR_PCI_PLB_DIV_2: + sysInfo->pllPciDiv = 2; + break; + case PLLMR_PCI_PLB_DIV_3: + sysInfo->pllPciDiv = 3; + break; + case PLLMR_PCI_PLB_DIV_4: + sysInfo->pllPciDiv = 4; + break; + } + + /* + * Determine EXTBUS_DIV. + */ + switch (pllmr & PLLMR_EXB_TO_PLB_MASK) + { + case PLLMR_EXB_PLB_DIV_2: + sysInfo->pllExtBusDiv = 2; + break; + case PLLMR_EXB_PLB_DIV_3: + sysInfo->pllExtBusDiv = 3; + break; + case PLLMR_EXB_PLB_DIV_4: + sysInfo->pllExtBusDiv = 4; + break; + case PLLMR_EXB_PLB_DIV_5: + sysInfo->pllExtBusDiv = 5; + break; + } + + /* + * Determine OPB_DIV. + */ + switch (pllmr & PLLMR_OPB_TO_PLB_MASK) + { + case PLLMR_OPB_PLB_DIV_1: + sysInfo->pllOpbDiv = 1; + break; + case PLLMR_OPB_PLB_DIV_2: + sysInfo->pllOpbDiv = 2; + break; + case PLLMR_OPB_PLB_DIV_3: + sysInfo->pllOpbDiv = 3; + break; + case PLLMR_OPB_PLB_DIV_4: + sysInfo->pllOpbDiv = 4; + break; + } + + /* + * Check pllFwdDiv to see if running in bypass mode where the CPU speed + * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO + * to make sure it is within the proper range. + * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV + * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. + */ + if (sysInfo->pllFwdDiv == 1) + { + sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ; + sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ/sysInfo->pllPlbDiv; + } + else + { + sysInfo->freqVCOMhz = (1000 * sysInfo->pllFwdDiv * sysInfo->pllFbkDiv * + sysInfo->pllPlbDiv) / sysClkPeriodNs; + if (sysInfo->freqVCOMhz >= VCO_MIN && sysInfo->freqVCOMhz <= VCO_MAX) + { + sysInfo->freqPLB = (ONE_BILLION / + ((sysClkPeriodNs * 10) / sysInfo->pllFbkDiv)) * 10; + sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; + } + else + { + printf("\nInvalid VCO frequency calculated : %ld MHz \a\n", + sysInfo->freqVCOMhz); + printf("It must be between %d-%d MHz \a\n", VCO_MIN, VCO_MAX); + printf("PLL Mode reg : %8.8lx\a\n", pllmr); + hang(); + } + } +} + + ulong get_gclk_freq (void) { ulong val; - #ifdef CONFIG_PPC405GP + PPC405_SYS_INFO sys_info; + + get_sys_info(&sys_info); + val = sys_info.freqProcessor; + +#ifdef CONFIG_CPCI405 /* * Boot onboard FPGA */ fpga_boot(); +#endif /* CONFIG_CPCI405 */ +#endif /* CONFIG_PPC405GP */ - val = 200000000; -#endif #ifdef CONFIG_IOP480 val = 66000000; #endif @@ -188,12 +358,15 @@ ulong get_gclk_freq (void) ulong get_bus_freq (ulong gclk_freq) { ulong val; - #ifdef CONFIG_PPC405GP - val = 100000000; -#endif + PPC405_SYS_INFO sys_info; + + get_sys_info(&sys_info); + val = sys_info.freqPLB / 1000000; +#endif /* CONFIG_PPC405GP */ + #ifdef CONFIG_IOP480 - val = 66000000; + val = 66; #endif return val;