From: wdenk Date: Mon, 10 Sep 2001 23:03:24 +0000 (+0000) Subject: * Add I2C and SPI microcode relocation patches (MPC8xx) X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=c86344adb62efe3905c80017ed224977a40e81bf;p=users%2Frw%2Fppcboot.git * Add I2C and SPI microcode relocation patches (MPC8xx) Based on a patch by Joakim Tjernlund, 23 Aug 2001 * Added -meabi to compiler flags; make sure we have a valid initial stack frame so any back traces will terminate properly * Modified default configuration for sbc8260 Patch by Jon Diekema, 4 Sep 2001 * Changed default behavious in case of crashes: automatically reboot on panic now (see description of CONFIG_PANIC_HANG in the README file) --- diff --git a/CHANGELOG b/CHANGELOG index 6a86d27..a4a18f5 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,10 +56,23 @@ To do: Modifications for 1.0.5: ====================================================================== +* Add I2C and SPI microcode relocation patches (MPC8xx) + Based on a patch by Joakim Tjernlund, 23 Aug 2001 + +* Added -meabi to compiler flags; make sure we have a valid initial + stack frame so any back traces will terminate properly + +* Modified default configuration for sbc8260 + Patch by Jon Diekema, 4 Sep 2001 + +* Changed default behavious in case of crashes: automatically reboot + on panic now (see description of CONFIG_PANIC_HANG in the README + file) + * Added port to MOUSSE board Patch by James F Dougherty, 10 Sep 2001 -* Add etags Make target +* Add etags make target Patch by James F Dougherty, 10 Sep 2001 * PPCBoot stores all clock information in Hz internally. diff --git a/README b/README index 3253607..76f09e8 100644 --- a/README +++ b/README @@ -605,6 +605,16 @@ The following options need to be configured: HERMES, IP860, RPXlite, LWMON, LANTEC, PCU_E, FLAGADM, TQM8260 +- Error Recovery: + CONFIG_PANIC_HANG + + Define this variable to stop the system in case of a + fatal error, so that you have to reset it manually. + This is probably NOT a good idea for an embedded + system where you want to system to reboot + automatically as fast as possible, but it may be + useful during development since you can try to debug + the conditions that lead to the situation. Configuration Settings: ----------------------- @@ -862,6 +872,14 @@ Low Level (hardware related) configuration options: Machine Mode Register and Memory Periodic Timer Prescaler definitions (SDRAM timing) +- CFG_I2C_UCODE_PATCH, CFG_I2C_DPMEM_OFFSET [0x1FC0]: + enable I2C microcode relocation patch (MPC8xx); + define relocation offset in DPRAM [DSP2] + +- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]: + enable SPI microcode relocation patch (MPC8xx); + define relocation offset in DPRAM [SCC4] + Building the Software: ====================== diff --git a/cpu/mpc74xx/config.mk b/cpu/mpc74xx/config.mk index fec35ef..e67ca44 100644 --- a/cpu/mpc74xx/config.mk +++ b/cpu/mpc74xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 +PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_74xx -ffixed-r2 -mstring diff --git a/cpu/mpc74xx/start.S b/cpu/mpc74xx/start.S index c267bff..1e61ff2 100644 --- a/cpu/mpc74xx/start.S +++ b/cpu/mpc74xx/start.S @@ -289,6 +289,9 @@ in_flash: /* set up r1 (SP) */ addis r1,r0,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ GET_GOT /* initialize GOT access */ diff --git a/cpu/mpc8240/config.mk b/cpu/mpc8240/config.mk index 00f3988..a4b18cd 100644 --- a/cpu/mpc8240/config.mk +++ b/cpu/mpc8240/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 +PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC8240 -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc8240/start.S b/cpu/mpc8240/start.S index 672659c..7b40bc2 100644 --- a/cpu/mpc8240/start.S +++ b/cpu/mpc8240/start.S @@ -142,11 +142,15 @@ boot_warm: in_flash: - /* thisk the stack pointer *somewhere* sensible. doesnt matter much where as we'll - move it when we relocate*/ - - lis r1, (CFG_MEMTEST_END - 0x3000)@h - ori r1, r1, (CFG_MEMTEST_END - 0x3000)@l + /* + * Thisk the stack pointer *somewhere* sensible. Doesnt + * matter much where as we'll move it when we relocate + */ + lis r1, (CFG_MEMTEST_END - 0x3000)@h + ori r1, r1, (CFG_MEMTEST_END - 0x3000)@l + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ /* let the C-code set up the rest */ diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 033104d..e68fdce 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 +PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_8260 -ffixed-r2 -mstring # -mcpu=8260 diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 39ff4aa..f5440bf 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -221,7 +221,9 @@ in_flash: lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */ ori r1, r3, CFG_INIT_SP_OFFSET - stwu r1, -8(r1) /* make room for stack frame header */ + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ /* let the C-code set up the rest */ /* */ diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile index 8131354..763c40d 100644 --- a/cpu/mpc8xx/Makefile +++ b/cpu/mpc8xx/Makefile @@ -30,7 +30,8 @@ LIB = lib$(CPU).a START = start.o kgdb.o OBJS = traps.o serial.o cpu.o cpu_init.o speed.o \ commproc.o interrupts.o fec.o scc.o spi.o \ - i2c.o soft_i2c.o video.o wlkbd.o status_led.o bedbug_860.o + i2c.o soft_i2c.o video.o wlkbd.o status_led.o \ + bedbug_860.o upatch.o all: .depend $(START) $(LIB) diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index 1b5ff9a..7db2680 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 +PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 95c56b1..839cf27 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -26,6 +26,10 @@ #include #include +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) + void cpm_load_patch(volatile immap_t *immr); +#endif + /* * Breath some life into the CPU... * @@ -109,6 +113,25 @@ cpu_init_f (volatile immap_t *immr) /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at * preliminary addresses - these have to be modified later * when FLASH size has been determined + * + * Depending on the size of the memory region defined by + * CFG_OR0_REMAP some boards (wide address mask) allow to map the + * CFG_MONITOR_BASE, while others (narrower address mask) can't + * map CFG_MONITOR_BASE. + * + * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is + * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000. + * + * If BR0 wasn't loaded with address base 0xff000000, then BR0's + * base address remains as 0x00000000. However, the address mask + * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped + * into the Bank0. + * + * This is why CONFIG_IVMS8 and similar boards must load BR0 with + * CFG_BR0_PRELIM in advance. + * + * [Thanks to Michael Liao for this explanation. + * I owe him a free beer. - wd] */ #if defined(CONFIG_GTH) || \ @@ -123,11 +146,7 @@ cpu_init_f (volatile immap_t *immr) defined(CONFIG_SPD823TS) || \ defined(CONFIG_SXNI855T) || \ (defined(CONFIG_MPC860T) && defined(CONFIG_FADS)) - /* XXX - FIXME - XXX - * I still don't understand why some systems work only with this - * statement here, and others work only without it. - * I offer a free beer to anyone who can explain that to me - wd - */ + memctl->memc_br0 = CFG_BR0_PRELIM; /* XXX ??? XXX ??? XXX */ #endif @@ -186,7 +205,6 @@ cpu_init_f (volatile immap_t *immr) #endif /* ! CONFIG_MBX */ - /* * Reset CPM */ @@ -205,8 +223,8 @@ cpu_init_f (volatile immap_t *immr) mbx_init(); #endif /* CONFIG_MBX */ -#if defined(CONFIG_I2C) && defined(CFG_ALLOC_DPRAM) - iip->iic_rbase = 0; +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) + cpm_load_patch(immr); /* load mpc8xx microcode patch */ #endif } diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index 3116ef2..53d81b7 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -121,47 +121,48 @@ i2c_roundrate(int hz, int speed, int filter, int modval, * Sets the I2C clock predivider and divider to meet required clock speed. */ static int -i2c_setrate(int hz, int speed) +i2c_setrate (int hz, int speed) { - immap_t *immap = (immap_t *)CFG_IMMR ; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval=0, - bestspeed_modval=0, - bestspeed_filter=0, - totspeed, - filter = 0; /* Use this fixed value */ - - for (modval = 0; modval < 4; modval++) - { - if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0) - { - int diff = speed - totspeed ; - - if ((diff >= 0) && (diff < bestspeed_diff)) - { - bestspeed_diff = diff ; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; + immap_t *immap = (immap_t *) CFG_IMMR; + volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c; + int brgval, + modval, /* 0-3 */ + bestspeed_diff = speed, + bestspeed_brgval = 0, + bestspeed_modval = 0, + bestspeed_filter = 0, + totspeed, + filter = 0; /* Use this fixed value */ + + for (modval = 0; modval < 4; modval++) { + if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) { + int diff = speed - totspeed; + + if ((diff >= 0) && (diff < bestspeed_diff)) { + bestspeed_diff = diff; + bestspeed_modval = modval; + bestspeed_brgval = brgval; + bestspeed_filter = filter; } } } - PRINTD(("[I2C] Best is:\n")); - PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", - hz, speed, - bestspeed_filter, bestspeed_modval, bestspeed_brgval, - bestspeed_diff)); + PRINTD (("[I2C] Best is:\n")); + PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", + hz, + speed, + bestspeed_filter, + bestspeed_modval, + bestspeed_brgval, + bestspeed_diff)); - i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); - i2c->i2c_i2brg = bestspeed_brgval & 0xff; + i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); + i2c->i2c_i2brg = bestspeed_brgval & 0xff; - PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg)); + PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, + i2c->i2c_i2brg)); - return 1 ; + return 1; } void @@ -170,12 +171,20 @@ i2c_init(int speed, int slaveaddr) init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET); volatile immap_t *immap = (immap_t *)CFG_IMMR ; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; + volatile iic_t *iip; ulong rbase, tbase; volatile I2C_BD *rxbd, *txbd; uint dpaddr; +#ifdef CFG_I2C_UCODE_PATCH + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#else + iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + /* Disable relocation */ + iip->iic_rpbase = 0; +#endif + #ifdef CFG_ALLOC_DPRAM dpaddr = iip->iic_rbase; if (dpaddr == 0) { @@ -199,9 +208,6 @@ i2c_init(int speed, int slaveaddr) rbase = dpaddr; tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); - /* Disable relocation */ - iip->iic_rpbase = 0 ; - /* Initialize Port B I2C pins. */ cp->cp_pbpar |= 0x00000030; cp->cp_pbdir |= 0x00000030; @@ -245,10 +251,20 @@ i2c_init(int speed, int slaveaddr) /* Set maximum receive size. */ iip->iic_mrblr = I2C_RXTX_LEN; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { +#ifdef CFG_I2C_UCODE_PATCH + /* + * Initialize required parameters if using microcode patch. + */ + iip->iic_rbptr = iip->iic_rbase; + iip->iic_tbptr = iip->iic_tbase; + iip->iic_rstate = 0; + iip->iic_tstate = 0; +#else + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); + } while (cp->cp_cpcr & CPM_CR_FLG); +#endif /* Clear events and interrupts */ i2c->i2c_i2cer = 0xff; @@ -260,10 +276,15 @@ i2c_newio(i2c_state_t *state) { volatile immap_t *immap = (immap_t *)CFG_IMMR ; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + volatile iic_t *iip; PRINTD(("[I2C] i2c_newio\n")); +#ifdef CFG_I2C_UCODE_PATCH + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#else + iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; +#endif state->rx_idx = 0; state->tx_idx = 0; state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase]; @@ -281,11 +302,11 @@ i2c_newio(i2c_state_t *state) int i2c_send(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size, - unsigned char *dataout) + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size, + unsigned char *dataout) { volatile I2C_BD *txbd; int i,j; @@ -306,28 +327,22 @@ i2c_send(i2c_state_t *state, PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - if (flags & I2CF_START_COND) - { - PRINTD(("[I2C] Formatting addresses...\n")); - if (flags & I2CF_ENABLE_SECONDARY) - { - txbd->length = size + 2; /* Length of message plus dest addresses */ - txbd->addr[0] = address << 1; - txbd->addr[1] = secondary_address; - i = 2; - } - else - { - txbd->length = size + 1; /* Length of message plus dest address */ - txbd->addr[0] = address << 1; /* Write destination address to BD */ - i = 1; + if (flags & I2CF_START_COND) { + PRINTD(("[I2C] Formatting addresses...\n")); + if (flags & I2CF_ENABLE_SECONDARY) { + txbd->length = size + 2; /* Length of msg + dest addr */ + txbd->addr[0] = address << 1; + txbd->addr[1] = secondary_address; + i = 2; + } else { + txbd->length = size + 1; /* Length of msg + dest addr */ + txbd->addr[0] = address << 1; /* Write dest addr to BD */ + i = 1; + } + } else { + txbd->length = size; /* Length of message */ + i = 0; } - } - else - { - txbd->length = size; /* Length of message */ - i = 0; - } /* set up txbd */ txbd->status = BD_SC_READY; @@ -357,11 +372,11 @@ i2c_send(i2c_state_t *state, } int i2c_receive(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size_to_expect, - unsigned char *datain) + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size_to_expect, + unsigned char *datain) { volatile I2C_BD *rxbd, *txbd; @@ -385,15 +400,12 @@ int i2c_receive(i2c_state_t *state, txbd->addr = state->tx_buf; /* set up TXBD for destination address */ - if (flags & I2CF_ENABLE_SECONDARY) - { + if (flags & I2CF_ENABLE_SECONDARY) { txbd->length = 2; txbd->addr[0] = address << 1; /* Write data */ txbd->addr[1] = secondary_address; /* Internal address */ txbd->status = BD_SC_READY; - } - else - { + } else { txbd->length = 1 + size_to_expect; txbd->addr[0] = (address << 1) | 0x01; txbd->status = BD_SC_READY; @@ -406,8 +418,7 @@ int i2c_receive(i2c_state_t *state, rxbd->addr = datain; txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - { + if (flags & I2CF_STOP_COND) { txbd->status |= BD_SC_LAST | BD_SC_WRAP; rxbd->status |= BD_SC_WRAP; } @@ -439,13 +450,19 @@ int i2c_doio(i2c_state_t *state) { volatile immap_t *immap = (immap_t *)CFG_IMMR ; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; + volatile iic_t *iip; volatile I2C_BD *txbd, *rxbd; volatile int j = 0; PRINTD(("[I2C] i2c_doio\n")); +#ifdef CFG_I2C_UCODE_PATCH + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#else + iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; +#endif + if (state->tx_idx <= 0 && state->rx_idx <= 0) { PRINTD(("[I2C] No I/O is queued\n")); return I2CERR_QUEUE_EMPTY; diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c index 6f91b17..d04a892 100644 --- a/cpu/mpc8xx/spi.c +++ b/cpu/mpc8xx/spi.c @@ -147,7 +147,13 @@ void spi_init_f (void) iop = (iop8xx_t *) &immr->im_ioport; cp = (cpm8xx_t *) &immr->im_cpm; +#ifdef CFG_SPI_UCODE_PATCH + spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; +#else spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; +#endif /* 1 */ /* ------------------------------------------------ @@ -226,12 +232,20 @@ void spi_init_f (void) spi->spi_tbptr = spi->spi_tbase; /* 4 */ +#ifdef CFG_SPI_UCODE_PATCH + /* + * Initialize required parameters if using microcode patch. + */ + spi->spi_rstate = 0; + spi->spi_tstate = 0; +#else /* Init SPI Tx + Rx Parameters */ while (cp->cp_cpcr & CPM_CR_FLG) ; cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cp_cpcr & CPM_CR_FLG) ; +#endif /* CFG_SPI_UCODE_PATCH */ /* 5 */ /* Set SDMA configuration register */ @@ -285,7 +299,14 @@ void spi_init_r (void) immr = (immap_t *) CFG_IMMR; cp = (cpm8xx_t *) &immr->im_cpm; + +#ifdef CFG_SPI_UCODE_PATCH + spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; +#else spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; +#endif /* tx and rx buffer descriptors */ tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; @@ -371,7 +392,13 @@ ssize_t spi_xfer (size_t count) immr = (immap_t *) CFG_IMMR; cp = (cpm8xx_t *) &immr->im_cpm; +#ifdef CFG_SPI_UCODE_PATCH + spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; +#else spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; +#endif tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index d65b5f0..a899a93 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -174,6 +174,9 @@ in_flash: lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */ ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ + /* Note: R0 is still 0 here */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ /* * Disable serialized ifetch and show cycles diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index 5f13666..b17978d 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 +PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -mcpu=403 -msoft-float diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0e2e8a2..a325724 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -13,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -23,23 +23,23 @@ */ //------------------------------------------------------------------------------+ // -// This source code has been made available to you by IBM on an AS-IS -// basis. Anyone receiving this source is licensed under IBM -// copyrights to use it in any way he or she deems fit, including -// copying it, modifying it, compiling it, and redistributing it either -// with or without modifications. No license under IBM patents or -// patent applications is to be implied by the copyright license. +// This source code has been made available to you by IBM on an AS-IS +// basis. Anyone receiving this source is licensed under IBM +// copyrights to use it in any way he or she deems fit, including +// copying it, modifying it, compiling it, and redistributing it either +// with or without modifications. No license under IBM patents or +// patent applications is to be implied by the copyright license. // -// Any user of this software should understand that IBM cannot provide -// technical support for this software and will not be responsible for -// any consequences resulting from the use of this software. +// Any user of this software should understand that IBM cannot provide +// technical support for this software and will not be responsible for +// any consequences resulting from the use of this software. // -// Any person who transfers this source code or any derivative work -// must include the IBM copyright notice, this paragraph, and the -// preceding two paragraphs in the transferred software. +// Any person who transfers this source code or any derivative work +// must include the IBM copyright notice, this paragraph, and the +// preceding two paragraphs in the transferred software. // -// COPYRIGHT I B M CORPORATION 1995 -// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +// COPYRIGHT I B M CORPORATION 1995 +// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M //------------------------------------------------------------------------------- /* ppcboot - Startup Code for IBM 4xx PowerPC based Embedded Boards @@ -70,8 +70,8 @@ #include #include -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" #endif /* We don't want the MMU yet. @@ -80,8 +80,8 @@ #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ - .extern ext_bus_cntlr_init - .extern sdram_init + .extern ext_bus_cntlr_init + .extern sdram_init /* * Set up GOT: Global Offset Table @@ -131,173 +131,177 @@ boot_warm: /*****************************************************************************/ #ifdef CONFIG_IOP480 - //----------------------------------------------------------------------- - // Set up some machine state registers. - //----------------------------------------------------------------------- - addi r4,r0,0x0000 // initialize r4 to zero - mtspr esr,r4 // clear Exception Syndrome Reg - mttcr r4 // timer control register - addis r4,r0,0x0000 - mtexier r4 // disable all interrupts - addi r4,r0,0x1000 // set ME bit (Machine Exceptions) - oris r4,r4,0x2 // set CE bit (Critical Exceptions) - mtmsr r4 // change MSR - addis r4,r0,0xFFFF // set r4 to 0xFFFFFFFF (status in the - ori r4,r4,0xFFFF // dbsr is cleared by setting bits to 1) - mtdbsr r4 // clear/reset the dbsr - mtexisr r4 // clear all pending interrupts - addis r4,r0,0x8000 - mtexier r4 // enable critical exceptions - addis r4,r0,0x0000 // assume 403GCX - enable core clk - ori r4,r4,0x4020 // dbling (no harm done on GA and GC - mtiocr r4 // since bit not used) & DRC to latch - // data bus on rising edge of CAS - //----------------------------------------------------------------------- - // Clear XER. - //----------------------------------------------------------------------- - addis r0,r0,0x0000 - mtxer r0 - //----------------------------------------------------------------------- - // Invalidate i-cache and d-cache TAG arrays. - //----------------------------------------------------------------------- - addi r3,0,1024 // 1/4 of I-cache size, half of D-cache - addi r4,0,1024 // 1/4 of I-cache + //----------------------------------------------------------------------- + // Set up some machine state registers. + //----------------------------------------------------------------------- + addi r0,r0,0x0000 // initialize r0 to zero + mtspr esr,r0 // clear Exception Syndrome Reg + mttcr r0 // timer control register + mtexier r0 // disable all interrupts + addi r4,r0,0x1000 // set ME bit (Machine Exceptions) + oris r4,r4,0x2 // set CE bit (Critical Exceptions) + mtmsr r4 // change MSR + addis r4,r0,0xFFFF // set r4 to 0xFFFFFFFF (status in the + ori r4,r4,0xFFFF // dbsr is cleared by setting bits to 1) + mtdbsr r4 // clear/reset the dbsr + mtexisr r4 // clear all pending interrupts + addis r4,r0,0x8000 + mtexier r4 // enable critical exceptions + addis r4,r0,0x0000 // assume 403GCX - enable core clk + ori r4,r4,0x4020 // dbling (no harm done on GA and GC + mtiocr r4 // since bit not used) & DRC to latch + // data bus on rising edge of CAS + //----------------------------------------------------------------------- + // Clear XER. + //----------------------------------------------------------------------- + mtxer r0 + //----------------------------------------------------------------------- + // Invalidate i-cache and d-cache TAG arrays. + //----------------------------------------------------------------------- + addi r3,0,1024 // 1/4 of I-cache size, half of D-cache + addi r4,0,1024 // 1/4 of I-cache ..cloop: - iccci 0,r3 - iccci r4,r3 - dccci 0,r3 - addic. r3,r3,-16 // move back one cache line - bne ..cloop // loop back to do rest until r3 = 0 + iccci 0,r3 + iccci r4,r3 + dccci 0,r3 + addic. r3,r3,-16 // move back one cache line + bne ..cloop // loop back to do rest until r3 = 0 - // - // initialize IOP480 so it can read 1 MB code area for SRAM spaces - // this requires enabling MA[17..0], by default only MA[12..0] are enabled. - // + // + // initialize IOP480 so it can read 1 MB code area for SRAM spaces + // this requires enabling MA[17..0], by default only MA[12..0] are enabled. + // - // first copy IOP480 register base address into r3 - addis r3,0,0x5000 // IOP480 register base address hi - ori r3,r3,0x0000 // IOP480 register base address lo + // first copy IOP480 register base address into r3 + addis r3,0,0x5000 // IOP480 register base address hi +// ori r3,r3,0x0000 // IOP480 register base address lo #ifdef CONFIG_ADCIOP - // use r4 as the working variable - // turn on CS3 (LOCCTL.7) - lwz r4,0x84(r3) // LOCTL is at offset 0x84 - andi. r4,r4,0xff7f // make bit 7 = 0 -- CS3 mode - stw r4,0x84(r3) // LOCTL is at offset 0x84 + // use r4 as the working variable + // turn on CS3 (LOCCTL.7) + lwz r4,0x84(r3) // LOCTL is at offset 0x84 + andi. r4,r4,0xff7f // make bit 7 = 0 -- CS3 mode + stw r4,0x84(r3) // LOCTL is at offset 0x84 #endif - + #ifdef CONFIG_DASA_SIM - // use r4 as the working variable - // turn on MA17 (LOCCTL.7) - lwz r4,0x84(r3) // LOCTL is at offset 0x84 - ori r4,r4,0x80 // make bit 7 = 1 -- MA17 mode - stw r4,0x84(r3) // LOCTL is at offset 0x84 + // use r4 as the working variable + // turn on MA17 (LOCCTL.7) + lwz r4,0x84(r3) // LOCTL is at offset 0x84 + ori r4,r4,0x80 // make bit 7 = 1 -- MA17 mode + stw r4,0x84(r3) // LOCTL is at offset 0x84 #endif - - // turn on MA16..13 (LCS0BRD.12 = 0) - lwz r4,0x100(r3) // LCS0BRD is at offset 0x100 - andi. r4,r4,0xefff // make bit 12 = 0 - stw r4,0x100(r3) // LCS0BRD is at offset 0x100 - - // make sure above stores all comlete before going on - sync - - // last thing, set local init status done bit (DEVINIT.31) - lwz r4,0x80(r3) // DEVINIT is at offset 0x80 - oris r4,r4,0x8000 // make bit 31 = 1 - stw r4,0x80(r3) // DEVINIT is at offset 0x80 - - // clear all pending interrupts and disable all interrupts - li r4,-1 // set p1 to 0xffffffff - stw r4,0x1b0(r3) // clear all pending interrupts - stw r4,0x1b8(r3) // clear all pending interrupts - li r4,0 // set r4 to 0 - stw r4,0x1b4(r3) // disable all interrupts - stw r4,0x1bc(r3) // disable all interrupts - - // make sure above stores all comlete before going on - sync - - //----------------------------------------------------------------------- - // Enable two 128MB cachable regions. - //----------------------------------------------------------------------- - addis r1,r0,0x8000 - addi r1,r1,0x0001 - mticcr r1 // instruction cache - - addis r1,r0,0x0000 - addi r1,r1,0x0000 - mtdccr r1 // data cache - - addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + + // turn on MA16..13 (LCS0BRD.12 = 0) + lwz r4,0x100(r3) // LCS0BRD is at offset 0x100 + andi. r4,r4,0xefff // make bit 12 = 0 + stw r4,0x100(r3) // LCS0BRD is at offset 0x100 + + // make sure above stores all comlete before going on + sync + + // last thing, set local init status done bit (DEVINIT.31) + lwz r4,0x80(r3) // DEVINIT is at offset 0x80 + oris r4,r4,0x8000 // make bit 31 = 1 + stw r4,0x80(r3) // DEVINIT is at offset 0x80 + + // clear all pending interrupts and disable all interrupts + li r4,-1 // set p1 to 0xffffffff + stw r4,0x1b0(r3) // clear all pending interrupts + stw r4,0x1b8(r3) // clear all pending interrupts + li r4,0 // set r4 to 0 + stw r4,0x1b4(r3) // disable all interrupts + stw r4,0x1bc(r3) // disable all interrupts + + // make sure above stores all comlete before going on + sync + + //----------------------------------------------------------------------- + // Enable two 128MB cachable regions. + //----------------------------------------------------------------------- + addis r1,r0,0x8000 + addi r1,r1,0x0001 + mticcr r1 // instruction cache + + addis r1,r0,0x0000 + addi r1,r1,0x0000 + mtdccr r1 // data cache + + addis r1,r0,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ GET_GOT /* initialize GOT access */ bl board_init_f /* run first part of init code (from Flash) */ -#endif /* CONFIG_IOP480 */ +#endif /* CONFIG_IOP480 */ /*****************************************************************************/ #ifdef CONFIG_PPC405 - //----------------------------------------------------------------------- - // Clear and set up some registers. - //----------------------------------------------------------------------- - addi r4,r0,0x0000 - mtspr sgr,r4 - mtspr dcwr,r4 - mtesr r4 // clear Exception Syndrome Reg - mttcr r4 // clear Timer Control Reg - mtxer r4 // clear Fixed-Point Exception Reg - mtevpr r4 // clear Exception Vector Prefix Reg - addi r4,r0,0x1000 // set ME bit (Machine Exceptions) - oris r4,r4,0x0002 // set CE bit (Critical Exceptions) - mtmsr r4 // change MSR - addi r4,r0,(0xFFFF-0x10000) // set r4 to 0xFFFFFFFF (status in the - // dbsr is cleared by setting bits to 1) - mtdbsr r4 // clear/reset the dbsr - - //----------------------------------------------------------------------- - // Invalidate I and D caches. Enable I cache for defined memory regions + //----------------------------------------------------------------------- + // Clear and set up some registers. + //----------------------------------------------------------------------- + addi r4,r0,0x0000 + mtspr sgr,r4 + mtspr dcwr,r4 + mtesr r4 // clear Exception Syndrome Reg + mttcr r4 // clear Timer Control Reg + mtxer r4 // clear Fixed-Point Exception Reg + mtevpr r4 // clear Exception Vector Prefix Reg + addi r4,r0,0x1000 // set ME bit (Machine Exceptions) + oris r4,r4,0x0002 // set CE bit (Critical Exceptions) + mtmsr r4 // change MSR + addi r4,r0,(0xFFFF-0x10000) // set r4 to 0xFFFFFFFF (status in the + // dbsr is cleared by setting bits to 1) + mtdbsr r4 // clear/reset the dbsr + + //----------------------------------------------------------------------- + // Invalidate I and D caches. Enable I cache for defined memory regions // to speed things up. Leave the D cache disabled for now. It will be // enabled/left disabled later based on user selected menu options. // Be aware that the I cache may be disabled later based on the menu - // options as well. See miscLib/main.c. - //----------------------------------------------------------------------- - bl invalidate_icache - bl invalidate_dcache - - //----------------------------------------------------------------------- - // Enable two 128MB cachable regions. - //----------------------------------------------------------------------- - addis r4,r0,0x8000 - addi r4,r4,0x0001 - mticcr r4 // instruction cache - isync - - addis r4,r0,0x0000 - addi r4,r4,0x0000 - mtdccr r4 // data cache - - //----------------------------------------------------------------------- - // Initialize the External Bus Controller for external peripherals - //----------------------------------------------------------------------- - bl ext_bus_cntlr_init - - //----------------------------------------------------------------------- - // Initialize SDRAM Controller - //----------------------------------------------------------------------- - bl sdram_init - - addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ - - GET_GOT /* initialize GOT access */ + // options as well. See miscLib/main.c. + //----------------------------------------------------------------------- + bl invalidate_icache + bl invalidate_dcache + + //----------------------------------------------------------------------- + // Enable two 128MB cachable regions. + //----------------------------------------------------------------------- + addis r4,r0,0x8000 + addi r4,r4,0x0001 + mticcr r4 // instruction cache + isync + + addis r4,r0,0x0000 + addi r4,r4,0x0000 + mtdccr r4 // data cache + + //----------------------------------------------------------------------- + // Initialize the External Bus Controller for external peripherals + //----------------------------------------------------------------------- + bl ext_bus_cntlr_init + + //----------------------------------------------------------------------- + // Initialize SDRAM Controller + //----------------------------------------------------------------------- + bl sdram_init + + addis r1,r0,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + GET_GOT /* initialize GOT access */ bl board_init_f /* run first part of init code (from Flash) */ -#endif /* CONFIG_PPC405 */ +#endif /* CONFIG_PPC405 */ .globl _start_of_vectors @@ -387,7 +391,7 @@ ProgramCheck: STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) + CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) .globl _end_of_vectors _end_of_vectors: @@ -471,124 +475,124 @@ int_return: rfi crit_return: - mfmsr r29 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r29,r29,r4 - SYNC /* Some chip revs need this... */ - mtmsr r29 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr 990,r2 /* SRR2 */ - mtspr 991,r0 /* SRR3 */ - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfci + mfmsr r29 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r29,r29,r4 + SYNC /* Some chip revs need this... */ + mtmsr r29 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr 990,r2 /* SRR2 */ + mtspr 991,r0 /* SRR3 */ + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfci /* Cache functions. */ invalidate_icache: - iccci r0,r0 // for 405, iccci invalidates the - blr // entire I cache + iccci r0,r0 // for 405, iccci invalidates the + blr // entire I cache invalidate_dcache: - addi r6,0,0x0000 // clear GPR 6 - addi r7,r0, 128 // do loop for # of dcache lines + addi r6,0,0x0000 // clear GPR 6 + addi r7,r0, 128 // do loop for # of dcache lines // NOTE: dccci invalidates both - mtctr r7 // ways in the D cache + mtctr r7 // ways in the D cache ..dcloop: - dccci 0,r6 // invalidate line - addi r6,r6, 32 // bump to next line - bdnz ..dcloop + dccci 0,r6 // invalidate line + addi r6,r6, 32 // bump to next line + bdnz ..dcloop blr flush_dcache: - addis r9,r0,0x0002 // set mask for EE and CE msr bits - ori r9,r9,0x8000 - mfmsr r12 // save msr - andc r9,r12,r9 - mtmsr r9 // disable EE and CE - addi r10,r0,0x0001 // enable data cache for unused memory - mfdccr r9 // region 0xF8000000-0xFFFFFFFF via - or r10,r10,r9 // bit 31 in dccr - mtdccr r10 - addi r10,r0,128 // do loop for # of lines - addi r11,r0,4096 // D cache set size=4K - mtctr r10 - addi r10,r0,(0xE000-0x10000) // start at 0xFFFFE000 - add r11,r10,r11 // add to get to other side of cache line + addis r9,r0,0x0002 // set mask for EE and CE msr bits + ori r9,r9,0x8000 + mfmsr r12 // save msr + andc r9,r12,r9 + mtmsr r9 // disable EE and CE + addi r10,r0,0x0001 // enable data cache for unused memory + mfdccr r9 // region 0xF8000000-0xFFFFFFFF via + or r10,r10,r9 // bit 31 in dccr + mtdccr r10 + addi r10,r0,128 // do loop for # of lines + addi r11,r0,4096 // D cache set size=4K + mtctr r10 + addi r10,r0,(0xE000-0x10000) // start at 0xFFFFE000 + add r11,r10,r11 // add to get to other side of cache line ..flush_dcache_loop: - lwz r3,0(r10) // least recently used side - lwz r3,0(r11) // the other side - dccci r0,r11 // invalidate both sides - addi r10,r10,0x0020 // bump to next line (32 bytes) - addi r11,r11,0x0020 // bump to next line (32 bytes) - bdnz ..flush_dcache_loop - sync // allow memory access to complete - mtdccr r9 // restore dccr - mtmsr r12 // restore msr - blr - - .globl icache_enable + lwz r3,0(r10) // least recently used side + lwz r3,0(r11) // the other side + dccci r0,r11 // invalidate both sides + addi r10,r10,0x0020 // bump to next line (32 bytes) + addi r11,r11,0x0020 // bump to next line (32 bytes) + bdnz ..flush_dcache_loop + sync // allow memory access to complete + mtdccr r9 // restore dccr + mtmsr r12 // restore msr + blr + + .globl icache_enable icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mticcr r3 + mflr r8 + bl invalidate_icache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mticcr r3 blr .globl icache_disable icache_disable: - addis r3,r0, 0x0000 /* clear bit 0 */ - mticcr r3 - isync + addis r3,r0, 0x0000 /* clear bit 0 */ + mticcr r3 + isync blr .globl icache_status icache_status: - mficcr r3 + mficcr r3 srwi r3, r3, 31 /* >>31 => select bit 0 */ blr .globl dcache_enable dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mtdccr r3 + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mtdccr r3 blr .globl dcache_disable dcache_disable: - mflr r8 - bl flush_dcache - mtlr r8 - addis r3,r0, 0x0000 /* clear bit 0 */ - mtdccr r3 + mflr r8 + bl flush_dcache + mtlr r8 + addis r3,r0, 0x0000 /* clear bit 0 */ + mtdccr r3 blr .globl dcache_status dcache_status: - mfdccr r3 + mfdccr r3 srwi r3, r3, 31 /* >>31 => select bit 0 */ blr @@ -608,127 +612,127 @@ wr_tcr: blr //------------------------------------------------------------------------------- -// Function: in8 -// Description: Input 8 bits +// Function: in8 +// Description: Input 8 bits //------------------------------------------------------------------------------- - .globl in8 + .globl in8 in8: - lbz r3,0x0000(r3) - blr + lbz r3,0x0000(r3) + blr //------------------------------------------------------------------------------- -// Function: out8 -// Description: Output 8 bits +// Function: out8 +// Description: Output 8 bits //------------------------------------------------------------------------------- - .globl out8 + .globl out8 out8: - stb r4,0x0000(r3) - blr + stb r4,0x0000(r3) + blr //------------------------------------------------------------------------------- -// Function: out16 -// Description: Output 16 bits +// Function: out16 +// Description: Output 16 bits //------------------------------------------------------------------------------- - .globl out16 + .globl out16 out16: - sth r4,0x0000(r3) - blr + sth r4,0x0000(r3) + blr //------------------------------------------------------------------------------- -// Function: out16r -// Description: Byte reverse and output 16 bits +// Function: out16r +// Description: Byte reverse and output 16 bits //------------------------------------------------------------------------------- - .globl out16r + .globl out16r out16r: - sthbrx r4,r0,r3 - blr + sthbrx r4,r0,r3 + blr //------------------------------------------------------------------------------- -// Function: out32 -// Description: Output 32 bits +// Function: out32 +// Description: Output 32 bits //------------------------------------------------------------------------------- - .globl out32 + .globl out32 out32: - stw r4,0x0000(r3) - blr + stw r4,0x0000(r3) + blr //------------------------------------------------------------------------------- -// Function: out32r -// Description: Byte reverse and output 32 bits +// Function: out32r +// Description: Byte reverse and output 32 bits //------------------------------------------------------------------------------- - .globl out32r + .globl out32r out32r: - stwbrx r4,r0,r3 - blr + stwbrx r4,r0,r3 + blr //------------------------------------------------------------------------------- -// Function: in16 -// Description: Input 16 bits +// Function: in16 +// Description: Input 16 bits //------------------------------------------------------------------------------- - .globl in16 + .globl in16 in16: - lhz r3,0x0000(r3) - blr + lhz r3,0x0000(r3) + blr //------------------------------------------------------------------------------- -// Function: in16r -// Description: Input 16 bits and byte reverse +// Function: in16r +// Description: Input 16 bits and byte reverse //------------------------------------------------------------------------------- - .globl in16r + .globl in16r in16r: - lhbrx r3,r0,r3 - blr + lhbrx r3,r0,r3 + blr //------------------------------------------------------------------------------- -// Function: in32 -// Description: Input 32 bits +// Function: in32 +// Description: Input 32 bits //------------------------------------------------------------------------------- - .globl in32 + .globl in32 in32: - lwz 3,0x0000(3) - blr + lwz 3,0x0000(3) + blr //------------------------------------------------------------------------------- -// Function: in32r -// Description: Input 32 bits and byte reverse +// Function: in32r +// Description: Input 32 bits and byte reverse //------------------------------------------------------------------------------- - .globl in32r + .globl in32r in32r: - lwbrx r3,r0,r3 - blr + lwbrx r3,r0,r3 + blr //------------------------------------------------------------------------------- -// Function: ppcDcbf -// Description: Data Cache block flush -// Input: r3 = effective address -// Output: none. +// Function: ppcDcbf +// Description: Data Cache block flush +// Input: r3 = effective address +// Output: none. //------------------------------------------------------------------------------- - .globl ppcDcbf + .globl ppcDcbf ppcDcbf: - dcbf r0,r3 - blr + dcbf r0,r3 + blr //------------------------------------------------------------------------------- -// Function: ppcDcbi -// Description: Data Cache block Invalidate -// Input: r3 = effective address -// Output: none. +// Function: ppcDcbi +// Description: Data Cache block Invalidate +// Input: r3 = effective address +// Output: none. //------------------------------------------------------------------------------- - .globl ppcDcbi + .globl ppcDcbi ppcDcbi: - dcbi r0,r3 - blr + dcbi r0,r3 + blr //------------------------------------------------------------------------------- -// Function: ppcSync -// Description: Processor Synchronize -// Input: none. -// Output: none. +// Function: ppcSync +// Description: Processor Synchronize +// Input: none. +// Output: none. //------------------------------------------------------------------------------- - .globl ppcSync + .globl ppcSync ppcSync: - sync - blr + sync + blr /*------------------------------------------------------------------------------*/ @@ -816,7 +820,7 @@ relocate_code: icbi 0,r4 add r4,r4,r6 blt 6b -7: sync /* Wait for all icbi to complete on bus */ +7: sync /* Wait for all icbi to complete on bus */ isync /* @@ -833,8 +837,8 @@ in_ram: /* * Relocation Function, r14 point to got2+0x8000 * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. */ li r0,__got2_entries@sectoff@l la r3,GOT(_GOT2_TABLE_) @@ -848,7 +852,7 @@ in_ram: bdnz 1b /* - * Now adjust the fixups and the pointers to the fixups + * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ 2: li r0,__fixup_entries@sectoff@l diff --git a/include/config_sbc8260.h b/include/config_sbc8260.h index ea48f4b..749e7c5 100644 --- a/include/config_sbc8260.h +++ b/include/config_sbc8260.h @@ -113,10 +113,10 @@ * if CONFIG_CONS_NONE is defined, then the serial console routines must * defined elsewhere. */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ +#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ /* * select ethernet configuration @@ -134,17 +134,17 @@ #define CONFIG_ETHER_USE_FCC2 #ifdef CONFIG_ETHER_USE_SCC1 -#define CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ +#define CONFIG_ETHER_ON_SCC 1 /* define if ethernet on SCC */ +#undef CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ #endif /* CONFIG_ETHER_USE_SCC1 */ #ifdef CONFIG_ETHER_USE_FCC2 -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ #endif /* CONFIG_ETHER_USE_FCC2 */ /* Define this to reserve an entire FLASH sector (256 KB) for @@ -152,7 +152,7 @@ * put in the same sector as ppcboot, and changing variables * will erase ppcboot temporarily */ -#define CFG_ENV_IN_OWN_SECT 1 +#define CFG_ENV_IN_OWN_SECT 1 /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -173,11 +173,25 @@ #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" #define CONFIG_AUTOBOOT_STOP_STR " " #undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 +#define DEBUG_BOOTKEYS 0 /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */ +#define CONFIG_BOOT_ROOT_INITRD 0 /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS 1 /* Use a NFS mounted root file system */ + +#if CONFIG_BOOT_ROOT_INITRD +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/ram0 rw " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_INITRD */ + +#if CONFIG_BOOT_ROOT_NFS #define CONFIG_BOOTCOMMAND \ "version;" \ "echo;" \ @@ -185,6 +199,7 @@ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ "bootm" +#endif /* CONFIG_BOOT_ROOT_NFS */ /* Add support for a few extra bootp options like: * - File size @@ -204,7 +219,7 @@ #define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | CFG_CMD_BEDBUG) /* Where do the internal registers live? */ -#define CFG_IMMR 0xf0000000 +#define CFG_IMMR 0xf0000000 /***************************************************************************** * @@ -222,23 +237,33 @@ * Miscellaneous configurable options */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_MAXARGS 8 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x140000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ +#define CFG_MEMTEST_START CFG_LOAD_ADDR + /* memtest works on the load */ + /* addr to the end of the DRAM */ + /* less monitor and malloc area */ +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ + - CFG_MEM_END_USAGE ) /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -249,8 +274,10 @@ * You should know what you are doing if you make changes here. */ -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE +#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE /*----------------------------------------------------------------------- * Hard Reset Configuration Words @@ -262,28 +289,28 @@ #endif /* defined(CFG_SBC_BOOT_LOW) */ /* get the HRCW ISB field from CFG_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ - ((CFG_IMMR & 0x01000000) >> 7) |\ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER (HRCW_BPS11 |\ - HRCW_DPPC11 |\ - CFG_SBC_HRCW_IMMR |\ - HRCW_MMR00 |\ - HRCW_LBPC11 |\ - HRCW_APPC10 |\ - HRCW_CS10PC00 |\ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\ - CFG_SBC_HRCW_BOOT_FLAGS) +#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ + ((CFG_IMMR & 0x01000000) >> 7) | \ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER ( HRCW_BPS11 | \ + HRCW_DPPC11 | \ + CFG_SBC_HRCW_IMMR | \ + HRCW_MMR00 | \ + HRCW_LBPC11 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ + CFG_SBC_HRCW_BOOT_FLAGS ) /* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) @@ -306,15 +333,15 @@ # define CFG_RAMBOOT #endif -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH and environment organization @@ -497,7 +524,6 @@ * Hmmm, 8 8Mx8 chips = 64 MB not 16. Well, we'll * pretend it's only 16 MB. */ -#define CFG_SDRAM_SIZE 16 #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ diff --git a/net/tftp.c b/net/tftp.c index 82cdd35..5660ea6 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -18,7 +18,7 @@ #define TIMEOUT 2 /* Seconds to timeout for a lost pkt */ #define TIMEOUT_COUNT 10 /* # of timeouts before giving up */ /* (for checking the image size) */ -#define NDOTS 65 /* Number of "loading" dots */ +#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ /* * TFTP operations. @@ -145,7 +145,11 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) return; len -= 2; TftpBlock = SWAP16(*(ushort *)pkt); - if (((TftpBlock - 1) % 10) == 0) putc ('#'); + if (((TftpBlock - 1) % 10) == 0) { + putc ('#'); + } else if ((TftpBlock % (10 * HASHES_PER_LINE)) == 0) { + puts ("\n\t "); + } if (TftpState == STATE_RRQ) { TftpState = STATE_DATA; diff --git a/ppc/vsprintf.c b/ppc/vsprintf.c index 6e7d38d..0ca2f5d 100644 --- a/ppc/vsprintf.c +++ b/ppc/vsprintf.c @@ -15,6 +15,10 @@ #include #include +#if !defined (CONFIG_PANIC_HANG) +#include +#include /* for do_reset() prototype */ +#endif unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) { @@ -328,7 +332,7 @@ void panic(const char *fmt, ...) printf(fmt); putc('\n'); va_end(args); -#if 1 +#if defined (CONFIG_PANIC_HANG) hang(); #else udelay (100000); /* allow messages to go out */