From: Rob Gardner Date: Fri, 30 Oct 2015 19:18:00 +0000 (-0600) Subject: SPARC64: Respect no-fault ASI for floating exceptions X-Git-Tag: v4.1.12-92~30^2~2 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=c7a569f4be83c5bd392225ec9c603d7126759f75;p=users%2Fjedix%2Flinux-maple.git SPARC64: Respect no-fault ASI for floating exceptions Floating point load instructions using ASI_PNF or other no-fault ASIs should never cause a SIGFPE. A store-quad instruction should naturally fault if a non-quad register is given, but this constraint should not apply to loads, which may be single precision, double, or quad, and the only constraint should be that the target register type be appropriate for the precision of the load. A bug in handle_ldf_stq() unnecessarily restricts no-fault loads to quad registers, and causes a floating point exception if one is not given. This restriction is removed. Orabug: 24942761 Signed-off-by: Rob Gardner Signed-off-by: Allen Pais Signed-off-by: Dave Kleikamp --- diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c index 62098a89bbbf..d9f3f45f9e53 100644 --- a/arch/sparc/kernel/unaligned_64.c +++ b/arch/sparc/kernel/unaligned_64.c @@ -445,15 +445,15 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs) save_and_clear_fpu(); current_thread_info()->xfsr[0] &= ~0x1c000; - if (freg & 3) { - current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; - do_fpother(regs); - return 0; - } if (insn & 0x200000) { /* STQ */ u64 first = 0, second = 0; + if (freg & 3) { + current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; + do_fpother(regs); + return 0; + } if (current_thread_info()->fpsaved[0] & flag) { first = *(u64 *)&f->regs[freg]; second = *(u64 *)&f->regs[freg+2];