From: wdenk Date: Sat, 26 May 2001 20:37:15 +0000 (+0000) Subject: Add CAN driver support for TQM8xxL boards. X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=b984f768549f960f12291704e4cf5819a09d0f7f;p=users%2Frw%2Fppcboot.git Add CAN driver support for TQM8xxL boards. Cleanup of C++ commants in some files. --- diff --git a/CHANGELOG b/CHANGELOG index e4b182b..9a698a1 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,10 +56,14 @@ To do: Modifications for 0.9.3: ====================================================================== +* Added CAN Bus Driver support for TQM8xxL systems + * Completed support for CU824 board * Fixed PCU E configuration for other / bigger flash types +* Cleanup of C++ style // comments which cause C compiler warnings. + ====================================================================== Modifications for 0.9.2: ====================================================================== diff --git a/README b/README index 99b565d..1f2a1ef 100644 --- a/README +++ b/README @@ -366,6 +366,22 @@ The following options need to be configured: 4th and following BOOTP requests: delay 0 ... 8 sec +- Status LED: CONFIG_STATUS_LED + + Several configurations allow to display the current + status using a LED. For instance, the LED will blink + fast while running PPCBoot code, stop blinking as + soon as a reply to a BOOTP request was received, and + start blinking slow once the Linux kernel is running + (supported by a status LED driver in the Linux + kernel). Defining CONFIG_STATUS_LED enables this + feature in PPCBoot. + +- CAN Support: CONFIG_CAN_DRVER + + Defining CONFIG_CAN_DRIVER enables CAN driver support + on those systems that support this (optional) + feature, like the TQM8xxL modules. Configuration Settings: ----------------------- diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index a387325..68bd738 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -127,7 +127,9 @@ long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; + long int size8, size9; + long int size_b0 = 0; + long int size_b1 = 0; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); @@ -149,10 +151,12 @@ long int initdram (int board_type) memctl->memc_or2 = CFG_OR2_PRELIM; memctl->memc_br2 = CFG_BR2_PRELIM; +#ifndef CONFIG_CAN_DRIVER if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ memctl->memc_or3 = CFG_OR3_PRELIM; memctl->memc_br3 = CFG_BR3_PRELIM; } +#endif /* CONFIG_CAN_DRIVER */ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ @@ -165,12 +169,14 @@ long int initdram (int board_type) memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ udelay(1); +#ifndef CONFIG_CAN_DRIVER if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ udelay(1); memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ udelay(1); } +#endif /* CONFIG_CAN_DRIVER */ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ @@ -200,6 +206,7 @@ long int initdram (int board_type) /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } +#ifndef CONFIG_CAN_DRIVER if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ /* * Check Bank 1 Memory Size @@ -213,6 +220,7 @@ long int initdram (int board_type) } else { size_b1 = 0; } +#endif /* CONFIG_CAN_DRIVER */ udelay (1000); @@ -270,12 +278,14 @@ long int initdram (int board_type) + size_b0; } else { unsigned long reg; +#ifndef CONFIG_CAN_DRIVER /* * No bank 1 * * invalidate bank */ memctl->memc_br3 = 0; +#endif /* CONFIG_CAN_DRIVER */ /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; @@ -286,6 +296,48 @@ long int initdram (int board_type) udelay(10000); +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR3 / BR3 */ + memctl->memc_or3 = CFG_OR3_CAN; + memctl->memc_br3 = CFG_BR3_CAN; + + /* Initialize MBMR */ + memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMB; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMB; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMB; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMB; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMB; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMB; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMB; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMB; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMB; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMB; +#endif /* CONFIG_CAN_DRIVER */ + + return (size_b0 + size_b1); } diff --git a/include/config_TQM823L.h b/include/config_TQM823L.h index 19881e0..45f4560 100644 --- a/include/config_TQM823L.h +++ b/include/config_TQM823L.h @@ -62,6 +62,8 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION @@ -177,7 +179,11 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ +#ifndef CONFIG_CAN_DRIVER #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -324,8 +330,16 @@ #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#ifndef CONFIG_CAN_DRIVER #define CFG_OR3_PRELIM CFG_OR2_PRELIM #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ /* * Memory Periodic Timer Prescaler diff --git a/include/config_TQM850L.h b/include/config_TQM850L.h index 77f0669..7dc39a8 100644 --- a/include/config_TQM850L.h +++ b/include/config_TQM850L.h @@ -62,6 +62,8 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION @@ -177,7 +179,11 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ +#ifndef CONFIG_CAN_DRIVER #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -325,8 +331,16 @@ #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#ifndef CONFIG_CAN_DRIVER #define CFG_OR3_PRELIM CFG_OR2_PRELIM #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ /* * Memory Periodic Timer Prescaler diff --git a/include/config_TQM855L.h b/include/config_TQM855L.h index 32bdae0..05ab619 100644 --- a/include/config_TQM855L.h +++ b/include/config_TQM855L.h @@ -62,6 +62,8 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION @@ -177,7 +179,11 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ +#ifndef CONFIG_CAN_DRIVER #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -325,8 +331,16 @@ #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#ifndef CONFIG_CAN_DRIVER #define CFG_OR3_PRELIM CFG_OR2_PRELIM #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ /* * Memory Periodic Timer Prescaler diff --git a/include/config_TQM860L.h b/include/config_TQM860L.h index 2c08bf9..7813f3c 100644 --- a/include/config_TQM860L.h +++ b/include/config_TQM860L.h @@ -62,6 +62,8 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION @@ -177,7 +179,11 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ +#ifndef CONFIG_CAN_DRIVER #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -324,8 +330,16 @@ #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#ifndef CONFIG_CAN_DRIVER #define CFG_OR3_PRELIM CFG_OR2_PRELIM #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ /* * Memory Periodic Timer Prescaler diff --git a/include/config_pcu_e.h b/include/config_pcu_e.h index fa63f70..d2bb481 100644 --- a/include/config_pcu_e.h +++ b/include/config_pcu_e.h @@ -95,14 +95,17 @@ /* Ethernet hardware configuration done using port pins */ #define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */ #define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */ -//XXX#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ -//XXX#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */ -//XXX#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */ -//XXX#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */ +#if 0 /* XXX */ +#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ +#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */ +#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */ +#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */ +#else /* XXX */ #define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ #define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ #define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ #define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ +#endif /* XXX */ /* Ethernet settings: * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex @@ -148,7 +151,6 @@ #define CFG_SDRAM_BASE 0x00000000 /* this is an ugly hack needed because of the silly non-constant address map */ #define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) -//#define CFG_FLASH_BASE 0xFF000000 #if defined(DEBUG) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ @@ -310,8 +312,11 @@ */ #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -//XXX #define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ +#if 0 /* XXX */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ +#else /* XXX */ #define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ +#endif /* XXX */ /* * used to re-map FLASH: restrict access enough but not too much to @@ -330,29 +335,38 @@ /* 16 bit, bank valid */ #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -//XXX #define CFG_OR1_REMAP CFG_OR0_REMAP -//XXX #define CFG_OR1_PRELIM CFG_OR0_PRELIM -//XXX #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#if 0 /* XXX */ +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#else /* XXX */ #define CFG_OR6_REMAP CFG_OR0_REMAP #define CFG_OR6_PRELIM CFG_OR0_PRELIM #define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#endif /* XXX */ /* * BR2/OR2: SDRAM * * Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -//XXX #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ +#if 0 /* XXX */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ +#else /* XXX */ #define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ +#endif /* XXX */ #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ #define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ -//XXX #define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -//XXX #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#if 0 /* XXX */ +#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* XXX */ #define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) #define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#endif /* XXX */ /* * Memory Periodic Timer Prescaler diff --git a/include/version.h b/include/version.h index b7e3b14..2e92633 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define PPCBOOT_VERSION "PPCBoot 0.9.3-pre1" +#define PPCBOOT_VERSION "PPCBoot 0.9.3-pre2" #endif /* __VERSION_H__ */ diff --git a/tools/envcrc.c b/tools/envcrc.c index f699fa6..da12e80 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -63,7 +63,7 @@ int main (int argc, char **argv) crc = crc32(0, dataptr, datasize) ; - // Check if verbose mode is activated passing a parameter to the program + /* Check if verbose mode is activated passing a parameter to the program */ if (argc > 1) { printf("CRC32 from offset %08X to %08X of environment = %08X\n", (unsigned int)(dataptr - envptr),