From: wdenk Date: Wed, 7 Feb 2001 00:09:33 +0000 (+0000) Subject: * If we power on the 12V disk drive voltage, we must allow for at X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=b90a79f33cb7770ce2e4abdf10b6655f486914e6;p=users%2Frw%2Fppcboot.git * If we power on the 12V disk drive voltage, we must allow for at least 500 ms for everything to stabilize and come up (IVML24) * Fix address range used for mtest for some configurations that tried to test the exception vector area --- diff --git a/CHANGELOG b/CHANGELOG index 0a0bdfe..ae89564 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -61,6 +61,12 @@ To do: Modifications for 0.8.2: ====================================================================== +* If we power on the 12V disk drive voltage, we must allow for at + least 500 ms for everything to stabilize and come up (IVML24) + +* Fix address range used for mtest for some configurations that tried + to test the exception vector area + * Squeeze a few bytes here and there to make it fit in 128k again. Sic! * Don't count-down if no bootcmd is defined @@ -81,6 +87,9 @@ Modifications for 0.8.2: Modifications for 0.8.1: ====================================================================== +* Added CFG_RAMBOOT option to be able to boot PPCBoot image in RAM + (Marius Gröger 2001-01-31) + * Added "echo" command * Added "tags" make target diff --git a/common/cmd_boot.c b/common/cmd_boot.c index 1d17bec..5dee9fe 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -71,7 +71,7 @@ void do_bdinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); } #ifdef CONFIG_HERMES - print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed); + print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed)); #endif printf ("\n IP addr = "); print_IPaddr (bd->bi_ip_addr); printf ("\n baudrate = %6ld bps\n", bd->bi_baudrate ); diff --git a/common/cmd_ide.c b/common/cmd_ide.c index d8d2d67..774276f 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -976,6 +976,13 @@ static void ide_reset (void) immr->im_cpm.cp_pbpar &= ~(CFG_PB_12V_ENABLE); immr->im_cpm.cp_pbodr &= ~(CFG_PB_12V_ENABLE); immr->im_cpm.cp_pbdir |= CFG_PB_12V_ENABLE; + + /* We must wait at least 500 ms for the voltage to stabilize; + * this is an additional 250 ms to the 250 m,s we already wait below + */ + for (i=0; i<25; ++i) { + udelay (10000); + } #endif /* CFG_PB_12V_ENABLE */ #ifdef CFG_PB_IDE_MOTOR @@ -987,6 +994,7 @@ static void ide_reset (void) } #endif /* CFG_PB_IDE_MOTOR */ + /* wait 250 ms */ for (i=0; i<25; ++i) { udelay (10000); } diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 1a7092f..370bdf5 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -329,7 +329,7 @@ void do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) puts (name); putc ('='); while (k < nxt) - putc(get_env_char(k)); + putc(get_env_char(k++)); putc ('\n'); break; } diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index c35e938..eeb0655 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -180,7 +180,9 @@ boot_warm: bl init_8260_core - /* Clear the Address Mask in OR0 so flash appears everywhere */ +#ifndef CFG_RAMBOOT + /* When booting from ROM (Flash or EPROM), clear the */ + /* Address Mask in OR0 so ROM appears everywhere */ /*--------------------------------------------------------------*/ lis r3, (CFG_IMMR+IM_REGBASE)@h @@ -199,6 +201,7 @@ boot_warm: blr in_flash: +#endif /* CFG_RAMBOOT */ /* initialize some things that are hard to access from C */ /*--------------------------------------------------------------*/ diff --git a/include/config_FADS823.h b/include/config_FADS823.h index 2ffbf9c..518a9f5 100644 --- a/include/config_FADS823.h +++ b/include/config_FADS823.h @@ -120,8 +120,8 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ #define CFG_LOAD_ADDR 0x00100000 /* default load address */ diff --git a/include/config_FADS850SAR.h b/include/config_FADS850SAR.h index 5c8c2d1..7bb3a21 100644 --- a/include/config_FADS850SAR.h +++ b/include/config_FADS850SAR.h @@ -78,8 +78,8 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ #define CFG_LOAD_ADDR 0x00100000 /* default load address */ diff --git a/include/config_GENIETV.h b/include/config_GENIETV.h index 7c2a5d8..0f422c5 100644 --- a/include/config_GENIETV.h +++ b/include/config_GENIETV.h @@ -120,8 +120,8 @@ #define CFG_MAXARGS 8 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ #define CFG_LOAD_ADDR 0x00100000 /* default load address */ diff --git a/include/config_Sandpoint8240.h b/include/config_Sandpoint8240.h index 4bcd849..a847de7 100644 --- a/include/config_Sandpoint8240.h +++ b/include/config_Sandpoint8240.h @@ -62,7 +62,7 @@ #endif #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ #define CFG_EUMB_ADDR 0xFC000000 diff --git a/include/config_rsdproto.h b/include/config_rsdproto.h index 5049077..d3cebb4 100644 --- a/include/config_rsdproto.h +++ b/include/config_rsdproto.h @@ -196,11 +196,15 @@ * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependend. */ #define CFG_SDRAM_BASE PHYS_SDRAM_60X #define CFG_FLASH_BASE 0xFFF00000 //#define CFG_MONITOR_BASE 0x200000 #define CFG_MONITOR_BASE 0xfff00000 +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMBOOT +#endif #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */