From: Ajit Kumar Pandey Date: Fri, 4 Mar 2022 20:57:27 +0000 (-0600) Subject: ASoC: SOF: amd: Flush cache after ATU_BASE_ADDR_GRP register update X-Git-Tag: howlett/maple/20220722_2~954^2~7^2~55^2~6 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=b7485ec850591ad62fde0526bd7fdc56cdc04efd;p=users%2Fjedix%2Flinux-maple.git ASoC: SOF: amd: Flush cache after ATU_BASE_ADDR_GRP register update ACP_SRAM_PTE block has cache that needs to be flushed after every PTE updates. This patch updates ACPAXI2AXI_ATU_CTRL register to flush cache after updating PTE with stream physical address. Reviewed-by: Ranjani Sridharan Signed-off-by: Ajit Kumar Pandey Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220304205733.62233-5-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown --- diff --git a/sound/soc/sof/amd/acp-stream.c b/sound/soc/sof/amd/acp-stream.c index f2837bfbdb20..b3ca4a90dbf8 100644 --- a/sound/soc/sof/amd/acp-stream.c +++ b/sound/soc/sof/amd/acp-stream.c @@ -115,6 +115,9 @@ int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *strea offset += 8; } + /* Flush ATU Cache after PTE Update */ + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID); + return 0; }