From: wdenk Date: Mon, 15 Oct 2001 14:47:04 +0000 (+0000) Subject: Added CFG_DEFAULT_IMMR: X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=b69dbeae05adf0a111d296bc6bd77bb44bbd60ca;p=users%2Frw%2Fppcboot.git Added CFG_DEFAULT_IMMR: Default address of the IMMR after system reset. Needed on some 8260 systems (MPC8260ADS and RPXsuper) to be able to adjust the position of the IMMR register after a reset. --- diff --git a/CHANGELOG b/CHANGELOG index 1b5efe2..7996642 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,10 @@ To do: Modifications for 1.0.6: ====================================================================== +* Added CFG_DEFAULT_IMMR: Default address of the IMMR after system + reset. Needed on some 8260 systems (MPC8260ADS and RPXsuper) to be + able to adjust the position of the IMMR register after a reset. + * Allow to pass parameters (start and end address, start pattern) to "mtest" command diff --git a/README b/README index 1d8cc02..f2056f5 100644 --- a/README +++ b/README @@ -845,6 +845,12 @@ Low Level (hardware related) configuration options: - CFG_CACHELINE_SIZE: Cache Line Size of the CPU. +- CFG_DEFAULT_IMMR: + Default address of the IMMR after system reset. + Needed on some 8260 systems (MPC8260ADS and RPXsuper) + to be able to adjust the position of the IMMR + register after a reset. + - CFG_IMMR: Physical address of the Internal Memory Mapped Register; DO NOT CHANGE! (11-4) [MPC8xx systems only] diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index f5440bf..96f1ea4 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -181,12 +181,12 @@ boot_warm: bl cogent_init_8260 #endif /* CONFIG_COGENT */ -#if defined(CONFIG_DEFAULT_HRCW) +#if defined(CFG_DEFAULT_IMMR) lis r3, CFG_IMMR@h ori r3, r3, CFG_IMMR@l - lis r4, 0x00010000@h + lis r4, CFG_DEFAULT_IMMR@h stw r3, 0x1A8(r4) -#endif /* CONFIG_DEFAULT_HRCW */ +#endif /* CFG_DEFAULT_IMMR */ /* Initialise the MPC8260 processor core */ /*--------------------------------------------------------------*/ diff --git a/include/config_MPC8260ADS.h b/include/config_MPC8260ADS.h index f783a21..80f9cfb 100644 --- a/include/config_MPC8260ADS.h +++ b/include/config_MPC8260ADS.h @@ -3,7 +3,7 @@ * Stuart Hughes * This file is based on similar values for other boards found in other * ppcboot config files, and some that I found in the mpc8260ads manual. - * + * * Note: my board is a PILOT rev. * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. * @@ -17,7 +17,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -57,9 +57,9 @@ * cogent/cma101/serial.[ch]). */ #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ #undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ /* * select ethernet configuration @@ -73,7 +73,7 @@ * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ @@ -105,7 +105,7 @@ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ @@ -116,15 +116,15 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ @@ -133,44 +133,46 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ /* for versions < 2.4.5-pre5 */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_FLASH_BASE 0xff800000 -#define FLASH_BASE 0xff800000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ -#define CFG_FLASH_SIZE 8 -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_BASE 0xff800000 +#define FLASH_BASE 0xff800000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ /* this is stuff came out of the Motorola docs */ -#define CFG_IMMR 0x04700000 -#define CFG_BCSR 0x04500000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_LSDRAM_BASE 0x04000000 +#define CFG_DEFAULT_IMMR 0x0F010000 + +#define CFG_IMMR 0x04700000 +#define CFG_BCSR 0x04500000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_LSDRAM_BASE 0x04000000 -#define RS232EN_1 0x02000002 -#define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 +#define RS232EN_1 0x02000002 +#define RS232EN_2 0x01000001 +#define FETHIEN 0x08000008 +#define FETH_RST 0x04000004 -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET /* 0x0EA28205 */ -#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ - ( HRCW_BMS | HRCW_APPC10 ) |\ - ( HRCW_MODCK_H0101 ) \ - ) +#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ + ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ + ( HRCW_BMS | HRCW_APPC10 ) |\ + ( HRCW_MODCK_H0101 ) \ + ) /* no slaves */ #define CFG_HRCW_SLAVE1 0 @@ -181,17 +183,17 @@ #define CFG_HRCW_SLAVE6 0 #define CFG_HRCW_SLAVE7 0 -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) # define CFG_RAMBOOT #endif -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #ifndef CFG_RAMBOOT # define CFG_ENV_IS_IN_FLASH 1 @@ -199,37 +201,37 @@ # define CFG_ENV_SECT_SIZE 0x40000 #else # define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 #endif /* CFG_RAMBOOT */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif #define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CFG_HID2 0 - -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x100C0000 -#define CFG_SIUMCR 0x0A200000 -#define CFG_SCCR 0x00000000 -#define CFG_BR0_PRELIM 0xFF801801 -#define CFG_OR0_PRELIM 0xFF800836 -#define CFG_BR1_PRELIM 0x04501801 -#define CFG_OR1_PRELIM 0xFFFF8010 - -#define CFG_RMR 0 -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 -#define CFG_PSDMR 0x016EB452 -#define CFG_MPTPR 0x00001900 -#define CFG_PSRT 0x00000021 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) + +#define CFG_HID2 0 + +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x100C0000 +#define CFG_SIUMCR 0x0A200000 +#define CFG_SCCR 0x00000000 +#define CFG_BR0_PRELIM 0xFF801801 +#define CFG_OR0_PRELIM 0xFF800836 +#define CFG_BR1_PRELIM 0x04501801 +#define CFG_OR1_PRELIM 0xFFFF8010 + +#define CFG_RMR 0 +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 +#define CFG_PSDMR 0x016EB452 +#define CFG_MPTPR 0x00001900 +#define CFG_PSRT 0x00000021 #endif /* __CONFIG_H */ diff --git a/include/config_RPXsuper.h b/include/config_RPXsuper.h index aa5cd1d..8c5aa15 100644 --- a/include/config_RPXsuper.h +++ b/include/config_RPXsuper.h @@ -8,7 +8,7 @@ * *****************************************************************************/ /* for the AY-Revision which does not use the HRCW */ -#define CONFIG_DEFAULT_HRCW +#define CFG_DEFAULT_IMMR 0x00010000 /* What is the oscillator's (UX2) frequency in Hz? */ #define CONFIG_8260_CLKIN (66 * 1000 * 1000)