From: Imre Deak Date: Tue, 5 Aug 2025 07:36:47 +0000 (+0300) Subject: drm/i915/tc: Use the cached max lane count value X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=aaf01f66e0ee688f0df7eb941914c78fdecf1edd;p=users%2Fwilly%2Fxarray.git drm/i915/tc: Use the cached max lane count value Use the PHY's cached max lane count value on all platforms similarly to LNL+. On LNL+ using the cached value is mandatory - since the corresponding HW register field can get cleared by the time the value is queried - on earlier platforms there isn't a problem with using the HW register instead. Having a uniform way to query the value still makes sense and it's also a bit more efficient, so do that. Reviewed-by: Mika Kahola Link: https://lore.kernel.org/r/20250805073700.642107-7-imre.deak@intel.com Signed-off-by: Imre Deak --- diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 668ef139391b..f00fb6fc94d8 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -395,15 +395,11 @@ static void read_pin_configuration(struct intel_tc_port *tc) int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) { - struct intel_display *display = to_intel_display(dig_port); struct intel_tc_port *tc = to_tc_port(dig_port); if (!intel_encoder_is_tc(&dig_port->base)) return 4; - if (DISPLAY_VER(display) < 20) - return get_max_lane_count(tc); - return tc->max_lane_count; }