From: Mark Brown Date: Wed, 30 Apr 2025 14:33:59 +0000 (+0900) Subject: spi: axi-spi-engine: offload instruction optimization X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=a7f035c2c72496cf7ac34bfaa8c289e0d4c45836;p=users%2Fjedix%2Flinux-maple.git spi: axi-spi-engine: offload instruction optimization Merge series from David Lechner : In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK using the SPI offload feature of the AXI SPI Engine, we need to shave off some time that is spent executing unnecessary instructions. There are a few one-time setup instructions that can be moved so that they execute only once when the SPI offload trigger is enabled rather than repeating each time the offload is triggered. Additionally, a recent change to the IP block allows dropping the SYNC instruction completely. With these changes, we are left with only the 3 instructions that are needed to to assert CS, transfer the data, and deassert CS. This makes 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the available time period. --- a7f035c2c72496cf7ac34bfaa8c289e0d4c45836