From: Nick Chan Date: Thu, 20 Feb 2025 12:21:45 +0000 (+0800) Subject: arm64: dts: apple: s800-0-3: Add CPU caches X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=a7a38536f2ea5d3797b9d647d4a8abdaa36ebeb3;p=users%2Fjedix%2Flinux-maple.git arm64: dts: apple: s800-0-3: Add CPU caches Add information about CPU caches in both variants of Apple A9 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-4-2c7011097768@gmail.com Signed-off-by: Sven Peter --- diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi index c0e9ae45627c..09db4ed64054 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -46,6 +49,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; }; };