From: Klaus Jensen <k.jensen@samsung.com>
Date: Sun, 5 Mar 2023 21:36:45 +0000 (+0100)
Subject: hw/nvme: fix trace event for pin-based irq
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=a4324fa2efb2eb968bc1451543654df0170ce39f;p=qemu-nvme.git

hw/nvme: fix trace event for pin-based irq

The nvme_irq_pin trace event ("pulsing IRQ pin") is a left-over from
when the device used the deprecated (and invalid) pci_irq_pulse()
function.

Fix it to make it clear if the irq pin is being asserted or not.

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---

diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 983ca8afa9..c581106b06 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -647,12 +647,16 @@ static void nvme_irq_check(NvmeCtrl *n)
     PCIDevice *pci = PCI_DEVICE(n);
     uint32_t intms = ldl_le_p(&n->bar.intms);
 
+    trace_pci_nvme_irq_check(intms, n->irq_status);
+
     if (msix_enabled(pci)) {
         return;
     }
     if (~intms & n->irq_status) {
+        trace_pci_nvme_irq_pin(1);
         pci_irq_assert(pci);
     } else {
+        trace_pci_nvme_irq_pin(0);
         pci_irq_deassert(pci);
     }
 }
@@ -666,7 +670,6 @@ static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
             trace_pci_nvme_irq_msix(cq->vector);
             msix_notify(pci, cq->vector);
         } else {
-            trace_pci_nvme_irq_pin();
             assert(cq->vector < 32);
             n->irq_status |= 1 << cq->vector;
             nvme_irq_check(n);
diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events
index 9afddf3b95..7a982b8313 100644
--- a/hw/nvme/trace-events
+++ b/hw/nvme/trace-events
@@ -1,6 +1,7 @@
 # successful events
 pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u"
-pci_nvme_irq_pin(void) "pulsing IRQ pin"
+pci_nvme_irq_check(uint32_t intms, uint32_t irq_status) "intms 0x%"PRIx32" irq_status 0x%"PRIx32""
+pci_nvme_irq_pin(uint8_t assert) "assert %"PRIu8""
 pci_nvme_irq_masked(void) "IRQ is masked"
 pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2=0x%"PRIx64""
 pci_nvme_dbbuf_config(uint64_t dbs_addr, uint64_t eis_addr) "dbs_addr=0x%"PRIx64" eis_addr=0x%"PRIx64""