From: Luca Coelho Date: Wed, 27 Aug 2025 10:12:06 +0000 (+0300) Subject: drm/i915: use REG_BIT on FW_BLC_SELF_* macros X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=a304609be24ec94ddb9b18a5cf6357e58466ac5e;p=users%2Fhch%2Fmisc.git drm/i915: use REG_BIT on FW_BLC_SELF_* macros Use REG_BIT() instead of open coding the shift in the FW_BLC_SELF_* macro definitions to avoid potentially typing them as 'int'. For example, this happens when we pass them to _MASKED_BIT_ENABLE(), because of the typeof() construct there. When we pass 1 << 15 (the FW_BLC_SELF_EN macro), we get typeof(1 << 15), which is 'int'. Then the value becomes negative (-2147450880) and we try to assign it to a 'u32'. In practice this is not a problem though, because when we try to assign -2147450880 to the u32, that becomes 0x80008000, which was the intended result. Link: https://lore.kernel.org/intel-gfx/20250827111109.401604-1-luciano.coelho@intel.com/ Reviewed-by: Jani Nikula Reviewed-by: Andi Shyti Signed-off-by: Luca Coelho --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b283b25d8368..354ef75ef6a5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -412,9 +412,9 @@ #define FW_BLC _MMIO(0x20d8) #define FW_BLC2 _MMIO(0x20dc) #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ -#define FW_BLC_SELF_EN_MASK (1 << 31) -#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ -#define FW_BLC_SELF_EN (1 << 15) /* 945 only */ +#define FW_BLC_SELF_EN_MASK REG_BIT(31) +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ #define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 #define LM_BURST_LENGTH 0x00000700