From: wdenk <wdenk>
Date: Wed, 10 Oct 2001 09:28:28 +0000 (+0000)
Subject: * On MPC8240, enable dcache and allocate space for the initial data
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=a2a0f0fb97b16980b2ec511da3540ed97fd7fb93;p=users%2Frw%2Fppcboot.git

* On MPC8240, enable dcache and allocate space for the initial data
  structure and initial stack in it; the MMU had to be enabled
  because burst-mode accesses to Flash wouldn't work otherwise.
  Tested on CU824, but should work for other 8240-based systems as
  well.

* Added Configuration for MPC8260ADS board
  (Patch by Stuart Hughes, 07 Oct 2001)

* Add automatic RAM size detection to CU824 board configuration

* Make eth_halt() do nothing when ethernet has never been initialized
  (board/{esd/common,cu824}/dc2114x.c)
---

diff --git a/CHANGELOG b/CHANGELOG
index 8336690..6e4478e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -56,6 +56,20 @@ To do:
 Modifications for 1.0.6:
 ======================================================================
 
+* On MPC8240, enable dcache and allocate space for the initial data
+  structure and initial stack in it; the MMU had to be enabled
+  because burst-mode accesses to Flash wouldn't work otherwise.
+  Tested on CU824, but should work for other 8240-based systems as
+  well.
+
+* Added Configuration for MPC8260ADS board
+  (Patch by Stuart Hughes, 07 Oct 2001)
+
+* Add automatic RAM size detection to CU824 board configuration
+
+* Make eth_halt() do nothing when ethernet has never been initialized
+  (board/{esd/common,cu824}/dc2114x.c)
+
 * Fix duplicate "preboot" environment entry
 
 * Patch by Jerry Van Baren, 19 Sep 2001:
@@ -88,6 +102,8 @@ Modifications for 1.0.6:
   CONFIG_PPC405   -> CONFIG_4xx
   CONFIG_PPC405GP -> CONFIG_405GP
   CONFIG_PPC405CR -> CONFIG_405CR
+- PPC405GP: Changed pci master configuration for Linux compatibility
+  (no more need for bios_fixup())
 
 * Remove references to obsolete CFG_HWINFO_LEN stuff
 
@@ -143,10 +159,10 @@ Modifications for 1.0.5:
 
   For binary compatibility with older Linux kernels (which expect the
   clocks passed in the bd_info data to be in MHz) the environment
-  variable "clock_in_mhz" can be defined so that PPCBoot converts
+  variable "clocks_in_mhz" can be defined so that PPCBoot converts
   clock data to MHZ before passing it to the Linux kernel. When
   CONFIG_CLOCKS_IN_MHZ is defined in the board config file, a
-  definition of "clock_in_mhz=1" is automatically included in the
+  definition of "clocks_in_mhz=1" is automatically included in the
   default environment.
 
   NOTE: for all boards that did not use the (now obsolete)
diff --git a/CREDITS b/CREDITS
index 9f4e011..bd75e15 100644
--- a/CREDITS
+++ b/CREDITS
@@ -93,6 +93,10 @@ E: huber@alum.wpi.edu
 D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
 W: http://www.mclx.com/
 
+H: Stuart Hughes
+E: stuarth@lineo.com
+D: Port to MPC8260ADS board
+
 N: Murray Jensen
 E: Murray.Jensen@cmst.csiro.au
 D: Initial 8260 support; GDB support; Port to Cogent+Hymod boards; Hymod Board Database
diff --git a/MAKEALL b/MAKEALL
index 469a94b..d06000b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -55,6 +55,7 @@ LIST="$LIST	\
 LIST="$LIST	\
 	cogent_mpc8260	\
 	hymod		\
+	MPC8260ADS	\
 	PM826		\
 	RPXsuper	\
 	rsdproto	\
diff --git a/Makefile b/Makefile
index ef27856..a6c2f89 100644
--- a/Makefile
+++ b/Makefile
@@ -488,6 +488,14 @@ hymod_config:	unconfig
 	echo "CPU   = mpc8260"	>>config.mk ;	\
 	echo "#include <config_$(@:_config=).h>" >config.h
 
+MPC8260ADS_config:	unconfig
+	@echo "Configuring for $(@:_config=) Board..." ; \
+	cd include ;				\
+	echo "ARCH  = ppc"	> config.mk ;	\
+	echo "BOARD = mpc8260ads" >>config.mk ;	\
+	echo "CPU   = mpc8260"	>>config.mk ;	\
+	echo "#include <config_$(@:_config=).h>" >config.h
+
 PM826_config: unconfig
 	@echo "Configuring for $(@:_config=) Board..." ; \
 	cd include ;				\
diff --git a/README b/README
index 65cddfb..7bdfd63 100644
--- a/README
+++ b/README
@@ -257,12 +257,12 @@ The following options need to be configured:
                 internally. For binary compatibility with older Linux
                 kernels (which expect the clocks passed in thr
                 bd_info data to be in MHz) the environment variable
-                "clock_in_mhz" can be defined so that PPCBoot
+                "clocks_in_mhz" can be defined so that PPCBoot
                 converts clock data to MHZ before passing it to the
                 Linux kernel.
 
                 When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
-                "clock_in_mhz=1" is  automatically  included  in  the
+                "clocks_in_mhz=1" is  automatically  included  in  the
                 default environment.
 
 - Console Interface:
diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c
index 060a991..df18de9 100644
--- a/board/cu824/cu824.c
+++ b/board/cu824/cu824.c
@@ -54,9 +54,48 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-		/* Nothing left to init here. Everthing is done in cpu_init_f().
-		 */
-	return CFG_RAM_SIZE;
-}
+	int              i, cnt;
+	volatile uchar * base      = CFG_SDRAM_BASE;
+	volatile ulong * addr;
+	ulong            save[32];
+	ulong            val, ret  = 0;
+
+	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *)base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *)base;
+	save[i] = *addr;
+	*addr = 0;
 
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
 
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+		addr = (volatile ulong *)base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof(long) - 1;
+			ulong mear1  = mpc8240_mpc107_getreg(MEAR1);
+			ulong emear1 = mpc8240_mpc107_getreg(EMEAR1);
+			mear1 =  (mear1  & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+			mpc8240_mpc107_setreg(MEAR1,  mear1);
+			mpc8240_mpc107_setreg(EMEAR1, emear1);
+
+			ret = cnt * sizeof(long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+Done:
+	return ret;
+}
diff --git a/board/cu824/dc2114x.c b/board/cu824/dc2114x.c
index 0f1a9fd..9af8983 100644
--- a/board/cu824/dc2114x.c
+++ b/board/cu824/dc2114x.c
@@ -414,6 +414,11 @@ int eth_rx(void)
 
 void eth_halt(void)
 {
+	if (iobase != CFG_ETH_IOBASE) {
+		/* Ethernet has not been initialized yet.  */
+		return;
+	}
+
 	STOP_DE4X5;
 	outl(0, DE4X5_SICR);
 	CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, SLEEP);
diff --git a/board/esd/common/dc2114x.c b/board/esd/common/dc2114x.c
index 566eef2..4ab03e4 100644
--- a/board/esd/common/dc2114x.c
+++ b/board/esd/common/dc2114x.c
@@ -479,9 +479,14 @@ int eth_rx(void)
 void eth_halt(void)
 {
 #if 1
-  STOP_DE4X5;
-  outl(0, DE4X5_SICR);
-  PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_CFDA_PSM, SLEEP, 1);
+	if (iobase != CFG_ETH_IOBASE) {
+		/* Ethernet has not been initialized yet.  */
+		return;
+	}
+
+	STOP_DE4X5;
+	outl(0, DE4X5_SICR);
+	PCI_Write_CFG_Reg(CFG_ETH_DEV_FN, PCI_CFDA_PSM, SLEEP, 1);
 #endif
 }
 
diff --git a/board/mpc8260ads/Makefile b/board/mpc8260ads/Makefile
new file mode 100644
index 0000000..dfb8829
--- /dev/null
+++ b/board/mpc8260ads/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o 
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8260ads/config.mk b/board/mpc8260ads/config.mk
new file mode 100644
index 0000000..9d55598
--- /dev/null
+++ b/board/mpc8260ads/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8260ads board
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/mpc8260ads/flash.c b/board/mpc8260ads/flash.c
new file mode 100644
index 0000000..ab866cc
--- /dev/null
+++ b/board/mpc8260ads/flash.c
@@ -0,0 +1,466 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.  
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+
+typedef volatile unsigned char	vu_char;
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifndef CONFIG_MPC8260ADS
+	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+#endif
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+#ifndef CONFIG_MPC8260ADS
+	bcsr->bd_ctrl |= BD_CTRL_FLWE;
+#endif
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+#ifndef CONFIG_MPC8260ADS
+	/* Remap FLASH according to real size */
+	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br1 & ~(BR_BA_MSK));
+#endif
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+
+	value = addr[0] & 0x00FF00FF;
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr;
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x80808080) != 0x80808080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+		}
+	}
+
+	/* reset to read mode */
+	*addr = 0xFFFFFFFF;	/* reset bank */
+
+	printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+	while (((csr = *addr) & 0x80808080) != 0x80808080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c
new file mode 100644
index 0000000..8da8e5c
--- /dev/null
+++ b/board/mpc8260ads/mpc8260ads.c
@@ -0,0 +1,273 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ * 
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   1,   0,   0,   0,   0   }, /* LXT970 FETHMDC */
+	/* PC9  */ {   1,   1,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+typedef struct bscr_ {
+	unsigned long bcsr0;
+	unsigned long bcsr1;
+	unsigned long bcsr2;
+	unsigned long bcsr3;
+	unsigned long bcsr4;
+	unsigned long bcsr5;
+	unsigned long bcsr6;
+	unsigned long bcsr7;
+} bcsr_t;
+
+void reset_phy(void)
+{
+    volatile bcsr_t  *bcsr           = (bcsr_t *)CFG_BCSR;
+
+    /* reset the FEC port */
+    bcsr->bcsr1                    &= ~FETH_RST;
+    bcsr->bcsr1                    |= FETH_RST;
+}
+
+
+int board_pre_init(void)
+{
+    volatile bcsr_t  *bcsr         = (bcsr_t *)CFG_BCSR;
+    bcsr->bcsr1                    = ~FETHIEN & ~RS232EN_1;
+
+    return 0;
+}
+
+long int initdram(int board_type)
+{
+    volatile immap_t *immap         = (immap_t *)CFG_IMMR;
+    volatile memctl8260_t *memctl   = &immap->im_memctl;
+    volatile uchar        *ramaddr,
+                                  c = 0xff;
+    int i;
+
+#ifndef CFG_RAMBOOT
+    immap->im_siu_conf.sc_ppc_acr   = 0x00000002;
+    immap->im_siu_conf.sc_ppc_alrh  = 0x01267893;
+    immap->im_siu_conf.sc_tescr1    = 0x00004000;
+
+    /* init local sdram, bank 4 */
+    memctl->memc_lsrt               = 0x00000010;
+    memctl->memc_or4                = 0xFFC01480;
+    memctl->memc_br4                = 0x04001861;
+    memctl->memc_lsdmr              = 0x2886A522;
+    ramaddr                         = (uchar *)CFG_LSDRAM_BASE;
+    *ramaddr                        = c;
+    memctl->memc_lsdmr              = 0x0886A522;
+    for( i = 0; i < 8; i++ ) {
+        *ramaddr                    = c;
+    }
+    memctl->memc_lsdmr              = 0x1886A522;
+    *ramaddr                        = c;
+    memctl->memc_lsdmr              = 0x4086A522;
+    
+    /* init sdram dimm */
+    ramaddr                         = (uchar *)CFG_SDRAM_BASE;
+    memctl->memc_psrt               = 0x00000010;
+    immap->im_memctl.memc_or2       = 0xFF000CA0;
+    immap->im_memctl.memc_br2       = 0x00000041;
+    memctl->memc_psdmr              = 0x296EB452;
+    *ramaddr                        = c;
+    memctl->memc_psdmr              = 0x096EB452;
+    for (i = 0; i < 8; i++)
+        *ramaddr                    = c;
+
+    memctl->memc_psdmr              = 0x196EB452;
+    *ramaddr                        = c;
+    memctl->memc_psdmr              = 0x416EB452;
+    *ramaddr                        = c;
+#endif
+
+    /* return total ram size of simm */
+    return (16 * 1024 * 1024);
+}
+
+int checkboard(void)
+{
+    printf ("Motorola MPC8260ADS\n");
+
+    return 1;
+}
+
diff --git a/board/mpc8260ads/ppcboot.lds b/board/mpc8260ads/ppcboot.lds
new file mode 100644
index 0000000..671e70d
--- /dev/null
+++ b/board/mpc8260ads/ppcboot.lds
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/common/board.c b/common/board.c
index 3ddf665..a939c13 100644
--- a/common/board.c
+++ b/common/board.c
@@ -152,19 +152,20 @@ board_init_f (ulong bootflag)
     init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
 
 #if defined(CONFIG_BOARD_PRE_INIT) || \
-    defined(CONFIG_CPCI405)   || \
+    defined(CONFIG_ADCIOP)    || \
     defined(CONFIG_AR405)     || \
     defined(CONFIG_CANBT)     || \
-    defined(CONFIG_WALNUT405) || \
-    defined(CONFIG_PIP405)    || \
+    defined(CONFIG_CPCI405)   || \
     defined(CONFIG_CPCIISER4) || \
-    defined(CONFIG_OCRTC)     || \
-    defined(CONFIG_ADCIOP)    || \
+    defined(CONFIG_CU824)     || \
     defined(CONFIG_DASA_SIM)  || \
+    defined(CONFIG_EVB64260)  || \
     defined(CONFIG_LWMON)     || \
+    defined(CONFIG_MPC8260ADS)|| \
+    defined(CONFIG_OCRTC)     || \
+    defined(CONFIG_PIP405)    || \
     defined(CONFIG_RPXSUPER)  || \
-    defined(CONFIG_CU824)     || \
-    defined(CONFIG_EVB64260)
+    defined(CONFIG_WALNUT405)
     board_pre_init();        /* very early board init code (fpga boot, etc.) */
 #endif
 
@@ -620,14 +621,15 @@ void    board_init_r  (bd_t *bd, ulong dest_addr)
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
-    defined(CONFIG_SPD823TS)	|| \
-    defined(CONFIG_IVMS8)	|| \
-    defined(CONFIG_IVML24)	|| \
+    defined(CONFIG_CCM)		|| \
     defined(CONFIG_IP860)	|| \
+    defined(CONFIG_IVML24)	|| \
+    defined(CONFIG_IVMS8)	|| \
     defined(CONFIG_LWMON)	|| \
+    defined(CONFIG_MPC8260ADS)	|| \
     defined(CONFIG_PCU_E)	|| \
-    defined(CONFIG_CCM)		|| \
-    defined(CONFIG_RPXSUPER)	)
+    defined(CONFIG_RPXSUPER)	|| \
+    defined(CONFIG_SPD823TS)	)
 
 # if defined(CONFIG_WATCHDOG)
     watchdog_reset ();
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 0abce3f..711b341 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -479,6 +479,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[],
 	}
 
 #ifdef DEBUG
+	do_bdinfo (NULL, kbd, 0, 0, NULL);
+
 	printf ("## Transferring control to Linux (at address %08lx) ...\n",
 		(ulong)kernel);
 #endif
diff --git a/cpu/mpc8240/start.S b/cpu/mpc8240/start.S
index 7b40bc2..89af4ea 100644
--- a/cpu/mpc8240/start.S
+++ b/cpu/mpc8240/start.S
@@ -148,10 +148,12 @@ in_flash:
 	 */
 	lis	r1, (CFG_MEMTEST_END - 0x3000)@h
 	ori	r1, r1, (CFG_MEMTEST_END - 0x3000)@l
+
+#ifndef CONFIG_CU824
 	li	r0, 0			/* Make room for stack frame header and	*/
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
-
+#endif
 
 	/* let the C-code set up the rest					*/
 	/*									*/
@@ -163,6 +165,44 @@ in_flash:
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
 
+		/* Enable MMU.
+		 */
+	mfmsr	r3
+	ori	r3, r3, (MSR_IR | MSR_DR)
+	mtmsr	r3
+
+		/* Enable and invalidate data cache.
+		 */
+	mfspr	r3, HID0
+	mr	r2, r3
+	ori	r3, r3, HID0_DCE | HID0_DCI
+	ori	r2, r2, HID0_DCE
+	sync
+	mtspr	HID0, r3
+	mtspr	HID0, r2
+	sync
+
+		/* Allocate Initial RAM in data cache.
+		 */
+	lis	r3, CFG_INIT_RAM_ADDR@h
+	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+	li	r2, 128
+	mtctr	r2
+1:
+	dcbz	r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
+
+		/* Lock way0 in data cache.
+		 */
+	mfspr	r3, 1011
+	lis	r2, 0xffff
+	ori	r2, r2, 0xff1f
+	and	r3, r3, r2
+	ori	r3, r3, 0x0080
+	sync
+	mtspr   1011, r3
+
 	mr	r3, r21
 	/* r3: BOOTFLAG */
 	bl	board_init_f	/* run 1st part of board init code (from Flash) */
diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c
index bab3ff9..3167865 100644
--- a/cpu/mpc8260/ether_fcc.c
+++ b/cpu/mpc8260/ether_fcc.c
@@ -48,12 +48,16 @@
 
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET)
 
+/*---------------------------------------------------------------------*/
+/*---------------------------------------------------------------------*/
 #if (CONFIG_ETHER_INDEX == 1)
 
 #define PROFF_ENET		PROFF_FCC1
 #define CPM_CR_ENET_SBLOCK	CPM_CR_FCC1_SBLOCK
 #define CPM_CR_ENET_SBLOCK	CPM_CR_FCC1_SBLOCK
 #define CPM_CR_ENET_PAGE	CPM_CR_FCC1_PAGE
+
+/*******  HYMOD  *******************************************************/
 #if defined(CONFIG_HYMOD)
 /*
  * Attention: this is board-specific
@@ -66,10 +70,8 @@
 #define CMXFCR_VALUE		(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
 #define CPMFCR_RAMTYPE		0
 #define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-#endif
-#if defined(CONFIG_RPXSUPER)
-#error "on RPX Super ethernet must be FCC3"
-#endif
+#endif	/* CONFIG_HYMOD */
+/*******  PM826  *******************************************************/
 #if defined(CONFIG_PM826)
 /* 
  * Attention: this is board-specific
@@ -82,26 +84,49 @@
 #define CMXFCR_VALUE		(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 #define CPMFCR_RAMTYPE		0
 #define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+#endif	/* CONFIG_PM826 */
+/*******  RPXSUPER  ****************************************************/
+#if defined(CONFIG_RPXSUPER)
+#error "on RPX Super ethernet must be FCC3"
 #endif
+
+/*---------------------------------------------------------------------*/
+/*---------------------------------------------------------------------*/
 #elif (CONFIG_ETHER_INDEX == 2)
 
 #define PROFF_ENET		PROFF_FCC2
 #define CPM_CR_ENET_SBLOCK	CPM_CR_FCC2_SBLOCK
 #define CPM_CR_ENET_PAGE	CPM_CR_FCC2_PAGE
-#if defined(CONFIG_RSD_PROTO)
+/*******  HYMOD  *******************************************************/
+#if defined(CONFIG_HYMOD)
 /*
  * Attention: this is board-specific
  * - Rx-CLK is CLK13
  * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
+#define CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+#define CMXFCR_VALUE		(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+#define CPMFCR_RAMTYPE		0
+#define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+#endif	/* CONFIG_HYMOD */
+/*******  MPC8260ADS  **************************************************/
+#if defined(CONFIG_MPC8260ADS)
+/*
+ * Attention: this is board-specific
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Half duplex
+ */
 #define CMXFCR_MASK		(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 #define CMXFCR_VALUE		(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#define CPMFCR_RAMTYPE		(0)
-#define FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-#if defined(CONFIG_SBC8260)
+#define CPMFCR_RAMTYPE		0
+#define FCC_PSMR		0
+#endif	/* CONFIG_MPC8260ADS */
+/*******  RSD_PROTO  ***************************************************/
+#if defined(CONFIG_RSD_PROTO)
 /*
  * Attention: this is board-specific
  * - Rx-CLK is CLK13
@@ -109,27 +134,30 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-#define CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-#define CMXFCR_VALUE		(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-#define CPMFCR_RAMTYPE		0
+#define CMXFCR_MASK		(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CMXFCR_VALUE		(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CPMFCR_RAMTYPE		(0)
 #define FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-#if defined(CONFIG_HYMOD)
+#endif	/* CONFIG_RSD_PROTO */
+/*******  RPXSUPER  ****************************************************/
+#if defined(CONFIG_RPXSUPER)
+#error "on RPX Super ethernet must be FCC3"
+#endif	/* CONFIG_RPXSUPER */
+/*******  SBC8260  *****************************************************/
+#if defined(CONFIG_SBC8260)
 /*
  * Attention: this is board-specific
  * - Rx-CLK is CLK13
  * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
 #define CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 #define CMXFCR_VALUE		(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 #define CPMFCR_RAMTYPE		0
-#define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-#endif
-#if defined(CONFIG_RPXSUPER)
-#error "on RPX Super ethernet must be FCC3"
-#endif
+#define FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif	/* CONFIG_SBC8260 */
+/*******  TQM8260  *****************************************************/
 #if defined(CONFIG_TQM8260)
 /* 
  * Attention: this is board-specific
@@ -142,13 +170,16 @@
 #define CMXFCR_VALUE		(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 #define CPMFCR_RAMTYPE		0
 #define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-#endif
+#endif	/* CONFIG_TQM8260 */
 
+/*---------------------------------------------------------------------*/
+/*---------------------------------------------------------------------*/
 #elif (CONFIG_ETHER_INDEX == 3)
 
 #define PROFF_ENET		PROFF_FCC3
 #define CPM_CR_ENET_SBLOCK	CPM_CR_FCC3_SBLOCK
 #define CPM_CR_ENET_PAGE	CPM_CR_FCC3_PAGE
+/*******  HYMOD  *******************************************************/
 #if defined(CONFIG_HYMOD)
 /*
  * Attention: this is board-specific
@@ -161,7 +192,8 @@
 #define CMXFCR_VALUE		(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 #define CPMFCR_RAMTYPE		0
 #define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-#endif
+#endif	/* CONFIG_HYMOD */
+/*******  RPXSUPER  ****************************************************/
 #if defined(CONFIG_RPXSUPER)
 /*
  * Attention: this is board-specific
@@ -175,11 +207,13 @@
 #define CPMFCR_RAMTYPE		0
 //#define FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 #define FCC_PSMR		0
-#endif
+#endif	/* CONFIG_RPXSUPER */
 
+/*---------------------------------------------------------------------*/
 #else
 #error "FCC Ethernet not correctly defined"
 #endif
+/*---------------------------------------------------------------------*/
 
 /* Maximum input DMA size.  Must be a should(?) be a multiple of 4. */
 #define PKT_MAXDMA_SIZE         1520
diff --git a/include/config_CU824.h b/include/config_CU824.h
index d34952a..d0eda9f 100644
--- a/include/config_CU824.h
+++ b/include/config_CU824.h
@@ -97,9 +97,9 @@
 #define CFG_MEMTEST_START   0x00004000	/* memtest works on      */
 #define CFG_MEMTEST_END     0x02000000	/* 0 ... 32 MB in DRAM   */
 
-	/* Total amount of RAM.
+	/* Maximum amount of RAM.
 	 */
-#define CFG_RAM_SIZE        0x04000000
+#define CFG_MAX_RAM_SIZE    0x10000000
 
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
@@ -117,9 +117,9 @@
 	 */
 #define CFG_INIT_DATA_SIZE    128
 
-#define CONFIG_PRAM           CFG_INIT_DATA_SIZE
-#define CFG_INIT_RAM_ADDR     (CFG_RAM_SIZE - CFG_INIT_DATA_SIZE)
-#define CFG_INIT_DATA_OFFSET  0
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_INIT_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 
 
 /*
@@ -173,7 +173,7 @@
  */
 
 #define CFG_BANK0_START     0x00000000
-#define CFG_BANK0_END       (CFG_RAM_SIZE - 1)
+#define CFG_BANK0_END       (CFG_MAX_RAM_SIZE - 1)
 #define CFG_BANK0_ENABLE    1
 #define CFG_BANK1_START     0x3ff00000
 #define CFG_BANK1_END       0x3fffffff
@@ -199,22 +199,26 @@
 
 #define CFG_ODCR            0xff
 
-#define CFG_IBAT0L  0
-#define CFG_IBAT0U  0
-#define CFG_IBAT1L  0
-#define CFG_IBAT1U  0
-#define CFG_IBAT2L  0
-#define CFG_IBAT2U  0
-#define CFG_IBAT3L  0
-#define CFG_IBAT3U  0
-#define CFG_DBAT0L  0
-#define CFG_DBAT0U  0
-#define CFG_DBAT1L  0
-#define CFG_DBAT1U  0
-#define CFG_DBAT2L  0
-#define CFG_DBAT2U  0
-#define CFG_DBAT3L  0
-#define CFG_DBAT3U  0
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xFE000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xFE000000 | BATU_BL_32M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/config_MPC8260ADS.h b/include/config_MPC8260ADS.h
new file mode 100644
index 0000000..852b4c5
--- /dev/null
+++ b/include/config_MPC8260ADS.h
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2001
+ * Stuart Hughes <stuarth@lineo.com>
+ * This file is based on similar values for other boards found in other
+ * ppcboot config files, and some that I found in the mpc8260ads manual.
+ * 
+ * Note: my board is a PILOT rev.
+ * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_MPC8260ADS	1	/* ...on motorola ads board	*/
+
+/* allow serial and ethaddr to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define	CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	2	/* which channel for ether	*/
+
+/* other options */
+#define CONFIG_I2C		1	/* To enable I2C support	*/
+
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+					CFG_CMD_BEDBUG	| \
+					CFG_CMD_DATE	| \
+					CFG_CMD_EEPROM	| \
+					CFG_CMD_FDC	| \
+					CFG_CMD_IDE	| \
+					CFG_CMD_KGDB	| \
+					CFG_CMD_MII	| \
+					CFG_CMD_PCI	| \
+					CFG_CMD_PCMCIA	| \
+					CFG_CMD_SCSI	) )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm 100000" /* autoboot command*/
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#undef CFG_CLKS_IN_HZ			/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE          0xff800000
+#define FLASH_BASE              0xff800000
+#define CFG_MAX_FLASH_BANKS     1   /* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT      32  /* max num of sects on one chip */
+#define CFG_FLASH_SIZE          8
+#define CFG_FLASH_ERASE_TOUT    8000 /* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT    5    /* Timeout for Flash Write (in ms)    */
+
+/* this is stuff came out of the Motorola docs */
+#define CFG_IMMR            0x04700000
+#define CFG_BCSR            0x04500000
+#define CFG_SDRAM_BASE      0x00000000
+#define CFG_LSDRAM_BASE     0x04000000
+
+#define RS232EN_1 0x02000002
+#define RS232EN_2 0x01000001
+#define FETHIEN   0x08000008
+#define FETH_RST  0x04000004
+
+#define CFG_INIT_RAM_ADDR   CFG_IMMR
+#define CFG_INIT_RAM_END    0x4000  /* End of used area in DPRAM    */
+#define CFG_INIT_DATA_SIZE  128  /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_INIT_DATA_OFFSET
+
+
+/* 0x0EA28205 */
+#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
+                            ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
+                            ( HRCW_BMS | HRCW_APPC10 )                      |\
+                            ( HRCW_MODCK_H0101 )                             \
+                        )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM   0x02    /* Software reboot                   */
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN     (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN      (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ       (8 << 20)       /* Initial Memory map for Linux */
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH  1
+#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE  0x40000
+#else
+#  define CFG_ENV_IS_IN_NVRAM  1
+#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE         0x200
+#endif /* CFG_RAMBOOT */
+
+
+#define CFG_CACHELINE_SIZE  32      /* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
+#endif
+
+
+#define CFG_HID0_INIT  0
+#define CFG_HID0_FINAL  (HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CFG_HID2            0
+
+#define CFG_SYPCR           0xFFFFFFC3
+#define CFG_BCR             0x100C0000
+#define CFG_SIUMCR          0x0A200000
+#define CFG_SCCR            0x00000000
+#define CFG_BR0_PRELIM      0xFF801801
+#define CFG_OR0_PRELIM      0xFF800836
+#define CFG_BR1_PRELIM      0x04501801
+#define CFG_OR1_PRELIM      0xFFFF8010
+
+#define CFG_RMR             0
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR        0
+#define CFG_PSDMR       0x016EB452
+#define CFG_MPTPR       0x00001900
+#define CFG_PSRT        0x00000021
+
+#endif	/* __CONFIG_H */
diff --git a/include/flash.h b/include/flash.h
index 34b1810..9917aae 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -65,7 +65,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
 #define FLAG_PROTECT_CLEAR	0x02
 
 /*-----------------------------------------------------------------------
- * Device IDs for AMD and Fujitsu FLASH
+ * Device IDs
  */
 
 #define AMD_MANUFACT	0x00010001	/* AMD     manuf. ID in D23..D16, D7..D0 */
@@ -135,7 +135,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
 #define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
 #define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
 #define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
-#define INTEL_ID_28F320C3		0x88C588C5	/*	4MB , 8 8KB + 63 64KB bbt*/
+#define INTEL_ID_28F320C3   0x88C588C5	/*   4MB , 8 8KB + 63 64KB bbt		*/
 
 #define INTEL_ID_28F320JA3  0x00160016	/*  32M = 128K x  32			*/
 #define INTEL_ID_28F640JA3  0x00170017	/*  64M = 128K x  64			*/
@@ -144,6 +144,12 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
 #define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
 #define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
 
+/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
+#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
+					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
+
 /*-----------------------------------------------------------------------
  * Internal FLASH identification codes
  *
@@ -210,6 +216,8 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
 #define FLASH_28F160C3B	0x0091		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
 #define FLASH_28F160F3B	0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
 
+#define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM )	*/
+
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 
 
@@ -222,6 +230,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
 #define FLASH_MAN_STM	0x00200000
 #define FLASH_MAN_INTEL	0x00300000
 #define FLASH_MAN_MT	0x00400000
+#define FLASH_MAN_SHARP	0x00500000
 
 
 #define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type   information	*/
diff --git a/include/mpc8240.h b/include/mpc8240.h
index 85c59c6..40e7dfa 100755
--- a/include/mpc8240.h
+++ b/include/mpc8240.h
@@ -383,7 +383,7 @@
 
 #define BATL_BRPN_MSK		0xfffe0000
 #define BATL_WIMG_MSK		0x00000078
-#ifndef CONFIG_MOUSSE
+#ifdef CONFIG_SANDPOINT
 /* The below defines are not correct, but are in use
  * for Sandpoint.
  */
@@ -396,7 +396,7 @@
 #define BATL_CACHEINHIBIT	0x00000020
 #define BATL_MEMCOHERENCE	0x00000010
 #define BATL_GUARDEDSTORAGE	0x00000008
-#endif /* CONFIG_MOUSSE */
+#endif /* CONFIG_SANDPOINT */
 #define BATL_PP_MSK		0x00000003
 #define BATL_PP_00		0x00000000 /* No access */
 #define BATL_PP_01		0x00000001 /* Read-only */
diff --git a/include/ppcboot.h b/include/ppcboot.h
index c21a29b..f4e1af0 100644
--- a/include/ppcboot.h
+++ b/include/ppcboot.h
@@ -222,6 +222,7 @@ void	misc_init_r   (bd_t *);
     defined(CONFIG_IVML24)	|| \
     defined(CONFIG_IP860)	|| \
     defined(CONFIG_LWMON)	|| \
+    defined(CONFIG_MPC8260ADS)	|| \
     defined(CONFIG_RPXSUPER)	|| \
     defined(CONFIG_PCU_E)	|| \
     defined(CONFIG_CCM)
@@ -297,9 +298,10 @@ void	load_sernum_ethaddr(bd_t *bd);
     defined(CONFIG_ADCIOP)	|| \
     defined(CONFIG_DASA_SIM)	|| \
     defined(CONFIG_LWMON)	|| \
-    defined(CONFIG_RPXSUPER) || \
-    defined(CONFIG_CU824)    || \
-    defined(CONFIG_EVB64260) || \
+    defined(CONFIG_MPC8260ADS)	|| \
+    defined(CONFIG_RPXSUPER)	|| \
+    defined(CONFIG_CU824)	|| \
+    defined(CONFIG_EVB64260)	|| \
     defined(CONFIG_BOARD_PRE_INIT)
 /* $(BOARD)/$(BOARD).c */
 int	board_pre_init (void);