From: Miquel Raynal Date: Fri, 13 Jun 2025 18:23:56 +0000 (+0200) Subject: arm64: dts: ti: k3-am62a7-sk: Describe the SPI NAND X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=9c1185a99811a173e3c126d664982f6744f80997;p=users%2Fjedix%2Flinux-maple.git arm64: dts: ti: k3-am62a7-sk: Describe the SPI NAND Describe the octal SPI NAND available on the low-power starter kit. The pinctrl configuration comes from TI fork. With the current mainline tree, we currently get the following performances: eraseblock write speed is 7507 KiB/s eraseblock read speed is 15802 KiB/s page write speed is 7551 KiB/s page read speed is 15609 KiB/s 2 page write speed is 7551 KiB/s 2 page read speed is 15609 KiB/s erase speed is 284444 KiB/s 2x multi-block erase speed is 512000 KiB/s Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20250613182356.1272642-1-miquel.raynal@bootlin.com Signed-off-by: Vignesh Raghavendra --- diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index b277590260149..3a8b452725260 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -876,3 +876,45 @@ &main_rti4 { status = "reserved"; }; + +&fss { + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + bootph-all; + }; +}; + +&main_pmx0 { + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; +};