From: Philippe Mathieu-Daudé Date: Fri, 13 Aug 2021 10:37:12 +0000 (+0200) Subject: target/mips: Document Loongson-3A CPU definitions X-Git-Tag: v6.2.0-rc0~134^2~15 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=98d207cf9c232e6ac451b2aba24baa007956f578;p=users%2Fdwmw2%2Fqemu.git target/mips: Document Loongson-3A CPU definitions Document the cores on which each Loongson-3A CPU is based (see commit af868995e1b, "target/mips: Add Loongson-3 CPU definition"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Message-Id: <20210813110149.1432692-2-f4bug@amsat.org> --- diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998c..c6ab3af190 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -805,7 +805,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A1000", + .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */ .CP0_PRid = 0x6305, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | @@ -835,7 +835,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A4000", /* GS464V-based */ + .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */ .CP0_PRid = 0x14C000, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |