From: wdenk Date: Fri, 28 Dec 2001 14:03:47 +0000 (+0000) Subject: Patch by Josh Huber, 19 Dec 2001 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=934ac4924b92b71a15d85d0333950c88c4a1c04c;p=users%2Frw%2Fppcboot.git Patch by Josh Huber, 19 Dec 2001 - Renamed cpu/mpc74xx to cpu/74xx_7xx, added support for various CPUs of those families. - Added support for stack-in-cache trick for both those cpus and the evb64260 board. - Replaced code for sizing memory on the evb64260 to auto-configure the SDRAM by reading the SPD chip w/i2c bus. - Added a fairly bare bones i2c driver to the evb64260 board - Added support for ECC memory to the evb64260 board - Initial support for the new eval boards (and the 64260A chip) --- diff --git a/CHANGELOG b/CHANGELOG index a2cf484..529d3aa 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,17 @@ To do: Modifications for 1.1.3: ====================================================================== +* Patch by Josh Huber, 19 Dec 2001 + - Renamed cpu/mpc74xx to cpu/74xx_7xx, added support for various + CPUs of those families. + - Added support for stack-in-cache trick for both those cpus and + the evb64260 board. + - Replaced code for sizing memory on the evb64260 to auto-configure + the SDRAM by reading the SPD chip w/i2c bus. + - Added a fairly bare bones i2c driver to the evb64260 board + - Added support for ECC memory to the evb64260 board + - Initial support for the new eval boards (and the 64260A chip) + * Patch by Oliver Brown, 17 Dec 2001 - accept CROSS_COMPILE setting from shell - add support for gw8260 board diff --git a/Makefile b/Makefile index 2ae3730..bc63377 100644 --- a/Makefile +++ b/Makefile @@ -628,7 +628,7 @@ TQM8260_L2_config: unconfig @echo "#include " >>include/config.h ######################################################################### -## MPC74xx Systems +## 74xx/7xx Systems ######################################################################### EVB64260_config: unconfig @@ -636,7 +636,7 @@ EVB64260_config: unconfig cd ./include ; \ echo "ARCH = ppc" > config.mk ; \ echo "BOARD = evb64260" >>config.mk ; \ - echo "CPU = mpc74xx" >>config.mk ; \ + echo "CPU = 74xx_7xx" >>config.mk ; \ echo "#include " >config.h ######################################################################### diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h new file mode 100644 index 0000000..d106ced --- /dev/null +++ b/board/evb64260/64260.h @@ -0,0 +1,31 @@ +#ifndef __64260_H__ +#define __64260_H__ + +/* CPU Configuration bits */ +#define CPU_CONF_ADDR_MISS_EN (1 << 8) +#define CPU_CONF_AACK_DELAY (1 << 11) +#define CPU_CONF_ENDIANESS (1 << 12) +#define CPU_CONF_PIPELINE (1 << 13) +#define CPU_CONF_TA_DELAY (1 << 15) +#define CPU_CONF_RD_OOO (1 << 16) +#define CPU_CONF_STOP_RETRY (1 << 17) +#define CPU_CONF_MULTI_DECODE (1 << 18) +#define CPU_CONF_DP_VALID (1 << 19) +#define CPU_CONF_PERR_PROP (1 << 22) +#define CPU_CONF_FAST_CLK (1 << 23) +#define CPU_CONF_AACK_DELAY_2 (1 << 25) +#define CPU_CONF_AP_VALID (1 << 26) +#define CPU_CONF_REMAP_WR_DIS (1 << 27) +#define CPU_CONF_CONF_SB_DIS (1 << 28) +#define CPU_CONF_IO_SB_DIS (1 << 29) +#define CPU_CONF_CLK_SYNC (1 << 30) + +/* CPU Master Control bits */ +#define CPU_MAST_CTL_ARB_EN (1 << 8) +#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) +#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) +#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) +#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) +#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) + +#endif /* __64260_H__ */ diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile index 884219f..3cd2191 100644 --- a/board/evb64260/Makefile +++ b/board/evb64260/Makefile @@ -25,9 +25,9 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -SOBJS = sdram_init.o +SOBJS = misc.o OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ - eth.o ns16550.o mpsc.o + eth.o ns16550.o mpsc.o i2c.o sdram_init.o $(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index 74f28ed..4620a8b 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -38,7 +38,7 @@ unsigned long pci_dram_offset = 0; char *eth_data; /* if you like verbose output, turn this on! */ -#undef DEBUG +#undef DEBUG /* calculate the offset to the desired ethernet registers */ /* the registers are offset by 0x400 for each port -- see the headers */ @@ -92,6 +92,8 @@ evb64260_eth0_poll(void) RDN_ETH0 ++; if (RDN_ETH0 == NR) {RDN_ETH0 = 0;} + sync(); + /* Start Rx*/ GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080); @@ -106,31 +108,14 @@ evb64260_eth0_transmit(unsigned int s, volatile char *p) { /* wait for tx to be ready */ while (eth0_tx_desc[(TDN_ETH0)].command_status & 0x80000000) ; - + GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF, (unsigned int)eth0_tx_desc); -#if 0 /* this is already done */ - /* Build Ethernet Header */ - /* Destination MAC is broadcast */ - eth0_tx_buffer[0 ] = d[0]; - eth0_tx_buffer[1 ] = d[1]; - eth0_tx_buffer[2 ] = d[2]; - eth0_tx_buffer[3 ] = d[3]; - eth0_tx_buffer[4 ] = d[4]; - eth0_tx_buffer[5 ] = d[5]; - /* Source MAC is as defined in eeprom parameters */ - eth0_tx_buffer[6 ] = evb64260_eth0_mac_addr[0]; - eth0_tx_buffer[7 ] = evb64260_eth0_mac_addr[1]; - eth0_tx_buffer[8 ] = evb64260_eth0_mac_addr[2]; - eth0_tx_buffer[9 ] = evb64260_eth0_mac_addr[3]; - eth0_tx_buffer[10] = evb64260_eth0_mac_addr[4]; - eth0_tx_buffer[11] = evb64260_eth0_mac_addr[5]; - /* Next is IP packet */ - eth0_tx_buffer[12] = (t & 0xff00) >> 8; - eth0_tx_buffer[13] = t & 0xff; +#ifdef DEBUG + printf("copying to tx_buffer [%p], length %x, desc = %p\n", + eth0_tx_buffer, s, eth0_tx_desc); #endif - memcpy(eth0_tx_buffer, (char *) p, s); eth0_tx_desc[(TDN_ETH0)].buff_pointer = eth0_tx_buffer; @@ -146,12 +131,7 @@ evb64260_eth0_transmit(unsigned int s, volatile char *p) eth0_tx_desc[(TDN_ETH0+1)%NT].command_status = 0x0003ffff; -/* - { - unsigned long tempo; - for (tempo=0;tempo<10;tempo++) {} - } -*/ + sync(); GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x01000000); @@ -187,7 +167,7 @@ evb64260_eth0_probe(bd_t *bis) GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, &temp); /* turn on autonegotiation */ - temp = temp | 0x00000081; + temp |= 0x00000081; GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, temp); GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + REG_OFF, @@ -229,6 +209,8 @@ evb64260_eth0_probe(bd_t *bis) ð0_rx_desc[(temp+1)%NR].buff_size_byte_count; } + sync(); + GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF, (unsigned int) eth0_tx_desc); GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + REG_OFF, @@ -244,10 +226,10 @@ evb64260_eth0_probe(bd_t *bis) (unsigned int)eth0_rx_desc,eth0_rx_desc[0].command_status); printf ("Descriptor dump:\n"); - printf ("%08x\n",eth0_rx_desc[0].command_status); - printf ("%08x\n",eth0_rx_desc[0].buff_size_byte_count); - printf ("%08x\n",(unsigned int)eth0_rx_desc[0].buff_pointer); - printf ("%08x\n\n",(unsigned int)eth0_rx_desc[0].next_desc); + printf ("cmd status: %08x\n",eth0_rx_desc[0].command_status); + printf ("byte_count: %08x\n",eth0_rx_desc[0].buff_size_byte_count); + printf ("buff_ptr: %08x\n",(unsigned int)eth0_rx_desc[0].buff_pointer); + printf ("next_desc: %08x\n\n",(unsigned int)eth0_rx_desc[0].next_desc); printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x0)); printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x4)); printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x8)); diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h index 2e820a0..b11a3c2 100644 --- a/board/evb64260/eth.h +++ b/board/evb64260/eth.h @@ -39,14 +39,14 @@ typedef struct eth0_tx_desc_struct { volatile struct eth0_tx_desc_struct * next_desc; /* Note - the following will not work for 64 bit addressing */ volatile unsigned char * buff_pointer; -} eth0_tx_desc_single; +} eth0_tx_desc_single __attribute__ ((packed)); typedef struct eth0_rx_desc_struct { volatile __u32 buff_size_byte_count; volatile __u32 command_status; volatile struct eth0_rx_desc_struct * next_desc; volatile unsigned char * buff_pointer; -} eth0_rx_desc_single; +} eth0_rx_desc_single __attribute__ ((packed)); #define NT 20 /* Number of Transmit buffers */ #define NR 20 /* Number of Receive buffers */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c index d0c2be4..e6ede83 100644 --- a/board/evb64260/evb64260.c +++ b/board/evb64260/evb64260.c @@ -26,22 +26,30 @@ */ #include -#include +#include <74xx_7xx.h> #include #include +#include #include #include "eth.h" #include "mpsc.h" +#include "i2c.h" +#include "64260.h" -#undef DEBUG +#undef DEBUG +#define MAP_PCI -/* ------------------------------------------------------------------------- */ +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif -static long int dram_size (long int *, long int); +/* ------------------------------------------------------------------------- */ /* this is the GT register space location where we want it to be */ -unsigned int INTERNAL_REG_BASE_ADDR = 0xf0000000; +unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; /* ------------------------------------------------------------------------- */ @@ -76,13 +84,9 @@ my_remap_gt_regs(u32 cur_loc, u32 new_loc) int board_pre_init(void) { - /* - * 0 - SRAM - * 1 - RTC - * 2 - UART - * 3 - Flash - * boot - BootCS - */ + ulong tmp; + uchar sram_boot = 0; + cpu_t cpu = get_cpu_type(); /* * set up the GT the way the kernel wants it @@ -93,11 +97,6 @@ board_pre_init(void) */ my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS); - memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDevice1Space(CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDevice2Space(CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDevice3Space(CFG_DEV3_SPACE, CFG_DEV3_SIZE); - /* mask all external interrupt sources */ GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0); GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); @@ -110,220 +109,207 @@ board_pre_init(void) GT_REG_WRITE(CPU_INT_2_MASK, 0); GT_REG_WRITE(CPU_INT_3_MASK, 0); - return 0; -} - -/* various things to do after relocation */ + /* now, onto the configuration */ + GT_REG_WRITE(SDRAM_CONFIGURATION, 0xd8e10200); -void -misc_init_r(bd_t *bd) -{ -#ifdef CONFIG_MPSC - mpsc_init2(); -#endif -} - -/* ------------------------------------------------------------------------- */ + /* ----- DEVICE BUS SETTINGS ------ */ -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ + /* + * 0 - SRAM + * 1 - RTC + * 2 - UART + * 3 - Flash + * boot - BootCS + */ -int -checkboard (void) -{ - int l_type = 0; + /* + * the dual 7450 module requires burst access to the boot + * device, so the serial rom copies the boot device to the + * on-board sram on the eval board, and updates the correct + * registers to boot from the sram. (device0) + */ + if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) + sram_boot = 1; - printf ("EVB64260\n"); + if (!sram_boot) + memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDevice1Space(CFG_DEV1_SPACE, CFG_DEV1_SIZE); + memoryMapDevice2Space(CFG_DEV2_SPACE, CFG_DEV2_SIZE); + memoryMapDevice3Space(CFG_DEV3_SPACE, CFG_DEV3_SIZE); - return (l_type); -} + /* configure device timing */ + if (!sram_boot) + GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); + GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); + + /* detect if we are booting from the 32 bit flash */ + if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { + /* 32 bit boot flash */ + GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR); + } else { + /* 8 bit boot flash */ + GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + } -/* ------------------------------------------------------------------------- */ + /* cpu configuration register */ + tmp = GTREGREAD(CPU_CONFIGURATION); -/* automatic memory sizing */ + /* set the AACK delay bit + * see Res#14 */ + tmp |= CPU_CONF_AACK_DELAY; -int -memory_map_bank(unsigned int bankNo, - unsigned int bankBase, - unsigned int bankLength) -{ -#ifdef DEBUG - if (bankLength > 0) { - printf("\nmapping bank %d at %08x - %08x", - bankNo, bankBase, bankBase + bankLength - 1); + if (cpu == CPU_750CX) { + tmp |= CPU_CONF_DP_VALID; + tmp &= ~CPU_CONF_AP_VALID; } else { - printf("\nunmapping bank %d", bankNo); + tmp |= CPU_CONF_DP_VALID; + tmp |= CPU_CONF_AP_VALID; } -#endif - switch(bankNo) { - case 0: - memoryMapBank0(bankBase, bankLength); - pci0MapMemoryBank0(bankBase, bankLength); - pci1MapMemoryBank0(bankBase, bankLength); - return(true); - break; - case 1: - memoryMapBank1(bankBase, bankLength); - pci0MapMemoryBank1(bankBase, bankLength); - pci1MapMemoryBank1(bankBase, bankLength); - return(true); - break; - case 2: - memoryMapBank2(bankBase, bankLength); - pci0MapMemoryBank2(bankBase, bankLength); - pci1MapMemoryBank2(bankBase, bankLength); - return(true); - break; - case 3: - memoryMapBank3(bankBase, bankLength); - pci0MapMemoryBank3(bankBase, bankLength); - pci1MapMemoryBank3(bankBase, bankLength); - return(true); - break; - default: - return(0); - } -} + /* this only works with the MPX bus */ + tmp &= ~CPU_CONF_RD_OOO; + tmp &= ~CPU_CONF_PIPELINE; + tmp |= CPU_CONF_TA_DELAY; -#define GB (1 << 29) + GT_REG_WRITE(CPU_CONFIGURATION, tmp); -long int -initdram(int board_type) -{ - ulong bank_no, realsize, total, check; + /* CPU master control register */ + tmp = GTREGREAD(CPU_MASTER_CONTROL); -#ifdef DEBUG - int type; + tmp |= CPU_MAST_CTL_ARB_EN; - type = GTREGREAD(0x810); - printf("\n\nBank 0/1 width: %d\n", type); - type = GTREGREAD(0x814); - printf("Bank 1/2 width: %d\n", type); -#endif - memory_map_bank(0, 0, GB); - memory_map_bank(1, 0, 0); - memory_map_bank(2, 0, 0); - memory_map_bank(3, 0, 0); + if ((cpu == CPU_7400) || + (cpu == CPU_7410) || + (cpu == CPU_7450)) { - realsize = total = 0; - check = GB; - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { - if ((total + check) > CFG_GT_REGS) - check -= CFG_GT_REGS - (total+check); + tmp |= CPU_MAST_CTL_CLEAN_BLK; + tmp |= CPU_MAST_CTL_FLUSH_BLK; - memory_map_bank(bank_no, total, check); - realsize = dram_size((long int *)total, check); + } else { + /* cleanblock must be cleared for CPUs + * that do not support this command + * see Res#1 */ + tmp &= ~CPU_MAST_CTL_CLEAN_BLK; + tmp &= ~CPU_MAST_CTL_FLUSH_BLK; + } - /* XXX UGLY HACK XXX */ - /* todo: figure out why dram_size is returning >0 - when there is no memory there [josh]*/ - if (realsize < 10) - realsize = 0; + GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); - memory_map_bank(bank_no, total, realsize); + /* PCI interface settings */ + GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); + GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); + GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); + GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - total += realsize; - } + /* MPP setup */ + GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0); + GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1); + GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2); + GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3); -#ifdef DEBUG - puts("\n"); -#endif + /* XXX */ + GT_REG_WRITE(GPP_LEVEL_CONTROL, 0x000002c6); + GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x00000102); - return(total); + return 0; } -/* ------------------------------------------------------------------------- */ +/* various things to do after relocation */ -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int -dram_size(long int *base, long int maxsize) +void +misc_init_r(bd_t *bd) { - volatile long int *addr; - long int cnt, val; - - for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ +#ifdef CONFIG_MPSC + mpsc_init2(); +#endif - *addr = ~cnt; - } +#if 0 + /* disable the dcache and MMU */ + dcache_lock(); +// disable_addr_trans(); +// invalidate_bats(); +// dcache_disable(); +#endif +} - /* write 0 to base address */ - addr = base; - *addr = 0; +void +after_reloc(bd_t *bd, ulong dest_addr) +{ + /* check to see if we booted from the sram. If so, move things + * back to the way they should be. (we're running from main + * memory at this point now */ - /* check at base address */ - if ((val = *addr) != 0) { - return (0); + if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) { + memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceBootSpace(CFG_FLASH_BASE, _1M); } - for (cnt = 1; ; cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; + /* now, jump to the main ppcboot board init code */ + board_init_r(bd, dest_addr); - if (val != (~cnt)) { - return (cnt * sizeof(long)); - } - } /* NOTREACHED */ - - return 0; } -void -debug_led(int led, int mode) +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * + * right now, assume borad type. (there is just one...after all) + */ + +int +checkboard (void) { - volatile int *addr; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *)0x1c808000; - break; - - case 1: - addr = (int *)0x1c80c000; - break; - - case 2: - addr = (int *)0x1c810000; - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *)0x1c814000; - break; - - case 1: - addr = (int *)0x1c818000; - break; - - case 2: - addr = (int *)0x1c81c000; - break; - } - } + int l_type = 0; + + printf ("EVB64260\n"); - *addr = 0; + return (l_type); } +/* utility functions */ + void -perform_soft_reset() +debug_led(int led, int mode) { - unsigned int CS1baseAddress; - CS1baseAddress = memoryGetDeviceBaseAddress(DEVICE1); - WRITE_CHAR((CS1baseAddress | 0x20000),0); + volatile int *addr; + int dummy; + + if (mode == 1) { + switch (led) { + case 0: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000); + break; + + case 1: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000); + break; + + case 2: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000); + break; + } + } else if (mode == 0) { + switch (led) { + case 0: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000); + break; + + case 1: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000); + break; + + case 2: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000); + break; + } + } + + dummy = *addr; } #if (CONFIG_COMMANDS & CFG_CMD_NET) @@ -336,7 +322,14 @@ perform_soft_reset() int eth_init(bd_t *bis) { - return evb64260_eth0_probe(bis); + static short init_done = 0; + + if (!init_done) { + init_done = 1; + return evb64260_eth0_probe(bis); + } + + return 0; } int @@ -351,7 +344,7 @@ eth_send(volatile void *packet, int length) int eth_rx(void) { - return (evb64260_eth0_poll()); + return evb64260_eth0_poll(); } void diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c new file mode 100644 index 0000000..33d6331 --- /dev/null +++ b/board/evb64260/i2c.c @@ -0,0 +1,315 @@ +#include +#include +#include +#include +#include + +#define MAX_I2C_RETRYS 10 +#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ +#undef DEBUG_I2C + +#ifdef DEBUG_I2C +#define DP(x) x +#else +#define DP(x) +#endif + +/* Assuming that there is only one master on the bus (us) */ + +static void +i2c_init(void) +{ + unsigned int n, m, freq, margin, power; + unsigned int actualFreq, actualN, actualM; + unsigned int control, status; + unsigned int minMargin = 0xffffffff; + unsigned int tclk = 125000000; + unsigned int i2cFreq = 400000; + + DP(puts("i2c_init\n")); + + for(n = 0 ; n < 8 ; n++) + { + for(m = 0 ; m < 16 ; m++) + { + power = 2< freq) + margin = i2cFreq - freq; + else + margin = freq - i2cFreq; + if(margin < minMargin) + { + minMargin = margin; + actualFreq = freq; + actualN = n; + actualM = m; + } + } + } + + DP(puts("setup i2c bus\n")); + + /* Setup bus */ + + GT_REG_WRITE(I2C_SOFT_RESET, 0); + + DP(puts("udelay...\n")); + + udelay(I2C_DELAY); + + DP(puts("set baudrate\n")); + + GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); + GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); + + udelay(I2C_DELAY * 10); + + DP(puts("read control, baudrate\n")); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + GT_REG_READ(I2C_CONTROL, &control); +} + +static uchar +i2c_start(void) +{ + unsigned int control, status; + int count = 0; + + DP(puts("i2c_start\n")); + + /* Set the start bit */ + + GT_REG_READ(I2C_CONTROL, &control); + control |= (0x1 << 5); + GT_REG_WRITE(I2C_CONTROL, control); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + + count = 0; + while ((status & 0xff) != 0x08) { + udelay(I2C_DELAY); + if (count > 20) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return (status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + return (0); +} + +static uchar +i2c_select_device(uchar dev_addr, uchar read, int ten_bit) +{ + unsigned int status, data, bits = 7; + int count = 0; + + DP(puts("i2c_select_device\n")); + + /* Output slave address */ + + if (ten_bit) { + bits = 10; + } + + data = (dev_addr << 1); + /* set the read bit */ + data |= read; + GT_REG_WRITE(I2C_DATA, data); + /* assert the address */ + RESET_REG_BITS(I2C_CONTROL, BIT3); + + udelay(I2C_DELAY); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count = 0; + while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { + udelay(I2C_DELAY); + if (count > 20) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return(status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + if (bits == 10) { + printf("10 bit I2C addressing not yet implemented\n"); + return (0xff); + } + + return (0); +} + +static uchar +i2c_get_data(uchar* return_data, int len) { + + unsigned int data, status; + int count = 0; + + DP(puts("i2c_get_data\n")); + + while (len) { + + /* Get and return the data */ + + RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); + + udelay(I2C_DELAY * 5); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x50) { + udelay(I2C_DELAY); + if(count > 2) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return 0; + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_READ(I2C_DATA, &data); + len--; + *return_data = (uchar)data; + return_data++; + } + RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); + while ((status & 0xff) != 0x58) { + udelay(I2C_DELAY); + if(count > 200) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return (status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ + + return (0); +} + +static uchar +i2c_write_data(unsigned int data, int len) +{ + unsigned int status; + int count = 0; + + DP(puts("i2c_write_data\n")); + + if (len > 4) + return -1; + + while (len) { + /* Set and assert the data */ + + GT_REG_WRITE(I2C_DATA, (unsigned int)data); + RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); + + udelay(I2C_DELAY); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x28) { + udelay(I2C_DELAY); + if(count > 20) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return (status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + len--; + } + GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); + + udelay(I2C_DELAY * 10); + + return (0); +} + +static uchar +i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) +{ + uchar status; + + DP(puts("i2c_set_dev_offset\n")); + + status = i2c_select_device(dev_addr, 0, ten_bit); + if (status) { +#ifdef DEBUG_I2C + printf("Failed to select device setting offset: 0x%02x\n", + status); +#endif + return status; + } + + status = i2c_write_data(offset, 1); + if (status) { +#ifdef DEBUG_I2C + printf("Failed to write data: 0x%02x\n", status); +#endif + return status; + } + + return (0); +} + +uchar +i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, + int ten_bit) +{ + uchar status = 0; + + DP(puts("i2c_read\n")); + + i2c_init(); + + status = i2c_start(); + + if (status) { +#ifdef DEBUG_I2C + printf("Transaction start failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_set_dev_offset(dev_addr, 0, 0); + if (status) { +#ifdef DEBUG_I2C + printf("Failed to set offset: 0x%02x\n", status); +#endif + return status; + } + + i2c_init(); + + status = i2c_start(); + if (status) { +#ifdef DEBUG_I2C + printf("Transaction restart failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_select_device(dev_addr, 1, ten_bit); + if (status) { +#ifdef DEBUG_I2C + printf("Address not acknowledged: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_get_data(data, len); + if (status) { +#ifdef DEBUG_I2C + printf("Data not recieved: 0x%02x\n", status); +#endif + return status; + } + + return 0; +} diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h new file mode 100644 index 0000000..9c21992 --- /dev/null +++ b/board/evb64260/i2c.h @@ -0,0 +1,7 @@ +#ifndef __I2C_H__ +#define __I2C_H__ + +/* function declarations */ +uchar i2c_read(uchar, unsigned int, int, uchar*, int); + +#endif diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S new file mode 100644 index 0000000..31d42f8 --- /dev/null +++ b/board/evb64260/misc.S @@ -0,0 +1,149 @@ +#include +#include <74xx_7xx.h> +#include "version.h" + +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_ECC + /* Galileo specific asm code for initializing ECC */ + .globl board_relocate_rom +board_relocate_rom: + mflr r7 + /* update the location of the GT registers */ + lis r11, CFG_GT_REGS@h + /* if we're using ECC, we must use the DMA engine to copy ourselves */ + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + + mtlr r7 + blr + + .globl board_init_ecc +board_init_ecc: + mflr r7 + /* NOTE: r10 still contains the location we've been relocated to + * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + + /* now that we're running from ram, init the rest of main memory + * for ECC use */ + lis r8, CFG_MONITOR_LEN@h + ori r8, r8, CFG_MONITOR_LEN@l + + divw r3, r10, r8 + + /* set up the counter, and init the starting address */ + mtctr r3 + li r12, 0 + + /* bytes per transfer */ + mr r5, r8 +about_to_init_ecc: +1: mr r3, r12 + mr r4, r12 + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + add r12, r12, r8 + bdnz 1b + + mtlr r7 + blr + + /* r3: dest addr + * r4: source addr + * r5: byte count + * r11: gt regbase + * trashes: r6, r5 + */ +start_idma_transfer_0: + /* set the byte count, including the OWN bit */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_BYTE_COUNT + stwbrx r5, 0, (r6) + + /* set the source address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS + stwbrx r4, 0, (r6) + + /* set the dest address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS + stwbrx r3, 0, (r6) + + /* set the next record pointer */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0NEXT_RECORD_POINTER + stwbrx r5, 0, (r6) + + /* set the low control register */ + /* bit 9 is NON chained mode, bit 31 is new style descriptors. + bit 12 is channel enable */ + ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) + /* 15 shifted by 16 (oris) == bit 31 */ + oris r5, r5, (1 << 15) + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr + + /* this waits for the bytecount to return to zero, indicating + * that the trasfer is complete */ +wait_for_idma_0: + mr r5, r11 + lis r6, 0xff + ori r6, r6, 0xffff + ori r5, r5, CHANNEL0_DMA_BYTE_COUNT +1: lwbrx r4, 0, (r5) + and. r4, r4, r6 + bne 1b + + blr + + /* this turns off channel 0 of the idma engine */ +stop_idma_engine_0: + /* shut off the DMA engine */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr + +/* For use of the debug LEDs */ + .global led_on0 +led_on0: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0x8000 + stw r18, 0x0(r18) + sync + blr + + .global led_on1 +led_on1: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0xc000 + stw r18, 0x0(r18) + sync + blr + + .global led_on2 +led_on2: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x0000 + stw r18, 0x0(r18) + sync + blr +#endif diff --git a/board/evb64260/ppcboot.lds b/board/evb64260/ppcboot.lds index 943abeb..c915927 100644 --- a/board/evb64260/ppcboot.lds +++ b/board/evb64260/ppcboot.lds @@ -57,7 +57,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc74xx/start.o (.text) + cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/evb64260/sdram_init.S b/board/evb64260/sdram_init.S deleted file mode 100644 index 491a1a2..0000000 --- a/board/evb64260/sdram_init.S +++ /dev/null @@ -1,1010 +0,0 @@ -/* This file is copyright Galileo, I assume. - * it was lifted from the early init code in Dink32 - * Small modifications (c) 2001, Josh Huber */ - -#include -#include -#include "version.h" - -#include -#include - -/******************************************************************************* - -* -* sdramAutoConfig - SDRAM auto configuration. -* -* The SDRAM auto configuration feature is consist of two parts: -* 1) SDRAM width detection and bank parameters setting (Assembly code) -* 2) SDRAM address decoding and PCI address decoding (C code) -* This routine detects the width of the SDRAM installed in the board slots. -* This function detect all Sdram types: 16, 64, 128Mbit. -* The width of SDRAM slot 0 is stored in GT register 810. -* The width of SDRAM slot 1 is stored in GT register 814. -* The GT register 810 and 814, which is DMA register, are zero by default thus -* they are used for data storing. This SDRAM width information is retrieved -* by the C code part and used for the rest of the SDRAM initialization (PCI -* base address configuration registers and SDRAM decode registers) -* -*/ - -// ---------- GT defenitions -------------------------------------------- -#define INTERNAL_BASE 0x1400 -#define CPU_CONF 0x0 -#define SDRAM_CNFG 0x448 -#define SDRAM_PARA0 0x44c -#define SDRAM_PARA1 0x450 -#define SDRAM_PARA2 0x454 -#define SDRAM_PARA3 0x458 -#define BURST_MODE 0x478 -#define SDRAM_MODE 0x474 -#define GT_DEV0_PAR 0x45c -#define GT_DEV1_PAR 0x460 -#define GT_DEV2_PAR 0x464 -#define GT_DEV3_PAR 0x468 -#define GT_BOOT_PAR 0x46c -#define BOOTCS_P_LO 0x38 -#define BOOTCS_P_HI 0x40 -#define BOOTCS_D_LO 0x440 -#define BOOTCS_D_HI 0x444 -#define PCI1_MEM1_LO 0xb0 -#define PCI1_MEM1_HI 0xb8 -#define BOOT_BASE 0xfff0 -#define CPU_CONFIG 0x0 -#define TIMER_COUNT0 0x850 -#define T_C_CONTROL 0x864 -#define SCS1_0_LOW 0x008 -#define SCS1_0_HIGH 0x010 -#define SCS3_2_LOW 0x018 -#define SCS3_2_HIGH 0x020 -#define SCS1_LOW 0x208 -#define SCS1_HIGH 0x210 -#define SCS3_LOW 0x218 -#define SCS3_HIGH 0x220 - - -#define PCI_1_IO_LOW 0x90 -#define PCI_1_IO_HIGH 0x98 -#define PCI_1_MEM0_LOW 0xa0 -#define PCI_1_MEM0_HIGH 0xa8 -#define PCI_1_MEM1_LOW 0xb0 -#define PCI_1_MEM1_HIGH 0xb8 -#define PCI_0_TIME_OUT 0xC04 -#define PCI_1_TIME_OUT 0xC84 -#define PCI_0_BAR_EN 0xc3c -#define PCI_1_BAR_EN 0xcbc - -#define MPP_CNTRL0 0xf000 -#define MPP_CNTRL1 0xf004 -#define MPP_CNTRL2 0xf008 -#define MPP_CNTRL3 0xf00c -#define SER_PORTS_MUX 0xf010 -#define GPP_LEVEL_CNTRL 0xf110 - -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 -#define SDRAM_BANK0PARAMETERS 0x44C -#define SDRAM_BANK2PARAMETERS 0x454 -#define SDRAM_ADDRESS_DECODE 0x47C -#define SDRAM_OPERATION_MODE 0x474 -// ----------------------------------------------------------------------- - - /* r3: contains the NHR bit from HID0 - * we should use this to NOT reset the SDRAM on a soft reboot - * [josh] XXX */ - .globl gal_low_init -gal_low_init: - xor r0, r0, r0 - - /* SDRAM configuration - refresh_count=0x200, - phisical interleaving ensable, - virtual interleaving enable, - non staggered refresh, - standard SDRAM */ - mflr r9 /* save away link register */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_CNFG - addis r6, r0, 0xd8e1 - ori r6, r6, 0x0200 - lis r7, 0x0 -#ifdef REG - lis r7, 0x2 -#endif -#ifdef HVL - lis r7, 0x8 -#endif - or r6, r6, r7 - stwbrx r6, 0, (r5) // Store - sync - -_DIMM0: - - /* opening SCS[0] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS1_0_LOW /* r5 holds the SCS[0] Low decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - stwbrx r6, 0, (r5) /* ( 0x14000008 ) <= 0x0 */ - - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5,SCS_0_HIGH_DECODE_ADDRESS /* r5 holds the SCS[0] High decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - ori r6, r6, 0x00ff /* r6 <= 0xff */ - stwbrx r6, 0, (r5) /* ( 0x14000010 ) <= 0xff */ - - /* closing SCS[1] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_1_LOW_DECODE_ADDRESS /* r5 holds the SCS[1] Low decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - ori r6, r0, 0xffff /* r6 <= 0x0000.07ff */ - stwbrx r6, 0, (r5) /* ( 0x14000208 ) <= 0x7ff */ - - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5,SCS_1_HIGH_DECODE_ADDRESS /* r5 holds the SCS[1] High decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - stwbrx r6, 0, (r5) /* ( 0x14000210 ) <= 0x0 */ - - /* closing SCS[2] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_2_LOW_DECODE_ADDRESS /* r5 holds the SCS[2] Low decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - ori r6, r0, 0xffff /* r6 <= 0x0000.ffff */ - stwbrx r6, 0, (r5) /* ( 0x14000018 ) <= 0xffff */ - - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5,SCS_2_HIGH_DECODE_ADDRESS /* r5 holds the SCS[2] High decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - stwbrx r6, 0, (r5) /* ( 0x14000020 ) <= 0x0 */ - - /* closing SCS[3] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_3_LOW_DECODE_ADDRESS /* r5 holds the SCS[3] Low decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - ori r6, r0, 0xffff /* r6 <= 0x0000.0ffff */ - stwbrx r6, 0, (r5) /* ( 0x14000218 ) <= 0xffff */ - - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5,SCS_3_HIGH_DECODE_ADDRESS /* r5 holds the SCS[3] High decode Address */ - xor r6, r6, r6 /* r6 <= 0 */ - stwbrx r6, 0, (r5) /* ( 0x14000220 ) <= 0x0 */ - - - /* configurate bank0 to 256Mbit */ - sync - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_BANK0PARAMETERS /* r5 holds the Bank0 parametrs */ - lis r6, 0x0000 /* r6 <= 0x0 */ - ori r6, r6, 0xc000 /* r6 <= 0xc000 */ - stwbrx r6, 0, (r5) /* ( 0x1400044c ) <= 0x0000.c000 */ - - /* configuration Adrress decode 2 */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SDRAM_ADDRESS_DECODE /* r5 holds the Sdram Address Decode */ - xor r6, r6, r6 /* r6 <= 0x0 */ - ori r6, r6, 0x2 /* r6 <= 0x2 */ - stwbrx r6, 0, (r5) /* ( 0x1400047c ) <= 0x2 */ - - /* configuration Sdram Operation Mode */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SDRAM_OPERATION_MODE /* r5 holds the Sdram operation Mode */ - xor r6, r6, r6 /* r6 <= 0x0 */ - ori r6, r6, 0x3 /* r6 <= 0x3 */ - stwbrx r6, 0, (r5) /* ( 0x14000474 ) <= 0x3 */ - - /* A dummy writting */ - sync - xor r6, r6, r6 /* r6 <= 0x0 */ - stwbrx r6, 0, (r0) /* ( 0x0 ) <= 0x0 */ - - sync - xor r5, r5, r5 - addis r5, r0, INTERNAL_BASE - ori r5,r5, SDRAM_OPERATION_MODE /* r5 holds the Sdram operation Mode */ - xor r6, r6, r6 /* r6 <= 0 */ - stwbrx r6, 0, (r5) /* ( 0x14000474 ) <= 0x0 */ - - /* write to address 0x2000000 and check if 0x0 is beeing written to */ - xor r5,r5,r5 - xor r4,r4,r4 - addis r5, r0, 0x0 /* r5 <= 0x0000.0000 */ - addis r4, r0, 0x0 - ori r4, r4, 0x10 /* r4 <= 0x00000010 */ - -_1: stwbrx r0, 0, (r5) /* ( r5 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 - bne _1 /* If not equal, return. */ - - /* the address should activate Dadr12 */ - xor r5,r5,r5 - addis r5, r0, 0x0200 - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - stwbrx r6, 0, (r5) /* ( 0x0200.0000 ) <= 0x1111.1111 */ - xor r5,r5,r5 - xor r4,r4,r4 - ori r5, r0, 0x0010 /* r5 <= 0x0000.0010 */ - ori r4, r0, 0x1000 /* r4 <= 0x0000.0100 */ - lis r6, 0x2222 - ori r6, r6, 0x2222 /* r6 <= 0x2222.2222 */ - -_2: stwbrx r6, 0, (r5) /* ( r5 ) <= 0x2222.2222 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _2 /* If not equal, then return */ - sync - - /* check address 0x0 for duplicating. */ - xor r6,r6,r6 - addis r6, r0, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - lwbrx r4, 0, (r0) /* r4 <= ( 0x0000.0000)*/ - cmp 0, 1, r4, r6 /* if equal sduplication had occurred. */ - bne _256Mbit /* if not equal continue jump to _256Mbit */ - sync /* recommended after branch */ - -/* write to address 0x0000.1000 and checking duplication on adress 0 */ - - - xor r6, r6, r6 /* r6 <= 0x0 */ - xor r5, r5, r5 /* r5 <= 0x0 */ - xor r4, r4, r4 /* r4 <= 0x0 */ - ori r4, r4,0x10 /* r4 <= 0x00000010 */ - - -_3: stwbrx r6, 0, (r5) /* ( 0x00000000 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 - bne _3 /* If not equal, return. */ - - /* the address should activate Bank Select1 */ - - sync /* recommended after branch */ - lis r5, 0x0000 - ori r5, r5, 0x1000 /* r5 <= 0x0000.1000 */ - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - stwbrx r6, 0, (r5) /* ( 0x0000.1000 ) <= 0x1111.1111 */ - - sync - lis r5, 0x0 - ori r5, r5, 0x0010 /* r5 <= 0x0000.0010 */ - lis r4, 0x0 - ori r4, r4, 0x0100 /* r4 <= 0x0000.0100 */ - lis r6, 0x2222 - ori r6, r6, 0x2222 /* r6 <= 0x2222.2222 */ - -_4: stwbrx r6, 0, (r5) /* ( 0x00000010 ) <= 0x2222.2222 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _4 /* If not equal, then return */ - - /* check address 0x0 for duplicating. */ - - sync - xor r4, r4, r4 /* r4 <= 0x0 */ - xor r5, r5, r5 /* r5 <= 0x0 */ - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - lwbrx r4, 0, (r5) /* r4 <= ( 0x0000.0000) */ - cmp 0, 1, r4, r6 /* if equals duplication had occurred. */ - beq _16Mbit /* if equal jump to _16Mbit */ - sync - - /* Write to address 0x0800.0000 and check duplication on address0x00000000 */ - addis r5,r0,0x0 /* r5 <= 0x0 */ - addis r4,r0,0x0 - ori r4,r4,0x10 /* r4 <= 0x10 */ - -_5: stwbrx r0, 0, (r5) /* ( r5 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _5 /* If not equal, then return */ - sync - - /* The address should activate Dadr9 which on the column cycle*/ - /* is in active with 64 Mbit device */ - xor r5, r5, r5 - xor r6, r6, r6 - addis r5, r0, 0x0800 /* r5 <= 0x0800.0000 */ - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - stwbrx r6, 0, (r5) /* ( 0x0800.0000 ) <= 0x1111.1111 */ - xor r5,r5,r5 - xor r4,r4,r4 - ori r5, r0, 0x10 /* r5 <= 0x10 */ - ori r4, r0, 0x100 /* r4 <= 0x100 */ - lis r6, 0x2222 - ori r6, r6, 0x2222 /* r6 <= 0x2222.2222 */ - -_6: stwbrx r6, 0, (r5) /* ( r5 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _6 /* If not equal, then return */ - sync - - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - lwbrx r4, 0, (r0) /* r4 <= ( 0x0000.0000) */ - cmp 0, 1, r4, r6 /* if equals duplication had occurred. */ - beq _64Mbit /* if equal jump to _64Mbit */ - sync - b _128Mbit /* jump to _128Mbit */ - -_16Mbit: // if we got here a 16Mbit memory type is present at bank 0 (and maybe in bank 1) - lis r5, 0x1400 - ori r5, r5, 0x810 // r5 <= 0x1400.0810 - ori r6, r0, 16 // r6 <= 16 - stwbrx r6, 0, (r5) // ( 0x1400.0810 ) <= 16 - lis r5, 0x000f - ori r5, r0, 0x4000 // in _DIMM1: 0x44c <= 0x000f4000 - b _DIMM1 - -_64Mbit: - lis r5, 0x1400 - ori r5, r5, 0x810 // r5 <= 0x1400.0810 - ori r6, r0, 64 // r6 <= 64 - stwbrx r6, 0, (r5) // ( 0x1400.0810 ) <= 64 - lis r5, 0x000f - ori r5, r0, 0x8000 // in _DIMM1: 0x44c <= 0x000f8000 - b _DIMM1 - -_128Mbit: - lis r5, 0x1400 - ori r5, r5, 0x810 // r5 <= 0x1400.0810 - ori r6, r0, 128 // r6 <= 128 - stwbrx r6, 0, (r5) // ( 0x1400.0810 ) <= 128 - lis r5, 0x000f - ori r5, r0, 0x8000 // in _DIMM1: 0x44c <= 0x000f8000 - b _DIMM1 - -_256Mbit: - lis r5, 0x1400 - ori r5, r5, 0x810 // r5 <= 0x1400.0810 - ori r6, r0, 256 // r6 <= 256 - lis r5, 0x000f - stwbrx r6, 0, (r5) // ( 0x1400.0810 ) <= 128 - ori r5, r0, 0xc000 // in _DIMM1: 0x44c <= 0x000fc000 - - - // this section is the same as _DIMM0 it detect the type on dimm1 - -_DIMM1: - addis r4, r0, INTERNAL_BASE - ori r4, r4, SDRAM_BANK0PARAMETERS /* r4 holds the Bank0 parametrs register address */ - stwbrx r5, 0, (r4) /* update register 0x44c due to its type Bank0 */ - addi r4, r4, 0x4 - stwbrx r5, 0, (r4) /* update register 0x450 due to its type Bank1 */ - - /* Detect whether we have a 16,64,128 or 256 Mbit SDRAM on DIMM1 */ - - /* Extend bank2 to 0x10000000 and Close banks 0,1 and 3 */ - /* opening SCS[2] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_2_LOW_DECODE_ADDRESS /* r5 holds the SCS[2] Low decode Address */ - ori r6, r0, 0xff /* r6 <= 0xffff */ - stwbrx r0, 0, (r5) /* ( 0x14000018 ) <= 0x0 */ - addi r5, r5, 0x8 - stwbrx r6, 0, (r5) /* ( 0x14000020 ) <= 0xff */ - - /* closing SCS[0] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_0_LOW_DECODE_ADDRESS /* r5 holds the SCS[0] Low decode Address */ - ori r6, r0, 0xffff /* r6 <= 0xffff */ - stwbrx r6, 0, (r5) /* ( 0x14000008 ) <= 0xffff */ - addi r5, r5, 0x8 - stwbrx r0, 0, (r5) /* ( 0x14000010 ) <= 0x0 */ - - /* closing SCS[1] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_1_LOW_DECODE_ADDRESS /* r5 holds the SCS[1] Low decode Address */ - ori r6, r0, 0xffff /* r6 <= 0xffff */ - stwbrx r6, 0, (r5) /* ( 0x14000208 ) <= 0xffff */ - addi r5, r5, 0x8 - stwbrx r0, 0, (r5) /* ( 0x14000210 ) <= 0x0 */ - /* closing SCS[3] */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS_3_LOW_DECODE_ADDRESS /* r5 holds the SCS[3] Low decode Address */ - ori r6, r0, 0xffff /* r6 <= 0xffff */ - stwbrx r6, 0, (r5) /* ( 0x14000218 ) <= 0xffff */ - addi r5, r5, 0x8 - stwbrx r0, 0, (r5) /* ( 0x14000220 ) <= 0x0 */ - - /* configurate bank2 to 256Mbit */ - sync - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_BANK2PARAMETERS /* r5 holds the Bank2 parametrs */ - lis r6, 0x0000 /* r6 <= 0x0 */ - ori r6, r6, 0xc000 /* r6 <= 0xc000 */ - stwbrx r6, 0, (r5) /* ( 0x1400044c ) <= 0x0000.c000 */ - - /* configuration Address decode 2 */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SDRAM_ADDRESS_DECODE /* r5 holds the Sdram Address Decode */ - xor r6, r6, r6 /* r6 <= 0x0 */ - ori r6, r6, 0x2 /* r6 <= 0x2 */ - stwbrx r6, 0, (r5) /* ( 0x1400047c ) <= 0x2 */ - - /* write to address 0x0200.0000 and check if 0x0 is beeing written too */ - xor r5,r5,r5 - xor r4,r4,r4 - addis r5, r0, 0x0 /* r5 <= 0x0000.0000 */ - addis r4, r0, 0x0 - ori r4, r4, 0x10 /* r4 <= 0x00000010 */ - -_1_1: stwbrx r0, 0, (r5) /* ( r5 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 - bne _1_1 /* If not equal, return. */ - - /* the address should activate Dadr12 */ - xor r5,r5,r5 - addis r5, r0, 0x0200 - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - stwbrx r6, 0, (r5) /* ( 0x0200.0000 ) <= 0x1111.1111 */ - xor r5,r5,r5 - xor r4,r4,r4 - ori r5, r0, 0x0010 /* r5 <= 0x0000.0010 */ - ori r4, r0, 0x1000 /* r4 <= 0x0000.0100 */ - lis r6, 0x2222 - ori r6, r6, 0x2222 /* r6 <= 0x2222.2222 */ - -_2_1: stwbrx r6, 0, (r5) /* ( r5 ) <= 0x2222.2222 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _2_1 /* If not equal, then return */ - sync - - /* check address 0x0 for duplicating. */ - xor r6,r6,r6 - addis r6, r0, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - lwbrx r4, 0, (r0) /* r4 <= ( 0x0000.0000) */ - cmp 0, 1, r4, r6 /* if equal s duplication had occurred. */ - bne _256Mbit1 /* if not equal continue jump to _256Mbit1 */ - sync /* recommended after branch */ - - /* write to address 0x0000.1000 and checking duplication on adress 0 */ - xor r6, r6, r6 /* r6 <= 0x0 */ - xor r5, r5, r5 /* r5 <= 0x0 */ - xor r4, r4, r4 /* r4 <= 0x0 */ - ori r4, r4,0x10 /* r4 <= 0x00000010 */ - -_3_1: stwbrx r6, 0, (r5) /* ( 0x00000000 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 - bne _3_1 /* If not equal, return. */ - - /* the address should activate Bank Select1 */ - - sync /* recommended after branch */ - lis r5, 0x0000 - ori r5, r5, 0x1000 /* r5 <= 0x0000.1000 */ - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - stwbrx r6, 0, (r5) /* ( 0x0000.1000 ) <= 0x1111.1111 */ - - sync - lis r5, 0x0 - ori r5, r5, 0x0010 /* r5 <= 0x0000.0010 */ - lis r4, 0x0 - ori r4, r4, 0x0100 /* r4 <= 0x0000.0100 */ - lis r6, 0x2222 - ori r6, r6, 0x2222 /* r6 <= 0x2222.2222 */ - -_4_1: stwbrx r6, 0, (r5) /* ( 0x00000010 ) <= 0x2222.2222 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _4_1 /* If not equal, then return */ - - /* check address 0x0 for duplicating. */ - - sync - xor r4, r4, r4 /* r4 <= 0x0 */ - xor r5, r5, r5 /* r5 <= 0x0 */ - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - lwbrx r4, 0, (r5) /* r4 <= ( 0x0000.0000) */ - cmp 0, 1, r4, r6 /* if equals duplication had occurred. */ - beq _16Mbit1 /* if equal jump to _16Mbit1 */ - sync - - /* Write to address 0x0800.0000 and check duplication on address 0x00000000 */ - addis r5,r0,0x0 /* r5 <= 0x0 */ - addis r4,r0,0x0 - ori r4,r4,0x10 /* r4 <= 0x10 */ - -_5_1: stwbrx r0, 0, (r5) /* ( r5 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _5_1 /* If not equal, then return */ - sync - - /* The address should activate Dadr9 which on the column cycle */ - /* is in active with 64 Mbit device */ - xor r5, r5, r5 - xor r6, r6, r6 - addis r5, r0, 0x0800 /* r5 <= 0x0800.0000 */ - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - stwbrx r6, 0, (r5) /* ( 0x0800.0000 ) <= 0x1111.1111 */ - xor r5,r5,r5 - xor r4,r4,r4 - ori r5, r0, 0x10 /* r5 <= 0x10 */ - ori r4, r0, 0x100 /* r4 <= 0x100 */ - lis r6, 0x2222 - ori r6, r6, 0x2222 /* r6 <= 0x2222.2222 */ - -_6_1: stwbrx r6, 0, (r5) /* ( r5 ) <= 0x0 */ - addi r5,r5,0x4 /* r5 <= r5 + 4 */ - cmp 0, 1, r4, r5 /* Compare with default value */ - bne _6_1 /* If not equal, then return */ - sync - - lis r6, 0x1111 - ori r6, r6, 0x1111 /* r6 <= 0x1111.1111 */ - lwbrx r4, 0, (r0) /* r4 <= ( 0x0000.0000) */ - cmp 0, 1, r4, r6 /* if equals duplication had occurred. */ - beq _64Mbit1 /* if equal jump to _64Mbit1 */ - sync - b _128Mbit1 /* jump to _128Mbit1 */ - -_16Mbit1: // if we got here a 16Mbit memory type is present at bank 0 (and maybe in bank 1) - lis r5, 0x1400 - ori r5, r5, 0x814 // r5 <= 0x1400814 - ori r6, r0, 16 // r6 <= 16 - stwbrx r6, 0, (r5) // ( 0x1400.0814 ) <= 16 - lis r5, 0x000f - ori r4, r0, 0x4000 // in _init_Sdram: 0x44c <= 0x000f4000 - b _init_Sdram - -_64Mbit1: - lis r5, 0x1400 - ori r5, r5, 0x814 // r5 <= 0x1400814 - ori r6, r0, 64 // r6 <= 64 - stwbrx r6, 0, (r5) // ( 0x1400.0814 ) <= 64 - lis r5, 0x000f - ori r4, r0, 0x8000 // in _init_Sdram: 0x44c <= 0x000f8000 - b _init_Sdram - -_128Mbit1: - lis r5, 0x1400 - ori r5, r5, 0x814 // r5 <= 0x1400814 - ori r6, r0, 128 // r6 <= 128 - stwbrx r6, 0, (r5) // ( 0x1400.0814 ) <= 128 - lis r5, 0x000f - ori r4, r0, 0x8000 // in _init_Sdram: 0x44c <= 0x000f8000 - b _init_Sdram - -_256Mbit1: - lis r5, 0x1400 - ori r5, r5, 0x814 // r5 <= 0x1400814 - ori r6, r0, 256 // r6 <= 256 - stwbrx r6, 0, (r5) // ( 0x1400.0814 ) <= 256 - lis r5, 0x000f - ori r4, r0, 0xc000 // in _init_Sdram: 0x44c <= 0x000fc000 - -_init_Sdram: - lis r5, INTERNAL_BASE - ori r5, r5, 0x454 // r5 holds the Bank2 parametrs - stwbrx r4, 0, (r5) // update register 0x454 due to its type Bank2 - addi r5, r5, 0x4 - stwbrx r4, 0, (r5) // update register 0x458 due to its type Bank3 - - // now restoring all parametrs to deafults values. - // opening SCS[0] - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS1_0_LOW // r5 holds the SCS[1:0] Low decode Address - ori r6, r0, 0xff // r6 <= 0xff - stwbrx r0, 0, (r5) // ( 0x14000008 ) <= 0x0 - addi r5, r5, 0x8 - stwbrx r6, 0, (r5) // ( 0x14000010 ) <= 0xff - - // closing SCS[1] - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS1_LOW // r5 holds the SCS[1:0] Low decode Address - ori r6, r0, 0xffff // r6 <= 0xffff - stwbrx r6, 0, (r5) // ( 0x14000208 ) <= 0xffff - addi r5, r5, 0x8 - stwbrx r0, 0, (r5) // ( 0x14000210 ) <= 0x0 - - // closing SCS[2] - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS3_2_LOW // r5 holds the SCS[1:0] Low decode Address - ori r6, r0, 0xffff // r6 <= 0xffff - stwbrx r6, 0, (r5) // ( 0x14000008 ) <= 0xffff - addi r5, r5, 0x8 - stwbrx r0, 0, (r5) // ( 0x14000010 ) <= 0x0 - - // closing SCS[3] - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SCS3_LOW // r5 holds the SCS[1:0] Low decode Address - ori r6, r0, 0xffff // r6 <= 0xffff - stwbrx r6, 0, (r5) // ( 0x14000218 ) <= 0xffff - addi r5, r5, 0x8 - stwbrx r0, 0, (r5) // ( 0x14000220 ) <= 0x0 - -// ====================== Detecting memory, Until here. =========================== -#if 0 - /* SDRAM configuration - refresh_count=0x200, - phisical interleaving disable, - virtual interleaving disable, - staggered refresh, - standard SDRAM */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_CNFG - addis r6, r0, 0xd8e0 - ori r6, r6, 0xc200 - stwbrx r6, 0, (r5) // Store - sync - - - /* SDRAM parameters - Bank0 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_PARA0 - addis r6, r0, 0x0000 - ori r6, r6, 0x8000 - stwbrx r6, 0, (r5) // Store - sync - - /* SDRAM parameters - Bank1 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_PARA1 - addis r6, r0, 0x0000 - ori r6, r6, 0x8000 - stwbrx r6, 0, (r5) // Store - sync - - /* SDRAM parameters - Bank2 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_PARA2 - addis r6, r0, 0x0000 - ori r6, r6, 0x8000 - stwbrx r6, 0, (r5) // Store - sync - - /* SDRAM parameters - Bank3 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SDRAM_PARA3 - addis r6, r0, 0x0000 - ori r6, r6, 0x8000 - stwbrx r6, 0, (r5) // Store - sync - - /* configuration Sdram Operation Mode */ - sync - addis r5, r0, INTERNAL_BASE - ori r5,r5, SDRAM_MODE // r5 holds the Sdram operation Mode - xor r6, r6, r6 // r6 <= 0x0 - ori r6, r6, 0x3 // r6 <= 0x3 - stwbrx r6, 0, (r5) // ( 0x14000474 ) <= 0x3 - - /* A dummy write to bank0 */ - sync - xor r6, r6, r6 // r6 <= 0x0 - addis r6, r6, 0x0 // r6 <= 0x0 - stwbrx r0, 0, (r6) // ( 0x0 ) <= 0x0 - sync - /* A dummy write to bank1 */ - sync - xor r6, r6, r6 // r6 <= 0x0 - addis r6, r6, 0x0080 // r6 <= 0x0080.0000 - stwbrx r0, 0, (r6) // ( 0x80.0000 ) <= 0x0 - sync - /* A dummy write to bank2 */ - sync - xor r6, r6, r6 // r6 <= 0x0 - addis r6, r6, 0x0180 // r6 <= 0x0180.0000 - stwbrx r0, 0, (r6) // ( 0x180.0000 ) <= 0x0 - sync - /* A dummy write to bank3 */ - sync - xor r6, r6, r6 // r6 <= 0x0 - addis r6, r6, 0x0200 // r6 <= 0x0200.0000 - stwbrx r0, 0, (r6) // ( 0x200.0000 ) <= 0x0 - sync - - /* configuration Sdram Operation Mode */ - xor r5, r5, r5 - addis r5, r0, INTERNAL_BASE - ori r5,r5, SDRAM_MODE // r5 holds the Sdram operation Mode - xor r6, r6, r6 // r6 <= 0 - stwbrx r6, 0, (r5) // ( 0x14000474 ) <= 0x0 - - /* fource 64 bit device */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, 0x810 - addis r6, r0, 0x0 - ori r6, r6, 64 - stwbrx r6, 0, (r5) // Store - sync - - /* fource 64 bit device */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, 0x814 - addis r6, r0, 0x0 - ori r6, r6, 64 - stwbrx r6, 0, (r5) // Store - sync - -#endif // 0 - sync - -/* --\/-- GT device interface timing parameters --\/-- */ - - /* CS0 - 32 bit SRAM-Micron MT58L256L18P1-6ns */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_DEV0_PAR - addis r6, r0, 0xf020 - ori r6, r6, 0x51a9 - stwbrx r6, 0, (r5) // Store - sync - - /* CS1 - RTC-Dallas DS1501 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_DEV1_PAR - addis r6, r0, 0xffcf - ori r6, r6, 0xffff - stwbrx r6, 0, (r5) // Store - sync - - /* CS2 - UART-EXAR ST16C2552 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_DEV2_PAR - addis r6, r0, 0xf005 - ori r6, r6, 0x9bd4 - stwbrx r6, 0, (r5) // Store - sync - - /* CS3 and BootCS width detection */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_BOOT_PAR - lwbrx r6,0,r5 - andis. r6,r6,0x0030 - cmpi 0,0,r6,0x0 - bne boot_32_bit - - /* CS3 - 32bit Flash-Intel 28F640J3A-120ns */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_DEV3_PAR - addis r6, r0, 0xf4a8 - ori r6, r6, 0x241c - stwbrx r6, 0, (r5) // Store - sync - - /* BootCS - 8bit Flash-AMD AM29LV040B-120ns */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_BOOT_PAR - addis r6, r0, 0xf00b - ori r6, r6, 0x5e7c - stwbrx r6, 0, (r5) // Store - sync - b cont_init - sync - -#if 1 -boot_32_bit: - /* BootCS - 32bit Flash-Intel 28F640J3A-120ns */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_BOOT_PAR - addis r6, r0, 0xf4a8 - ori r6, r6, 0x241c - stwbrx r6, 0, (r5) // Store - sync - - /* CS3 - 8bit Flash-AMD AM29LV040B-120ns */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GT_DEV3_PAR - addis r6, r0, 0xf00b - ori r6, r6, 0x5e7c - stwbrx r6, 0, (r5) // Store - sync - -/* --/\-- GT devcie interface timing parameters --/\-- */ - -/* --\/------ GT CPU interface parameters --------\/-- */ -#define RdOOO -#define DP -#define AP -#define AACK_DELAY -#define Pipeline -#define TA_DELAY -cont_init: - /* CPU Configuration register */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, CPU_CONF - lwbrx r6, 0, (r5) -#ifdef RdOOO - lis r7, 0x0001 - or r6, r6, r7 // Read Out Of Order enable -#else - addis r7, r0, 0xfffe - ori r7, r7, 0xffff - and r6, r6, r7 -#endif -#ifdef DP - lis r7, 0x0008 - or r6, r6, r7 // Data Parity enable -#else - addis r7, r0, 0xfff7 - ori r7, r7, 0xffff - and r6, r6, r7 -#endif -#ifdef AP - lis r7, 0x0400 - or r6, r6, r7 // Address Parity enable -#else - addis r7, r0, 0xfbff - ori r7, r7, 0xffff - and r6, r6, r7 -#endif -#ifdef AACK_DELAY - ori r6, r6, 0x0800 // turn on AACK# delay -#else - addis r7, r0, 0xffff - ori r7, r7, 0xf7ff - and r6, r6, r7 -#endif -#ifdef Pipeline - ori r6, r6, 0x2000 // Pipeline enable -#endif -#ifdef TA_DELAY - ori r6, r6, 0x8000 // turn on TA# delay -#else - addis r7, r0, 0xffff - ori r7, r7, 0x7fff - and r6, r6, r7 -#endif - stwbrx r6, 0, (r5) // Store - sync - -#if 0 - /* -albert- */ - /* set up register 0x488 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, 0x488 - addis r6, r0, 0xD8E8 - ori r6, r6, 0x4200 - stwbrx r6, 0, (r5) -#endif - - /* CPU Master Control register */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, 0x160 - lwbrx r6, 0, (r5) - - mfspr r4, PVR - srawi r4,r4,16 - cmpi 0,0,r4, 0xc // 7400? - bne master_60x - sync - ori r6, r6, 0x3000 // - stwbrx r6, 0, (r5) // (0x14000160) <= (0x14000160) | 0x3000 - b cpu_interface_end - sync - -master_60x: - lis r8, 0xffff - ori r8, r8, 0xcfff - and r6, r6, r8 // - stwbrx r6, 0, (r5) // (0x14000160) <= (0x14000160) | 0xffffcfff - -cpu_interface_end: -/* --/\------ GT CPU interface parameters --------/\-- */ - -/* --\/------ GT PCI interface parameters --------\/-- */ - /* TimeOut 0/1 (PCI_0) */ - xor r5,r5,r5 - addis r5, r0, INTERNAL_BASE - ori r5, r5, PCI_0_TIME_OUT // r5 = 0x14000C04 - xor r6,r6,r6 - //addis r6, r0, 0x00ff - ori r6, r6, 0xffff // r6 = 0x00ffffff - stwbrx r6, 0, (r5) // (0x14000C04) <= 0x0000ffff - - /* TimeOut 0/1 (PCI_1) */ - xor r5,r5,r5 - addis r5, r0, INTERNAL_BASE - ori r5, r5, PCI_1_TIME_OUT // r5 = 0x14000C84 - xor r6,r6,r6 - //addis r6, r0, 0x00ff - ori r6, r6, 0xffff // r6 = 0x00ffffff - stwbrx r6, 0, (r5) // (0x14000C84) <= 0x0000ffff - - /* pci0 BAR enable */ - xor r5,r5,r5 - addis r5, r0, INTERNAL_BASE - ori r5, r5, PCI_0_BAR_EN // r5 = 0x14000c3c - xor r6,r6,r6 - addis r6, r0, 0xffff - ori r6, r6, 0xf800 // r6 = 0x0xfffff80e - stwbrx r6, 0, (r5) // (0x14000c3c) <= 0x0xfffff80e - - /* pci1 BAR enable */ - xor r5,r5,r5 - addis r5, r0, INTERNAL_BASE - ori r5, r5, PCI_1_BAR_EN // r5 = 0x14000cbc - xor r6,r6,r6 - addis r6, r0, 0xffff - ori r6, r6, 0xf800 // r6 = 0xfffff80e - stwbrx r6, 0, (r5) // (0x14000cbc) <= 0x0xfffff80e - -/* --/\------ GT PCI interface parameters --------/\-- */ - -/* --\/------ GT MPP interface parameters --------\/-- */ - /* MPP control0 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, MPP_CNTRL0 - addis r6, r0, 0x5354 - ori r6, r6, 0x1717 - stwbrx r6, 0, (r5) // Store - sync - - /* MPP control1 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, MPP_CNTRL1 - addis r6, r0, 0x4400 - ori r6, r6, 0x9911 - stwbrx r6, 0, (r5) // Store - sync - - /* MPP control2 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, MPP_CNTRL2 - addis r6, r0, 0x4009 - ori r6, r6, 0x1818 - stwbrx r6, 0, (r5) // Store - sync - - /* MPP control3 */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, MPP_CNTRL3 - addis r6, r0, 0x0009 - ori r6, r6, 0x0066 - stwbrx r6, 0, (r5) // Store - sync - - /* GPP Level Control - set the interrupt pins as active low */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, GPP_LEVEL_CNTRL - addis r6, r0, 0x0000 - ori r6, r6, 0x02c6 - stwbrx r6, 0, (r5) // Store - sync - - /* Serial Ports Multiplex - RMII */ - addis r5, r0, INTERNAL_BASE - ori r5, r5, SER_PORTS_MUX - addis r6, r0, 0x0000 - ori r6, r6, 0x0102 - stwbrx r6, 0, (r5) // Store - sync -/* --/\------ GT MPP interface parameters --------/\-- */ -#endif - mtlr r9 - blr diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c new file mode 100644 index 0000000..7160126 --- /dev/null +++ b/board/evb64260/sdram_init.c @@ -0,0 +1,490 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* sdram_init.c - automatic memory sizing */ + +#include +#include <74xx_7xx.h> +#include +#include +#include +#include + +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64260.h" + +#undef DEBUG +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +/* ------------------------------------------------------------------------- */ + +int +memory_map_bank(unsigned int bankNo, + unsigned int bankBase, + unsigned int bankLength) +{ +#ifdef DEBUG + if (bankLength > 0) { + printf("\nmapping bank %d at %08x - %08x", + bankNo, bankBase, bankBase + bankLength - 1); + } else { + printf("\nunmapping bank %d", bankNo); + } +#endif + + switch(bankNo) { + case 0: + memoryMapBank0(bankBase, bankLength); +#ifdef MAP_PCI + pci0MapMemoryBank0(bankBase, bankLength); + pci1MapMemoryBank0(bankBase, bankLength); +#endif + return(true); + break; + case 1: + memoryMapBank1(bankBase, bankLength); +#ifdef MAP_PCI + pci0MapMemoryBank1(bankBase, bankLength); + pci1MapMemoryBank1(bankBase, bankLength); +#endif + return(true); + break; + case 2: + memoryMapBank2(bankBase, bankLength); +#ifdef MAP_PCI + pci0MapMemoryBank2(bankBase, bankLength); + pci1MapMemoryBank2(bankBase, bankLength); +#endif + return(true); + break; + case 3: + memoryMapBank3(bankBase, bankLength); +#ifdef MAP_PCI + pci0MapMemoryBank3(bankBase, bankLength); + pci1MapMemoryBank3(bankBase, bankLength); +#endif + return(true); + break; + default: + return(0); + } +} + +#define GB (1 << 29) + +/* much of this code is based on (or is) the code in the pip405 port */ +/* thanks go to the authors of said port - Josh */ + +/* structure to store the relevant information about an sdram bank */ +typedef struct sdram_info { + uchar drb_size; + uchar registered, ecc; + uchar tpar; + uchar tras_clocks; + uchar burst_len; + uchar banks, slot; +} sdram_info_t; + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ + +static unsigned short +NS10to10PS(unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return(ns*100 + ns10*10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ + +static unsigned short +NSto10PS(unsigned char spd_byte) +{ + return(spd_byte*100); +} + +/* This code reads the SPD chip on the sdram and populates + * the array which is passed in with the relevant information */ +static int +check_dimm(uchar addr, uchar slot, sdram_info_t *info) +{ + int ret; + uchar rows, cols, sdram_banks, supp_cal, width, cal_val; + ulong memclk, tmemclk; + uchar trp_clocks, trcd_clocks; + uchar data[128]; + + memclk = get_bus_freq(0); + tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ + + DP(puts("before i2c read\n")); + + ret = i2c_read(addr, 0, 128, data, 0); + + DP(puts("after i2c read\n")); + + /* zero all the values */ + memset(info, 0, sizeof(*info)); + + if (ret) { + DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret)); + return 0; + } + + /* first, do some sanity checks */ + if (data[2] != 0x4) { + printf("Not SDRAM in slot %d\n", slot); + return 0; + } + + /* get various information */ + rows = data[3]; + cols = data[4]; + info->banks = data[5]; + sdram_banks = data[17]; + width = data[13] & 0x7f; + + DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); + + /* check if the memory is registered */ + if (data[21] & (BIT1 & BIT4)) + info->registered = 1; + +#ifdef CONFIG_ECC + /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ + info->ecc = (data[11] & 2) >> 1; +#endif + + /* bit 1 is CL2, bit 2 is CL3 */ + supp_cal = (data[18] & 0x6) >> 1; + + /* compute the relevant clock values */ + trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk; + trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk; + info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk; + + DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", + trp_clocks, trcd_clocks, info->tras_clocks)); + + /* try a CAS latency of 3 first... */ + cal_val = 0; + if (supp_cal & 3) { + if (NS10to10PS(data[9]) <= tmemclk) + cal_val = 3; + } + + /* then 2... */ + if (supp_cal & 2) { + if (NS10to10PS(data[23]) <= tmemclk) + cal_val = 2; + } + + DP(printf("cal_val = %d\n", cal_val)); + + /* bummer, did't work... */ + if (cal_val == 0) { + DP(printf("Couldn't find a good CAS latency\n")); + return 0; + } + + /* get the largest delay -- these values need to all be the same + * see Res#6 */ + info->tpar = cal_val; + if (trp_clocks > info->tpar) + info->tpar = trp_clocks; + if (trcd_clocks > info->tpar) + info->tpar = trcd_clocks; + + DP(printf("tpar set to: %d\n", info->tpar)); + + /* compute the module DRB size */ + info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M; + + /* find the burst len */ + info->burst_len = data[16] & 0xf; + if ((info->burst_len & 8) == 8) { + info->burst_len = 1; + } else if ((info->burst_len & 4) == 4) { + info->burst_len = 0; + } else + return 0; + + info->slot = slot; + + return 0; +} + +/* sets up the GT properly with information passed in */ +int +setup_sdram(sdram_info_t *info) +{ + ulong tmp, check; + ulong *addr = 0; + int i; + + /* sanity checking */ + if (! info->banks) { + printf("setup_sdram called with 0 banks\n"); + return 1; + } + + /* ---------------------------- */ + /* Program the GT with the discovered data */ + + /* bank parameters */ + tmp = 0; + + DP(printf("drb_size: %d\n", info->drb_size)); + switch (info->drb_size) { + case 1: + tmp |= (1 << 14); + break; + case 4: + case 8: + tmp |= (2 << 14); + break; + case 16: + case 32: + tmp |= (3 << 14); + break; + default: + printf("Error in dram size calculation\n"); + return 1; + } + + /* SDRAM bank parameters */ + /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ + DP(printf("setting up slot %d config with: %08lx\n", info->slot, tmp)); + GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); + GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); + + /* SDRAM configuration */ + tmp = GTREGREAD(SDRAM_CONFIGURATION); + + tmp |= (info->registered << 17); + + /* Use buffer 1 to return read data to the CPU + * See Res #12 */ + tmp |= (1 << 26); + + GT_REG_WRITE(SDRAM_CONFIGURATION, tmp); + + DP(printf("sdram_conf: %08x\n", GTREGREAD(SDRAM_CONFIGURATION))); + + /* SDRAM timing */ + DP(printf("setting timing parameters to: %d\n", info->tpar)); + + tmp = (((info->tpar == 3) ? 2 : 1) | + (((info->tpar == 3) ? 2 : 1) << 2) | + (((info->tpar == 3) ? 2 : 1) << 4) | + (info->tras_clocks << 8) | + (info->ecc << 13)); + + DP(printf("setting up sdram_timing with: %08lx\n", tmp)); + GT_REG_WRITE(SDRAM_TIMING, tmp); + + /* SDRAM address decode register */ + /* program this with the default value */ + GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2); + + DP(printf("SDRAM address decode: %08x\n", + GTREGREAD(SDRAM_ADDRESS_DECODE))); + + /* set the SDRAM configuration for each bank */ + for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { + DP(printf("\n*** Running a MRS cycle for bank %d ***\n", i)); + + /* map the bank */ + memory_map_bank(i, 0, GB/4); + + /* set SDRAM mode */ + GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3); + check = GTREGREAD(SDRAM_OPERATION_MODE); + + /* dummy write */ + *addr = 0; + + /* wait for the command to complete */ + while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0) + ; + + /* switch back to normal operation mode */ + GT_REG_WRITE(SDRAM_OPERATION_MODE, 0); + check = GTREGREAD(SDRAM_OPERATION_MODE); + + /* unmap the bank */ + memory_map_bank(i, 0, 0); + } + + return 0; +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +static long int +dram_size(long int *base, long int maxsize) +{ + volatile long int *addr; + long int cnt, val; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + *addr = 0xDEADBEEF; + + /* check at base address */ + if ((val = *addr) != 0xDEADBEEF) { + return 0; + } + + for (cnt = 1; ; cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + + if (val != (~cnt)) { + return (cnt * sizeof(long)); + } + } + /* NOTREACHED */ + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* ppcboot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int +initdram(int board_type) +{ + int s0 = 0, s1 = 0; + int checkbank[4] = { [0 ... 3] = 0 }; + ulong bank_no, realsize, total, check; + sdram_info_t dimm1, dimm2; + int nhr; + + /* first, use the SPD to get info about the SDRAM */ + + /* check the NHR bit and skip mem init if it's already done */ + nhr = get_hid0() & (1 << 16); + + if (nhr) { + printf("Skipping SDRAM setup due to NHR bit being set\n"); + } else { + /* DIMM0 */ + s0 = check_dimm(DIMM0_I2C_ADDR, 0, &dimm1); + + /* DIMM1 */ + s1 = check_dimm(DIMM1_I2C_ADDR, 1, &dimm2); + + memory_map_bank(0, 0, 0); + memory_map_bank(1, 0, 0); + memory_map_bank(2, 0, 0); + memory_map_bank(3, 0, 0); + + /* Now, program the GT with the correct values */ + if (dimm1.tpar > dimm2.tpar) + dimm2.tpar = dimm1.tpar; + else if(dimm2.tpar > dimm1.tpar) + dimm1.tpar = dimm2.tpar; + + if (dimm1.banks && setup_sdram(&dimm1)) { + printf("Setup for DIMM1 failed.\n"); + } + + if (dimm2.banks && setup_sdram(&dimm2)) { + printf("Setup for DIMM2 failed.\n"); + } + + /* set the NHR bit */ + set_hid0(get_hid0() | (1 << 16)); + } + /* next, size the SDRAM banks */ + + realsize = total = 0; + check = GB/4; + if (dimm1.banks > 0) checkbank[0] = 1; + if (dimm1.banks > 1) checkbank[1] = 1; + if (dimm1.banks > 2) + printf("Error, SPD claims DIMM1 has >2 banks\n"); + + if (dimm2.banks > 0) checkbank[2] = 1; + if (dimm2.banks > 1) checkbank[3] = 1; + if (dimm2.banks > 2) + printf("Error, SPD claims DIMM2 has >2 banks\n"); + + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + /* skip over banks that are not populated */ + if (! checkbank[bank_no]) + continue; + + if ((total + check) > CFG_GT_REGS) + check -= CFG_GT_REGS - (total+check); + + memory_map_bank(bank_no, total, check); + realsize = dram_size((long int *)total, check); + + if (realsize < 10) + realsize = 0; + + memory_map_bank(bank_no, total, realsize); + + total += realsize; + } + + if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) { + puts("[ECC] "); + } + + return(total); +} diff --git a/cpu/mpc74xx/Makefile b/cpu/74xx_7xx/Makefile similarity index 100% rename from cpu/mpc74xx/Makefile rename to cpu/74xx_7xx/Makefile diff --git a/cpu/mpc74xx/config.mk b/cpu/74xx_7xx/config.mk similarity index 93% rename from cpu/mpc74xx/config.mk rename to cpu/74xx_7xx/config.mk index e67ca44..7d55de2 100644 --- a/cpu/mpc74xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_74xx -ffixed-r2 -mstring +PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/cpu/mpc74xx/cpu.c b/cpu/74xx_7xx/cpu.c similarity index 73% rename from cpu/mpc74xx/cpu.c rename to cpu/74xx_7xx/cpu.c index 81b3217..19f9ef5 100644 --- a/cpu/mpc74xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -34,47 +34,91 @@ * * more modifications by * Josh Huber - * mostly removing functionality we don't need quite yet. + * added support for the 74xx series of cpus + * added support for the 7xx series of cpus + * made the code a little less hard-coded, and more auto-detectish */ #include -#include #include -#include +#include <74xx_7xx.h> #include -#if defined(CONFIG_74xx) -static int -check_CPU(long clock, uint pvr) +cpu_t +get_cpu_type(void) { + uint pvr = get_pvr(); + cpu_t type; + + type = CPU_UNKNOWN; + switch (PVR_VER(pvr)) { case 0x000c: - puts("MPC7400 "); -#ifdef CONFIG_ALTIVEC - puts("(altivec enabled) "); -#endif - printf("v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); + type = CPU_7400; + break; + case 0x0008: + type = CPU_750; + + if (((pvr >> 8) & 0xff) == 0x22) { + type = CPU_750CX; + } else if (((pvr >> 12) & 0xF) == 0x3) { + type = CPU_755; + } + break; + + case 0x800C: + type = CPU_7410; + break; + + case 0x8000: + type = CPU_7450; break; default: - puts("Unknown CPU -- configuration error!\n"); - return -1; break; } - return 0; + return type; } -#else -#error CPU undefined -#endif + /* ------------------------------------------------------------------------- */ int checkcpu(long clock) { - uint pvr = get_pvr(); + uint type = get_cpu_type(); + uint pvr = get_pvr(); + + switch (type) { + case CPU_750: + printf ("750 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); + return (0); + + case CPU_755: + printf ("755 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); + return (0); + + case CPU_750CX: + printf ("750CX(e) v2.%d\n", pvr & 0xf); + return (0); + + case CPU_7400: + printf ("MPC7400 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); + return (0); + + case CPU_7410: + printf ("MPC7410 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); + return (0); + + case CPU_7450: + printf ("MPC7450 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); + return (0); + + default: + printf("Unknown CPU -- PVR: 0x%08x\n", pvr); + return -1; + } - return check_CPU(clock, pvr); } /* these two functions are unimplemented currently [josh] */ diff --git a/cpu/mpc74xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c similarity index 78% rename from cpu/mpc74xx/cpu_init.c rename to cpu/74xx_7xx/cpu_init.c index c5c0cc1..8ac5721 100644 --- a/cpu/mpc74xx/cpu_init.c +++ b/cpu/74xx_7xx/cpu_init.c @@ -28,7 +28,22 @@ */ #include -#include +#include <74xx_7xx.h> + +__inline__ unsigned long +get_hid0(void) +{ + unsigned long msr; + + asm volatile("mfspr %0, 1008" : "=r" (msr) :); + return msr; +} + +__inline__ void +set_hid0(unsigned long msr) +{ + asm volatile("mtspr 1008, %0" : : "r" (msr)); +} /* * Breath some life into the CPU... @@ -39,10 +54,10 @@ void cpu_init_f (void) { - /* turn off debug leds */ - debug_led(0,0); - debug_led(1,0); - debug_led(2,0); + if (get_cpu_type() == CPU_7450) { + /* enable the timebase bit in HID0 */ + set_hid0(get_hid0() | 0x4000000); + } } /* diff --git a/cpu/mpc74xx/interrupts.c b/cpu/74xx_7xx/interrupts.c similarity index 99% rename from cpu/mpc74xx/interrupts.c rename to cpu/74xx_7xx/interrupts.c index b9b21f1..0da0ebf 100644 --- a/cpu/mpc74xx/interrupts.c +++ b/cpu/74xx_7xx/interrupts.c @@ -111,7 +111,7 @@ interrupt_init(bd_t *bd) #ifdef DEBUG puts("interrupt_init: setting actual decremter\n"); #endif - set_dec (decrementer_count); + set_dec (get_tbclk() / CFG_HZ); #ifdef DEBUG printf("interrupt_init: enabling interrupts (msr = %08x)\n", diff --git a/cpu/mpc74xx/kgdb.S b/cpu/74xx_7xx/kgdb.S similarity index 98% rename from cpu/mpc74xx/kgdb.S rename to cpu/74xx_7xx/kgdb.S index 9e28246..1978bdd 100644 --- a/cpu/mpc74xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -24,7 +24,7 @@ #include #include -#include +#include <74xx_7xx.h> #include "version.h" #include diff --git a/cpu/mpc74xx/speed.c b/cpu/74xx_7xx/speed.c similarity index 98% rename from cpu/mpc74xx/speed.c rename to cpu/74xx_7xx/speed.c index f47075f..03bdca5 100644 --- a/cpu/mpc74xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -22,7 +22,7 @@ */ #include -#include +#include <74xx_7xx.h> #include /* Access functions for the Machine State Register */ diff --git a/cpu/mpc74xx/start.S b/cpu/74xx_7xx/start.S similarity index 85% rename from cpu/mpc74xx/start.S rename to cpu/74xx_7xx/start.S index 1e61ff2..a99b46d 100644 --- a/cpu/mpc74xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -33,7 +33,7 @@ * jumped there, everything is ok. */ #include -#include +#include <74xx_7xx.h> #include "version.h" #include @@ -42,6 +42,8 @@ #include #include +#include + #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif @@ -82,14 +84,6 @@ version_string: .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" -#if 0 -/* this is used in the led on/off routines */ - .align 2 - .global temp_reg -temp_reg: - .long 0 -#endif - . = EXC_OFF_SYS_RESET .globl _start _start: @@ -205,17 +199,7 @@ boot_warm: sync mtmsr 0 - /* invalidate BATs */ - mtspr IBAT0U, r0 - mtspr IBAT1U, r0 - mtspr IBAT2U, r0 - mtspr IBAT3U, r0 - isync - mtspr DBAT0U, r0 - mtspr DBAT1U, r0 - mtspr DBAT2U, r0 - mtspr DBAT3U, r0 - isync + bl invalidate_bats #ifdef CFG_L2 /* init the L2 cache */ @@ -223,7 +207,7 @@ boot_warm: ori r3, r3, L2_INIT@l mtspr l2cr, r3 #endif -#ifdef CONFIG_ALTIVEC +#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) .long 0x7e00066c /* dssall instruction, gas doesn't have it yet */ /* ...for altivec, data stream stop all */ @@ -249,15 +233,6 @@ invl2: mtspr l2cr, r3 #endif - /* setup the bats */ - bl setup_bats - sync - -#if CFG_MMU - /*enable address translation */ - bl enable_addr_trans - sync -#endif /* * Calculate absolute address in FLASH and jump there *------------------------------------------------------*/ @@ -277,22 +252,44 @@ in_flash: /* sdram init, galileo init, etc */ /* r3: NHR bit from HID0 */ + /* setup the bats */ + bl setup_bats + + /* enable and invalidate the data cache */ + bl dcache_enable + + /* enable address translation */ + bl enable_addr_trans + + /* Allocate Initial RAM in data cache. + */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + li r2, 128 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b + +#if 0 mfspr r0, HID0 rlwinm r3, r0, 15, 31, 31 xor r4, r4, r4 lis r4, 0x2 or r0, r0, r4 mtspr HID0, r0 + li r0, 0 +#endif + /* set up the stack pointer in our newly created + * cache-ram (r1) */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET)@l - bl gal_low_init + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* set up r1 (SP) */ - addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - GET_GOT /* initialize GOT access */ /* run low-level CPU init code (from Flash) */ @@ -305,7 +302,23 @@ in_flash: bl board_init_f /* NOTREACHED */ - + + .globl invalidate_bats +invalidate_bats: + /* invalidate BATs */ + mtspr IBAT0U, r0 + mtspr IBAT1U, r0 + mtspr IBAT2U, r0 + mtspr IBAT3U, r0 + isync + mtspr DBAT0U, r0 + mtspr DBAT1U, r0 + mtspr DBAT2U, r0 + mtspr DBAT3U, r0 + isync + sync + blr + /* setup_bats - set them up to some initial state */ .globl setup_bats setup_bats: @@ -386,14 +399,14 @@ setup_bats: /* bats are done, now invalidate the TLBs */ addis r3, 0, 0x0000 - addis r5, 0, 0x4 /* upper bound of 0x0004000 for 7400 */ + addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ isync tlblp: tlbie r3 sync - addi r3, r3, 0x100 + addi r3, r3, 0x1000 cmp 0, 0, r3, r5 blt tlblp @@ -411,11 +424,14 @@ enable_addr_trans: .globl disable_addr_trans disable_addr_trans: /* disable address translation */ - mfmsr r5 - andi. r5, r5, (~(MSR_IR | MSR_DR) & 0xFFFF) - mtmsr r5 - isync - blr + mflr r4 + mfmsr r3 + andi. r0, r3, (MSR_IR | MSR_DR) + beqlr + andc r3, r3, r0 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi /* * This code finishes saving the registers to the exception frame @@ -505,9 +521,14 @@ icache_status: .globl dcache_enable dcache_enable: mfspr r3, HID0 + mr r2, r3 ori r3, r3, (HID0_DCI | HID0_DCE) + ori r2, r2, HID0_DCE sync mtspr HID0, r3 + mtspr HID0, r2 + isync + sync blr .globl dcache_disable @@ -515,10 +536,25 @@ dcache_disable: mfspr r3, HID0 li r4, HID0_DCE andc r3, r3, r4 + mr r2, r3 + ori r3, r3, HID0_DCI sync mtspr HID0, r3 + mtspr HID0, r2 + isync + sync blr + .globl dcache_lock +dcache_lock: + mfspr r3, HID0 + ori r3, r3, HID0_DLOCK + sync + mtspr HID0, r3 + isync + sync + blr + .globl dcache_status dcache_status: mfspr r3, HID0 @@ -584,7 +620,9 @@ relocate_code: /* * Now relocate code */ - +#ifdef CONFIG_ECC + bl board_relocate_rom +#else cmplw cr1,r3,r4 addi r0,r5,3 srwi. r0,r0,2 @@ -606,7 +644,7 @@ relocate_code: 3: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b - +#endif /* * Now flush the cache: note that we must start from a cache aligned * address. Otherwise we might miss one cache line. @@ -634,12 +672,14 @@ relocate_code: * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 blr in_ram: +#ifdef CONFIG_ECC + bl board_init_ecc +#endif /* * Relocation Function, r14 point to got2+0x8000 * @@ -694,7 +734,7 @@ clear_bss: mr r3, r9 /* Board Info pointer */ mr r4, r10 /* Destination Address */ - bl board_init_r + bl after_reloc /* Problems accessing "end" in C, so do it here */ .globl get_endaddr @@ -771,95 +811,3 @@ trap_reloc: isync blr - -#if 0 -/* useful routines for debugging the board */ -/* - Josh huber */ -/* --------- debug LED on globals -------- */ - .global led_on0 -led_on0: - addis r18, 0, 0x1c80 - lis r0,temp_reg@h - ori r0,r0,temp_reg@l - stw r18,0x0(r0) - ori r18, r18, 0x8000 - stw r2,0x0(r18) - lwz r18,0x0(r0) - sync - xor r0,r0,r0 - sync - blr - - .global led_on1 -led_on1: - addis r18, 0, 0x1c80 - lis r0,temp_reg@h - ori r0,r0,temp_reg@l - stw r18,0x0(r0) - ori r18, r18, 0xc000 - stw r2,0x0(r18) - lwz r18,0x0(r0) - sync - xor r0,r0,r0 - sync - blr - - .global led_on2 -led_on2: - addis r18, 0, 0x1c81 - lis r0,temp_reg@h - ori r0,r0,temp_reg@l - stw r18,0x0(r0) - ori r18, r18, 0x0000 - stw r2,0x0(r18) - lwz r18,0x0(r0) - sync - xor r0,r0,r0 - sync - blr - -/* ------ Debug led off globals ------ */ - .global led_off0 -led_off0: - lis r0,temp_reg@h - ori r0,r0,temp_reg@l - stw r18,0x0(r0) - addis r18, 0, 0x1c81 - ori r18, r18, 0x4000 - stw r2,0x0(r18) - lwz r18,0x0(r0) - sync - xor r0,r0,r0 - sync - blr - - .global led_off1 -led_off1: - addis r18, 0, 0x1c81 - lis r0,temp_reg@h - ori r0,r0,temp_reg@l - stw r18,0x0(r0) - ori r18, r18, 0x8000 - stw r2,0x0(r18) - lwz r18,0x0(r0) - sync - xor r0,r0,r0 - sync - blr - - .global led_off2 -led_off2: - addis r18, 0, 0x1c81 - lis r0,temp_reg@h - ori r0,r0,temp_reg@l - stw r18,0x0(r0) - ori r18, r18, 0xc000 - stw r2,0x0(r18) - lwz r18,0x0(r0) - sync - xor r0,r0,r0 - sync - blr - -/*------------------------------------------------------------------------------*/ -#endif diff --git a/cpu/mpc74xx/traps.c b/cpu/74xx_7xx/traps.c similarity index 100% rename from cpu/mpc74xx/traps.c rename to cpu/74xx_7xx/traps.c diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h new file mode 100644 index 0000000..a50d03a --- /dev/null +++ b/include/74xx_7xx.h @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2001 + * Josh Huber, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 74xx_7xx.h + * + * 74xx/7xx specific definitions + */ + +#ifndef __MPC74XX_H__ +#define __MPC74XX_H__ + +/*---------------------------------------------------------------- + * Exception offsets (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ + +/*---------------------------------------------------------------- + * l2cr values + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */ +#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */ +#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */ +#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */ +#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */ +#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */ +#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */ +#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */ +#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */ +#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */ +#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */ +#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */ +#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */ +#define L2CR_TS 0x00040000 /* bit 13 - test support on */ +#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */ +#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */ +#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */ +#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/*---------------------------------------------------------------- + * BAT settings. Look in config_.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#ifndef __ASSEMBLY__ +/* cpu ids we detect */ +typedef enum __cpu_t { + CPU_740, CPU_750, + CPU_740P, CPU_750P, + CPU_745, CPU_755, + CPU_750CX, + CPU_7400, + CPU_7410, + CPU_7450, + CPU_UNKNOWN} cpu_t; + +extern cpu_t get_cpu_type(void); + +extern unsigned long get_hid0(void); +extern void set_hid0(unsigned long); +#endif + +#endif /* __MPC74XX_H__ */ diff --git a/include/config_EVB64260.h b/include/config_EVB64260.h index 908860a..8c509d0 100644 --- a/include/config_EVB64260.h +++ b/include/config_EVB64260.h @@ -51,12 +51,18 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_74xx 1 /* This is a MPC74xx */ -#define CONFIG_EVB64260 1 /* ...on an EVB64260 board */ +#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_BAUDRATE 38400 /* console baudrate = 115kbps */ +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#undef CONFIG_ECC /* enable ECC support */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_PRE_INIT + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " /* * The following defines let you select what serial you want to use @@ -85,21 +91,24 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp 1000000; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):eth0:none; "\ + "bootp 1000000 && " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:" \ + "$netmask:$hostname:eth0:none; && " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_ALTIVEC /* undef to disable */ +#undef CONFIG_ALTIVEC /* undef to disable */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -136,11 +145,10 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR 0x00df0000 /* above the memtest region */ -#define CFG_INIT_RAM_END 0x0f00 -#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for init data */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for init data */ #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -167,6 +175,17 @@ #define CFG_DEV2_SIZE _8M #define CFG_DEV3_SIZE _16M +#define CFG_DEV0_PAR 0x20205093 +#define CFG_DEV1_PAR 0xcfcfffff +#define CFG_DEV2_PAR 0xc0059bd4 +#define CFG_8BIT_BOOT_PAR 0xc00b5e7c +#define CFG_32BIT_BOOT_PAR 0xc4a8241c + +#define CFG_MPP_CONTROL_0 0x53541717 +#define CFG_MPP_CONTROL_1 0x44009911 +#define CFG_MPP_CONTROL_2 0x40091818 +#define CFG_MPP_CONTROL_3 0x00090066 + #define CFG_DUART_IO CFG_DEV2_SPACE #define CFG_DUART_CHAN 1 /* channel to use for console */ #define CFG_INIT_CHAN1 @@ -176,67 +195,45 @@ #define SRAM_SIZE 0x00100000 /* 1 MB of sram */ #define CFG_CPU_CLK 300000000 -#define CFG_BUS_CLK 133000000 +#define CFG_BUS_CLK 125000000 /*---------------------------------------------------------------------- * Initial BAT mappings */ -/* do we even need the MMU? probably not... */ -#undef CFG_MMU - -#if 0 /* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L CFG_IBAT1L -#define CFG_DBAT0U CFG_IBAT1U - -/* address range for accessing the Gal. board registers/debug leds */ -#define CFG_IBAT1L (CFG_DEBUG_BASE | BATL_RW | BATL_COHERENT | BATL_GUARDED) -#define CFG_IBAT1U (CFG_DEBUG_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* GT regs, flash, all the devices */ -#define CFG_IBAT2L (CFG_DEV_REGS | BATL_CACHEINHIBIT | BATL_RO) -#define CFG_IBAT2U (CFG_DEV_REGS | BATU_VS | BATU_VP | BATU_BL_16M) -#define CFG_DBAT2L CFG_IBAT0L -#define CFG_DBAT2U CFG_IBAT0U - -/* nothing */ -#define CFG_IBAT3L (BATL_NO_ACCESS) -#define CFG_IBAT3U (BATU_INVALID) -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -/* values that DINK sets up...currently the kernel expects these values */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM */ -#define CFG_IBAT0L 0x00000032 -#define CFG_IBAT0U 0x00001fff -#define CFG_DBAT0L 0x00000032 -#define CFG_DBAT0U 0x00001fff - -/* address range for accessing the Gal. board registers/debug leds */ -#define CFG_IBAT1L 0x10000032 -#define CFG_IBAT1U 0x10001fff -#define CFG_DBAT1L 0x10000032 -#define CFG_DBAT1U 0x10001fff - -/* GT regs, flash, all the devices */ -#define CFG_IBAT2L 0x00000012 -#define CFG_IBAT2U 0xc0001fff -#define CFG_DBAT2L 0x00000012 -#define CFG_DBAT2U 0xc0001fff - -/* nothing */ -#define CFG_IBAT3L 0xf0000012 -#define CFG_IBAT3U 0xf0001fff -#define CFG_DBAT3L 0xf0000032 -#define CFG_DBAT3U 0xf0001fff -#endif +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* galileo regs [poweron location] */ +#define CFG_IBAT2L (CFG_DFL_GT_REGS | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (CFG_DFL_GT_REGS | BATU_BL_16M | BATU_VS | BATU_VP) + +/* flash, moved GT regs, etc */ +#define CFG_DBAT3L (CFG_GT_REGS | BATL_PP_10 | BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_GT_REGS | BATU_BL_256M | BATU_VS | BATU_VP) + +/* the GUARDEDSTORAGE bit should not be set in IBATs */ +#define CFG_IBAT3L (CFG_GT_REGS | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (CFG_GT_REGS | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 /* * For booting Linux, the board info and command line data @@ -279,7 +276,7 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #endif /* __CONFIG_H */ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h index 4acc084..12b3a8b 100644 --- a/include/galileo/gt64260R.h +++ b/include/galileo/gt64260R.h @@ -9,6 +9,10 @@ #define GT64260 #endif +/* CPU MASTER CONTROL REGISTER */ +#define CPU_CONFIGURATION 0x0 +#define CPU_MASTER_CONTROL 0x160 + /****************************************/ /* Processor Address Space */ /****************************************/ @@ -174,6 +178,7 @@ #define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 #define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac #define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 +#define SDRAM_TIMING 0x4b4 /****************************************/ @@ -681,99 +686,6 @@ #define L_SLAVE_READ_DATA_HIGH 0x1d3c #define L_SLAVE_READ_ID 0x1d64 -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0X04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 -#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 -#define PCI_CPU_BASE_ADDRESS 0x21c - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 - /****************************************/ /* Interrupts */ /****************************************/ diff --git a/include/galileo/pci.h b/include/galileo/pci.h index d31bceb..92f7e9e 100644 --- a/include/galileo/pci.h +++ b/include/galileo/pci.h @@ -358,4 +358,98 @@ bool pci0SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, bool pci1SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, unsigned int baseAddress, unsigned int regionLength); + +/****************************************/ +/* PCI Configuration Function 0 */ +/****************************************/ + +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C +#define PCI_SCS_0_BASE_ADDRESS 0x010 +#define PCI_SCS_1_BASE_ADDRESS 0x014 +#define PCI_SCS_2_BASE_ADDRESS 0x018 +#define PCI_SCS_3_BASE_ADDRESS 0x01C +#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 +#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 +#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C +#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define PCI_VPD_ADDRESS 0x048 +#define PCI_VPD_DATA 0X04c +#define PCI_MSI_MESSAGE_CONTROL 0x050 +#define PCI_MSI_MESSAGE_ADDRESS 0x054 +#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 +#define PCI_MSI_MESSAGE_DATA 0x05c +#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 + +/****************************************/ +/* PCI Configuration Function 1 */ +/****************************************/ + +#define PCI_CS_0_BASE_ADDRESS 0x110 +#define PCI_CS_1_BASE_ADDRESS 0x114 +#define PCI_CS_2_BASE_ADDRESS 0x118 +#define PCI_CS_3_BASE_ADDRESS 0x11c +#define PCI_BOOTCS_BASE_ADDRESS 0x120 + +/****************************************/ +/* PCI Configuration Function 2 */ +/****************************************/ + +#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 +#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 +#define PCI_P2P_I_O_BASE_ADDRESS 0x218 +#define PCI_CPU_BASE_ADDRESS 0x21c + +/****************************************/ +/* PCI Configuration Function 4 */ +/****************************************/ + +#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 +#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 +#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 +#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 + + +/****************************************/ +/* PCI Configuration Function 5 */ +/****************************************/ + +#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 +#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 +#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 +#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 + + +/****************************************/ +/* PCI Configuration Function 6 */ +/****************************************/ + +#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 +#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 +#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 +#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c +#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 +#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 + +/****************************************/ +/* PCI Configuration Function 7 */ +/****************************************/ + +#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 +#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c +#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 +#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 + #endif /* __INCpcih */ diff --git a/include/ppcboot.h b/include/ppcboot.h index e0cc3fd..3e273f3 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -202,28 +202,27 @@ int saveenv(void); #if defined(CONFIG_CPCI405) || \ defined(CONFIG_AR405) || \ - defined (CONFIG_WALNUT405) || \ - defined (CONFIG_PIP405) || \ - defined (CONFIG_MIP405) || \ - defined (CONFIG_CPCIISER4) || \ - defined (CONFIG_OCRTC) || \ - defined (CONFIG_DASA_SIM) || \ - defined (CONFIG_ERIC) || \ - defined (CONFIG_MOUSSE) || \ - defined (CONFIG_BAB750) || \ - defined (CONFIG_W7O) + defined(CONFIG_WALNUT405) || \ + defined(CONFIG_PIP405) || \ + defined(CONFIG_MIP405) || \ + defined(CONFIG_CPCIISER4) || \ + defined(CONFIG_OCRTC) || \ + defined(CONFIG_DASA_SIM) || \ + defined(CONFIG_ERIC) || \ + defined(CONFIG_MOUSSE) || \ + defined(CONFIG_BAB750) || \ + defined(CONFIG_W7O) /* $(CPU)/405gp_pci.c */ void pci_init (bd_t *); void pciinfo (int); #endif -#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \ - defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) || \ - defined(CONFIG_CPCI405) || defined(CONFIG_PCU_E) || \ - defined(CONFIG_EVB64260) || defined(CONFIG_LWMON) || \ - defined(CONFIG_EVB64260) || defined(CONFIG_LWMON) || \ - defined(CONFIG_CCM) || defined(CONFIG_W7O) || \ - defined(CONFIG_MISC_INIT_R) +#if defined(CONFIG_CCM) || defined(CONFIG_COGENT) || \ + defined(CONFIG_CPCI405) || defined(CONFIG_HYMOD) || \ + defined(CONFIG_LWMON) || defined(CONFIG_MISC_INIT_R) || \ + defined(CONFIG_PCU_E) || defined(CONFIG_RSD_PROTO) || \ + defined(CONFIG_SXNI855T) || defined(CONFIG_W7O) + /* cogent - $(BOARD)/mb.c */ /* SXNI855T, HYMOD, and W7O - $(BOARD)/$(BOARD).c */ # if !defined(CONFIG_PCU_E) && !defined(CONFIG_CCM) @@ -329,7 +328,6 @@ void load_sernum_ethaddr(bd_t *bd); defined(CONFIG_MPC8260ADS) || \ defined(CONFIG_RPXSUPER) || \ defined(CONFIG_CU824) || \ - defined(CONFIG_EVB64260) || \ defined(CONFIG_W7O) || \ defined(CONFIG_BOARD_PRE_INIT) /* $(BOARD)/$(BOARD).c */