From: Dave Airlie <airlied@redhat.com>
Date: Fri, 16 Jun 2017 03:58:27 +0000 (+1000)
Subject: BackMerge tag 'v4.12-rc5' into drm-next
X-Git-Tag: v4.13-rc1~73^2~15
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=925344ccc91d7a7fd84cab2dece1c34bbd86fd8c;p=users%2Fjedix%2Flinux-maple.git

BackMerge tag 'v4.12-rc5' into drm-next

Linux 4.12-rc5 for nouveau fixes
---

925344ccc91d7a7fd84cab2dece1c34bbd86fd8c
diff --cc drivers/gpu/drm/i915/i915_pci.c
index f80db2ccd92f,1a78363c7f4a..f940e486a62a
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -383,9 -387,9 +383,8 @@@ static const struct intel_device_info i
  	.has_rc6 = 1, \
  	.has_dp_mst = 1, \
  	.has_gmbus_irq = 1, \
 -	.has_hw_contexts = 1, \
  	.has_logical_ring_contexts = 1, \
  	.has_guc = 1, \
- 	.has_decoupled_mmio = 1, \
  	.has_aliasing_ppgtt = 1, \
  	.has_full_ppgtt = 1, \
  	.has_full_48bit_ppgtt = 1, \
diff --cc drivers/gpu/drm/i915/intel_dp.c
index 4a6feb6a69bd,fc691b8b317c..de4b1f2d367d
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -1654,13 -1587,16 +1634,15 @@@ intel_dp_compute_config(struct intel_en
  	/* Conveniently, the link BW constants become indices with a shift...*/
  	int min_clock = 0;
  	int max_clock;
 -	int link_rate_index;
  	int bpp, mode_rate;
  	int link_avail, link_clock;
 -	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
  	int common_len;
  	uint8_t link_bw, rate_select;
+ 	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
+ 					   DP_DPCD_QUIRK_LIMITED_M_N);
  
 -	common_len = intel_dp_common_rates(intel_dp, common_rates);
 +	common_len = intel_dp_common_len_rate_limit(intel_dp,
 +						    intel_dp->max_link_rate);
  
  	/* No common link rates between source and sink */
  	WARN_ON(common_len <= 0);
diff --cc drivers/gpu/drm/i915/intel_drv.h
index bd500977b3fc,f630c7af5020..71f94a01aedd
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@@ -981,22 -941,15 +973,22 @@@ struct intel_dp 
  	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 -	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 -	uint8_t num_sink_rates;
 +	/* source rates */
 +	int num_source_rates;
 +	const int *source_rates;
 +	/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 +	int num_sink_rates;
  	int sink_rates[DP_MAX_SUPPORTED_RATES];
 -	/* Max lane count for the sink as per DPCD registers */
 -	uint8_t max_sink_lane_count;
 -	/* Max link BW for the sink as per DPCD registers */
 -	int max_sink_link_bw;
 +	bool use_rate_select;
 +	/* intersection of source and sink rates */
 +	int num_common_rates;
 +	int common_rates[DP_MAX_SUPPORTED_RATES];
 +	/* Max lane count for the current link */
 +	int max_link_lane_count;
 +	/* Max rate for the current link */
 +	int max_link_rate;
  	/* sink or branch descriptor */
- 	struct intel_dp_desc desc;
+ 	struct drm_dp_desc desc;
  	struct drm_dp_aux aux;
  	enum intel_display_power_domain aux_power_domain;
  	uint8_t train_set[4];