From: Elena Reshetova Date: Thu, 4 Jan 2018 07:19:32 +0000 (-0800) Subject: x86/cpu/AMD: Make the LFENCE instruction serialized X-Git-Tag: v4.1.12-124.31.3~1385 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=911bb9204fe25ba5fd33ffee33b966cdde2f59c7;p=users%2Fjedix%2Flinux-maple.git x86/cpu/AMD: Make the LFENCE instruction serialized In order to reduce the impact of using MFENCE, make the execution of the LFENCE instruction serialized. This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not have this MSR. For these families, the LFENCE instruction is already serialized. Signed-off-by: Tom Lendacky Orabug: 27340445 CVE: CVE-2017-5753 Signed-off-by: Chuck Anderson Conflicts: patch refers to arch/x86/include/asm/msr-index.h code base has arch/x86/include/uapi/asm/msr-index.h Reviewed-by: John Haxby Signed-off-by: Kirtikar Kashyap --- diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 50df8b992015..a4d88b896b55 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -326,6 +326,8 @@ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL #define FAM10H_MMIO_CONF_BASE_SHIFT 20 #define MSR_FAM10H_NODE_ID 0xc001100c +#define MSR_F10H_DECFG 0xc0011029 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e4cf63301ff4..5d9632f267a7 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -700,8 +700,17 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has_xmm2) { - /* MFENCE stops RDTSC speculation */ - set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); + /* + * Use LFENCE for execution serialization. On some families + * LFENCE is already serialized and the MSR is not available, + * but msr_set_bit() uses rdmsrl_safe() and wrmsrl_safe(). + */ + if (c->x86 > 0xf) + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + + /* LFENCE with MSR_F10H_DECFG[1]=1 stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); } /*