From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Wed, 29 Jan 2025 19:23:22 +0000 (-0800)
Subject: Merge tag 'cxl-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=9071080d1e7af1a3a1699c3ba065c3293b5d09ce;p=users%2Fwilly%2Fpagecache.git

Merge tag 'cxl-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

Pull Compute Express Link (CXL) updates from Dave Jiang:
 "A tweak to the HMAT output that was acked by Rafael, a prep patch for
  CXL type2 devices support that's coming soon, refactoring of the CXL
  regblock enumeration code, and a series of patches to update the event
  records to CXL spec r3.1:

   - Move HMAT printouts to pr_debug()

   - Add CXL type2 support to cxl_dvsec_rr_decode() in preparation for
     type2 support

   - A series that updates CXL event records to spec r3.1 and related
     changes

   - Refactoring of cxl_find_regblock_instance() to count regblocks"

* tag 'cxl-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
  cxl/core/regs: Refactor out functions to count regblocks of given type
  cxl/test: Update test code for event records to CXL spec rev 3.1
  cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
  cxl/events: Update DRAM Event Record to CXL spec rev 3.1
  cxl/events: Update General Media Event Record to CXL spec rev 3.1
  cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
  cxl/events: Update Common Event Record to CXL spec rev 3.1
  cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()
  ACPI/HMAT: Move HMAT messages to pr_debug()
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9071080d1e7af1a3a1699c3ba065c3293b5d09ce