From: wdenk Date: Sun, 27 Jan 2002 00:56:55 +0000 (+0000) Subject: * Patch by Josh Huber, 22 Jan 2002 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=8f606eeaacc2d8855c4dedf8a4ec697f11fb9637;p=users%2Frw%2Fppcboot.git * Patch by Josh Huber, 22 Jan 2002 Fixes for EVB64260 board: - Fixes to the built-in ethernet driver - Fixes to the PCI init code - Re-write of the cache-management code - Fixes to the MPSC driver (built-in serial) - Cleanups/fixes to the memory detection routines - Many additional bugs fixed * Patch by Jim Thompson, 22 Jan 2002 - Add support for a Sandpoint_8245 target - Add support for a slightly different controller in board/sandpoint/eepro100.c - Remove unused function (checkflash()) from board/sandpoint/sandpoint.c - Make Musenki board use the stack-in-cache method - automatically set SDMODE_BURSTLEN to the appropriate value based on values in MCCR1. This deprecates CFG_SDMODE_BURSTLEN * Patch by Steve Bradshaw, 21 Jan 2002 - update/fix 405GP Walnut configuration * Patch by Pierre Aubert, 23 Jan 2002 - Add port for RPXClassic board - minor bug fixes in i2c and arp * Patch by Rich Ireland, 22 Jan 2002: Fix for bootelf command: clear BSS (and other sections of type 'SHT_NOBITS' when the SHF_ALLOC flag is present) * Patch by Nye Liu (et al), 24 Jan 2002: - evb changes - JFFS2 (read only) code. * Patch by Andrew May, 23 Jan 2002: Modified I2C clock divider calculation on 4xx boards. * Patch by Andrew May, 23 Jan 2002: - Pad BOOTP / DHCP extension lists to minimal length; some (WinNT?) DHCP servers seem to need this. - Don't delete any existing bootfile definition if DHCP / BOOTP reply does not provide one. --- diff --git a/CHANGELOG b/CHANGELOG index 72e8005..99c71cd 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,48 @@ Modifications for 1.1.5: ====================================================================== +* Patch by Josh Huber, 22 Jan 2002 + Fixes for EVB64260 board: + - Fixes to the built-in ethernet driver + - Fixes to the PCI init code + - Re-write of the cache-management code + - Fixes to the MPSC driver (built-in serial) + - Cleanups/fixes to the memory detection routines + - Many additional bugs fixed + +* Patch by Jim Thompson, 22 Jan 2002 + - Add support for a Sandpoint_8245 target + - Add support for a slightly different controller in + board/sandpoint/eepro100.c + - Remove unused function (checkflash()) from board/sandpoint/sandpoint.c + - Make Musenki board use the stack-in-cache method + - automatically set SDMODE_BURSTLEN to the appropriate value based + on values in MCCR1. This deprecates CFG_SDMODE_BURSTLEN + +* Patch by Steve Bradshaw, 21 Jan 2002 + - update/fix 405GP Walnut configuration + +* Patch by Pierre Aubert, 23 Jan 2002 + - Add port for RPXClassic board + - minor bug fixes in i2c and arp + +* Patch by Rich Ireland, 22 Jan 2002: + Fix for bootelf command: clear BSS (and other sections of type + 'SHT_NOBITS' when the SHF_ALLOC flag is present) + +* Patch by Nye Liu (et al), 24 Jan 2002: + - evb changes + - JFFS2 (read only) code. + +* Patch by Andrew May, 23 Jan 2002: + Modified I2C clock divider calculation on 4xx boards. + +* Patch by Andrew May, 23 Jan 2002: + - Pad BOOTP / DHCP extension lists to minimal length; some (WinNT?) + DHCP servers seem to need this. + - Don't delete any existing bootfile definition if DHCP / BOOTP + reply does not provide one. + * Add watchdog support for PCIPPC-2 board * Add DOC boot command and (raw) partition info support diff --git a/CREDITS b/CREDITS index 006cbf1..dff1bca 100644 --- a/CREDITS +++ b/CREDITS @@ -22,6 +22,10 @@ N: Swen Anderson E: sand@peppercon.de D: ERIC Support +N: Pierre Aubert +E: +D: Support for RPXClassic board + N: Andre Beaudin E: D: PCMCIA, Ethernet, TFTP diff --git a/MAKEALL b/MAKEALL index d09bcf2..f2ac5b8 100755 --- a/MAKEALL +++ b/MAKEALL @@ -22,9 +22,10 @@ LIST_8xx=" \ IP860 IVML24 IVML24_128 IVML24_256 \ IVMS8 IVMS8_128 IVMS8_256 LANTEC \ lwmon MBX MBX860T MHPC \ - NX823 pcu_e RPXlite SM850 \ - SPD823TS SXNI855T TQM823L TQM823L_LCD \ - TQM850L TQM855L TQM860L TQM860L_FEC \ + NX823 pcu_e RPXClassic RPXlite \ + SM850 SPD823TS SXNI855T TQM823L \ + TQM823L_LCD TQM850L TQM855L TQM860L \ + TQM860L_FEC \ " ######################################################################### @@ -43,10 +44,8 @@ LIST_4xx=" \ ######################################################################### LIST_824x=" \ - CU824 \ - MOUSSE \ - MUSENKI \ - Sandpoint8240 \ + CU824 MOUSSE MUSENKI \ + Sandpoint8240 Sandpoint8245 \ " ######################################################################### @@ -64,7 +63,7 @@ LIST_8260=" \ ######################################################################### LIST_74xx=" \ - EVB64260 PCIPPC2 \ + EVB64260 PCIPPC2 ZUMA \ " ######################################################################### diff --git a/Makefile b/Makefile index aaf1de2..0448a6f 100644 --- a/Makefile +++ b/Makefile @@ -62,8 +62,9 @@ SUBDIRS = tools \ cpu/$(CPU) \ board/$(BOARDDIR) \ common \ - net \ disk \ + fs \ + net \ rtc \ examples @@ -71,7 +72,8 @@ SUBDIRS = tools \ # ppcboot objects....order is important (i.e. start must be first) OBJS = cpu/$(CPU)/start.o \ - common/libcommon.a + common/libcommon.a \ + fs/jffs2/libjffs2.a OBJS += net/libnet.a disk/libdisk.a rtc/librtc.a @@ -344,6 +346,14 @@ pcu_e_config: unconfig echo "VENDOR = siemens" >>config.mk ; \ echo "#include " >config.h +RPXClassic_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = RPXClassic" >>config.mk ; \ + echo "CPU = mpc8xx" >>config.mk ; \ + echo "#include " >config.h + RPXlite_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd ./include ; \ @@ -577,7 +587,15 @@ Sandpoint8240_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd ./include ; \ echo "ARCH = ppc" > config.mk ; \ - echo "BOARD = sandpoint" >>config.mk ; \ + echo "BOARD = sandpoint">>config.mk ; \ + echo "CPU = mpc824x" >>config.mk ; \ + echo "#include " >config.h + +Sandpoint8245_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd ./include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = sandpoint">>config.mk ; \ echo "CPU = mpc824x" >>config.mk ; \ echo "#include " >config.h @@ -671,7 +689,8 @@ TQM8260_L2_config: unconfig ## 74xx/7xx Systems ######################################################################### -EVB64260_config: unconfig +EVB64260_config \ +ZUMA_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd ./include ; \ echo "ARCH = ppc" > config.mk ; \ diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile new file mode 100644 index 0000000..ef173d0 --- /dev/null +++ b/board/RPXClassic/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c new file mode 100644 index 0000000..3f3a952 --- /dev/null +++ b/board/RPXClassic/RPXClassic.c @@ -0,0 +1,298 @@ +/* + * (C) Copyright 2001 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * PPCboot port on RPXClassic LF (CLLF_BW31) board + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "mpc8xx.h" + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +static unsigned char aschex_to_byte (unsigned char *cp); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 00h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, + 0x3FBFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Read. (Offset 08h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, + 0x3FBFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, + 0x3FFFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, + 0x0CFFCC00, 0x33FFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* + * Refresh. (Offset 30h in UPMA RAM) + */ + 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, + 0x3FFFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3Ch in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Return 1 for now. + * + */ + +int checkboard (void) +{ + printf("RPXClassic\n") ; + + return (1) ; +} + +/*----------------------------------------------------------------------------- + * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM + *----------------------------------------------------------------------------- + */ +void board_get_enetaddr (uchar *enet) +{ + int i; + char buff [256], *cp; + uchar addr [2] = {0x54, 0}; + + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (addr, 2, buff, 128); + addr [1] = 128; + i2c_read (addr, 2, buff + 128, 128); + + /* Retrieve MAC address in buffer (key EA) */ + for (cp = buff;;) { + if (cp [0] == 'E' && cp [1] == 'A') { + cp += 3; + /* Read MAC address */ + for (i = 0; i < 6; i++, cp += 2) { + enet [i] = aschex_to_byte (cp); + } + } + /* Scan to the end of the record */ + while ((*cp != '\n') && (*cp != 0xff)) { + cp++; + } + /* If the next character is a \n, 0 or ff, we are done. */ + cp++; + if ((*cp == '\n') || (*cp == 0) || (*cp == 0xff)) + break; + } + +#ifdef CONFIG_FEC_ENET + /* The MAC address is the same as normal ethernet except the 3rd byte */ + /* (See the E.P. Planet Core Overview manual */ + enet [3] |= 0x80; + + /* Validate the fast ethernet tranceiver */ + *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; + *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; + *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; + *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; +#endif + + printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", + enet [0], enet [1], enet [2], enet [3], enet [4], enet [5]); + +} + +void rpxclassic_init (void) +{ + /* Enable NVRAM */ + *((uchar *) BCSR0) |= BCSR0_ENNVRAM ; + +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size10 ; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = CFG_MPTPR ; + + memctl->memc_mar = 0x00000000; + + /* Map controller banks 1 to the SDRAM bank */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002230 ; /* SDRAM bank 0 - refresh twice */ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* Check Bank 0 Memory Size + * try 10 column mode + */ + + size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ; + + return (size10); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof(long)); + } + } + return (maxsize); +} +static unsigned char aschex_to_byte (unsigned char *cp) +{ + u_char byte, c; + + c = *cp++; + + if ((c >= 'A') && (c <= 'F')) { + c -= 'A'; + c += 10; + } + else if ((c >= 'a') && (c <= 'f')) { + c -= 'a'; + c += 10; + } + else { + c -= '0'; + } + + byte = c * 16; + + c = *cp; + + if ((c >= 'A') && (c <= 'F')) { + c -= 'A'; + c += 10; + } + else if ((c >= 'a') && (c <= 'f')) { + c -= 'a'; + c += 10; + } + else { + c -= '0'; + } + + byte += c; + + return(byte); +} diff --git a/board/RPXClassic/config.mk b/board/RPXClassic/config.mk new file mode 100644 index 0000000..704251c --- /dev/null +++ b/board/RPXClassic/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Stäubli Faverges - +# Pierre AUBERT p.aubert@staubli.com +# PPCboot port on RPXClassic LF (CLLF_BW31) board +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xff000000 diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c new file mode 100644 index 0000000..897fc05 --- /dev/null +++ b/board/RPXClassic/flash.c @@ -0,0 +1,447 @@ +/* + * (C) Copyright 2001 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * PPCboot port on RPXClassic LF (CLLF_BW31) board + * + * RPXClassic uses Am29DL323B flash memory with 2 banks + * + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0 ; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000) ; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL323B: + printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Reset flash componeny */ + addr [0] = 0xf0f0f0f0; + + /* Write auto select command: read Manufacturer ID */ + addr[0xAAA] = 0xAAAAAAAA ; + addr[0x555] = 0x55555555 ; + addr[0xAAA] = 0x90909090 ; + + value = addr[0] ; + + switch (value & 0x00FF00FF) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[2] ; /* device ID */ + + switch (value & 0x00FF00FF) { + case (AMD_ID_DL323B & 0x00FF00FF): + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; /* 16 Mb */ + + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + /* set up sector start address table */ + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000) ; + } + + /* check for protected sectors */ + for (i = 0; i < 23; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; + } + /* Check for protected sectors in the 2nd bank */ + addr[0x100AAA] = 0xAAAAAAAA ; + addr[0x100555] = 0x55555555 ; + addr[0x100AAA] = 0x90909090 ; + + for (i = 23; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0xF0F0F0F0; /* reset bank 1 */ + addr = (volatile unsigned long *)info->start[23]; + + *addr = 0xF0F0F0F0; /* reset bank 2 */ + + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0x80808080; + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *)(info->start[sect]) ; + addr[0] = 0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long *)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/RPXClassic/ppcboot.lds b/board/RPXClassic/ppcboot.lds new file mode 100644 index 0000000..c25c3c3 --- /dev/null +++ b/board/RPXClassic/ppcboot.lds @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/ppcstring.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/zlib.o (.text) +/* XXX ? + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/RPXClassic/ppcboot.lds.debug b/board/RPXClassic/ppcboot.lds.debug new file mode 100644 index 0000000..f230a6b --- /dev/null +++ b/board/RPXClassic/ppcboot.lds.debug @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile index 3cd2191..4f209e1 100644 --- a/board/evb64260/Makefile +++ b/board/evb64260/Makefile @@ -27,7 +27,9 @@ LIB = lib$(BOARD).a SOBJS = misc.o OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ - eth.o ns16550.o mpsc.o i2c.o sdram_init.o + eth.o eth_addrtbl.o ns16550.o mpsc.o i2c.o \ + sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o + $(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt new file mode 100644 index 0000000..e20153c --- /dev/null +++ b/board/evb64260/bootseq.txt @@ -0,0 +1,94 @@ +(cpu/mpc7xxx/start.S) + +start: + b boot_cold + +start_warm: + b boot_warm + + +boot_cold: +boot_warm: + clear bats + init l2 (if enabled) + init altivec (if enabled) + invalidate l2 (if enabled) + setup bats (from defines in config_EVB) + enable_addr_trans: (if MMU enabled) + enable MSR_IR and MSR_DR + jump to in_flash + +in_flash: + enable l1 dcache + gal_low_init: (board/evb64260/sdram_init.S) + config SDRAM (CFG, TIMING, DECODE) + init scratch regs (810 + 814) + + detect DIMM0 (bank 0 only) + config SDRAM_PARA0 to 256/512Mbit + bl sdram_op_mode + detect bank0 width + write scratch reg 810 + config SDRAM_PARA0 with results + config SDRAM_PARA1 with results + + detect DIMM1 (bank 2 only) + config SDRAM_PARA2 to 256/512Mbit + detect bank2 width + write scratch reg 814 + config SDRAM_PARA2 with results + config SDRAM_PARA3 with results + + setup device bus timings/width + setup boot device timings/width + + setup CPU_CONF (0x0) + setup cpu master control register 0x160 + setup PCI0 TIMEOUT + setup PCI1 TIMEOUT + setup PCI0 BAR + setup PCI1 BAR + + setup MPP control 0-3 + setup GPP level control + setup Serial ports multiplex + + setup stack pointer (r1) + setup GOT + call cpu_init_f + debug leds + board_init_f: (common/board.c) + board_pre_init: + remap gt regs? + map PCI mem/io + map device space + clear out interupts + init_timebase + env_init + serial_init + console_init_f + display_options + initdram: (board/evb64260/evb64260.c) + detect memory + for each bank: + dram_size() + setup PCI slave memory mappings + setup SCS + setup monitor + alloc board info struct + init bd struct + relocate_code: (cpu/mpc7xxx/start.S) + copy,got,clearbss + board_init_r(bd, dest_addr) (common/board.c) + setup bd function pointers + trap_init + flash_init: (board/evb64260/flash.c) + setup bd flash info + cpu_init_r: (cpu/mpc7xxx/cpu_init.c) + nothing + mem_malloc_init + malloc_bin_reloc + spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + env_relocated + misc_init_r(bd): (board/evb64260/evb64260.c) + mpsc_init2 diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c new file mode 100644 index 0000000..187a908 --- /dev/null +++ b/board/evb64260/ecctest.c @@ -0,0 +1,91 @@ +#ifdef ECC_TEST +static inline void ecc_off(void) +{ + *(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) &= ~0x00200000; +} + +static inline void ecc_on(void) +{ + *(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) |= 0x00200000; +} + +static int putshex(const char *buf, int len) +{ + int i; + for (i=0;i #include +#include #include #include +#include +#include #include + #include "eth.h" +#include "eth_addrtbl.h" -/* globals */ -eth0_tx_desc_single *eth0_tx_desc; -eth0_rx_desc_single *eth0_rx_desc; -char *eth0_tx_buffer; -char *eth0_rx_buffer[NR]; +/* if you like verbose output, turn this on! */ +#undef DEBUG + +/* Restart autoneg if we detect link is up on phy init. */ +/* (fixes some autoneg problems with bad hubs/switches) */ +#undef RESTART_AUTONEG + +/* do this if you want to filter for our mac */ +#define USE_MAC_HASH_TABLE + +/* do this if you dont want to use snooping */ +#define USE_SOFTWARE_CACHE_MANAGEMENT + +#ifdef USE_SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +/* bummer - w/o flush, nothing works, even with snooping - FIXME */ +// #define FLUSH_DCACHE(a,b) +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) +#endif -unsigned long pci_dram_offset = 0; -char *eth_data; +/* locals */ +static eth0_tx_desc_single *eth0_tx_desc; +static eth0_rx_desc_single *eth0_rx_desc; +static char *eth0_tx_buffer; +static char *eth0_rx_buffer[NR]; -/* if you like verbose output, turn this on! */ -#undef DEBUG +#ifdef ZUMA_NTL +/* for intel LXT972 */ +static const char ether_port_phy_addr[3]={0,1,2}; +#else +static const char ether_port_phy_addr[3]={4,5,6}; +#endif + +#define ETHER_PORT_PHY (ether_port_phy_addr[CONFIG_ETHER_PORT]) /* calculate the offset to the desired ethernet registers */ /* the registers are offset by 0x400 for each port -- see the headers */ -#define REG_OFF (CONFIG_ETHER_PORT * 0x400) +#define REG_OFF (CONFIG_ETHER_PORT * ETHERNET_PORTS_DIFFERENCE_OFFSETS) + +static inline unsigned short +miiphy_read_ret(unsigned short phy, unsigned short reg) +{ + unsigned short val; + miiphy_read(phy,reg,&val); + return val; +} + /************************************************************************** RESET - Reset adapter @@ -54,20 +96,59 @@ evb64260_eth0_reset(bd_t *bis) /* put the card in its initial state */ } -/************************************************************************** -POLL - Wait for a frame -***************************************************************************/ -int -evb64260_eth0_poll(void) +static void evb64260_handle_SMI(unsigned int icr) { - unsigned int eth_len; +#ifdef DEBUG + printf("SMI interrupt: "); + + if(icr&0x20000000) { + printf("SMI done\n"); + } +#endif + + if(icr&0x10000000) { + unsigned short mii_11; + unsigned int psr; + mii_11=miiphy_read_ret(ETHER_PORT_PHY,0x11); + psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF); +#ifdef DEBUG + printf("PHY state change:\n" + " GT:%s:%s:%s:%s\n" + "mii:%s:%s:%s:%s %s:%s %s\n", + psr&1?"100":" 10", + psr&8?" Link":"nLink", + psr&2?"FD":"HD", + psr&4?" FC":"nFC", + + mii_11&(1<<14)?"100":" 10", + mii_11&(1<<10)?" Link":"nLink", + mii_11&(1<<9)?"FD":"HD", + mii_11&(1<<4)?" FC":"nFC", + + mii_11&(1<<7)?"ANc":"ANnc", + mii_11&(1<<8)?"AN":"Manual", + "" + ); +#endif + } +} - if (eth0_rx_desc[(RDN_ETH0)].command_status & 0x80000000) { +static int +evb64260_eth0_receive(unsigned int icr) +{ + int eth_len=0; + char *eth_data; + + eth0_rx_desc_single *rx=ð0_rx_desc[(RDN_ETH0)]; + + INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); + + if (rx->command_status & 0x80000000) { return 0; // No packet received } eth_len = (unsigned int) - (eth0_rx_desc[(RDN_ETH0)].buff_size_byte_count) & 0x0000ffff; + (rx->buff_size_byte_count) & 0x0000ffff; eth_data = (char *) eth0_rx_buffer[RDN_ETH0]; #ifdef DEBUG @@ -84,10 +165,13 @@ evb64260_eth0_poll(void) /* let the upper layer handle the packet */ NetReceive (eth_data, eth_len); - eth0_rx_desc[(RDN_ETH0)].buff_size_byte_count = 1536<<16; + rx->buff_size_byte_count = 1536<<16; + /* GT96100 Owner */ - eth0_rx_desc[(RDN_ETH0)].command_status = 0x80000000; + rx->command_status = 0x80000000; + + FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); RDN_ETH0 ++; if (RDN_ETH0 == NR) {RDN_ETH0 = 0;} @@ -97,20 +181,59 @@ evb64260_eth0_poll(void) /* Start Rx*/ GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080); +#ifdef DEBUG + { + int i; + for (i=0;i<12;i++) { + printf(" %02x", eth_data[i]); + } + } + printf(": %d bytes\n", eth_len); +#endif + INVALIDATE_DCACHE((unsigned int)eth_data, + (unsigned int)eth_data+eth_len); return eth_len; } +/************************************************************************** +POLL - look for an rx frame, handle other conditions +***************************************************************************/ +int +evb64260_eth0_poll(void) +{ + unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + REG_OFF); + + if(icr) { + GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER, 0); +#ifdef DEBUG + printf("poll got ICR %08x\n", icr); +#endif + /* SMI done or PHY state change*/ + if(icr&0x30000000) evb64260_handle_SMI(icr); + } + /* always process. We aren't using RX interrupts */ + return evb64260_eth0_receive(icr); +} + /************************************************************************** TRANSMIT - Transmit a frame ***************************************************************************/ int evb64260_eth0_transmit(unsigned int s, volatile char *p) { + unsigned int old_command_stat,old_psr; + eth0_tx_desc_single *tx=ð0_tx_desc[(TDN_ETH0)]; + /* wait for tx to be ready */ - while (eth0_tx_desc[(TDN_ETH0)].command_status & 0x80000000) ; + INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); + while (tx->command_status & 0x80000000) { + int i; + for(i=0;i<1000;i++); + INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); + } GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF, - (unsigned int)eth0_tx_desc); + (unsigned int)tx); #ifdef DEBUG printf("copying to tx_buffer [%p], length %x, desc = %p\n", @@ -118,23 +241,58 @@ evb64260_eth0_transmit(unsigned int s, volatile char *p) #endif memcpy(eth0_tx_buffer, (char *) p, s); - eth0_tx_desc[(TDN_ETH0)].buff_pointer = eth0_tx_buffer; - eth0_tx_desc[(TDN_ETH0)].bytecount_reserved = ((__u16)s) << 16; - if (s<60) { - eth0_tx_desc[(TDN_ETH0)].bytecount_reserved = 60<<16; - } - - eth0_tx_desc[(TDN_ETH0)].command_status = 0x80470000; - eth0_tx_desc[(TDN_ETH0)].next_desc = + tx->buff_pointer = eth0_tx_buffer; + tx->bytecount_reserved = ((__u16)s) << 16; + + /* 31 - own + * 22 - gencrc + * 18:16 - pad, last, first */ + tx->command_status = (1<<31) | (1<<22) | (7<<16); +#if 0 + /* FEr #18 */ + tx->next_desc = NULL; +#else + tx->next_desc = (struct eth0_tx_desc_struct *) ð0_tx_desc[(TDN_ETH0+1)%NT].bytecount_reserved; - eth0_tx_desc[(TDN_ETH0+1)%NT].command_status = 0x0003ffff; + /* cpu owned */ + eth0_tx_desc[(TDN_ETH0+1)%NT].command_status = (7<<16); /* pad, last, first */ +#endif - sync(); + old_command_stat=tx->command_status, + old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF); + + FLUSH_DCACHE((unsigned int)tx, + (unsigned int)ð0_tx_desc[(TDN_ETH0+2)%NT]); + + FLUSH_DCACHE((unsigned int)eth0_tx_buffer,(unsigned int)eth0_tx_buffer+s); GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x01000000); +#ifdef DEBUG + { + unsigned int command_stat=0; + printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); + /* wait for tx to be ready */ + do { + unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF); + command_stat=tx->command_status; + if(command_stat!=old_command_stat || psr !=old_psr) { + printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); + old_command_stat = command_stat; + old_psr = psr; + } + // evb64260_eth0_poll(); + } while (command_stat & 0x80000000); + + printf("sent %d byte frame\n", s); + + if((command_stat & (3<<15)) == 3) { + printf("frame had error (stat=%08x)\n", command_stat); + } + } +#endif return 0; } @@ -147,31 +305,197 @@ evb64260_eth0_disable(void) GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x80008000); } +/************************************************************************** +MII utilities - write: write to an MII register via SMI +***************************************************************************/ +int +miiphy_write(unsigned char phy, unsigned char reg, + unsigned short data) +{ + unsigned int temp= (reg<<21) | (phy<<16) | data; + + while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ + + GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); + return 0; +} + +/************************************************************************** +MII utilities - read: read from an MII register via SMI +***************************************************************************/ +int +miiphy_read(unsigned char phy, unsigned char reg, + unsigned short *val) +{ + unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; + + while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ + + GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); + + while(1) { + temp=GTREGREAD(ETHERNET_SMI_REGISTER); + if(temp & (1<<27)) break; /* wait for ReadValid */ + } + *val = temp & 0xffff; + + return 0; +} + +#ifdef DEBUG +/************************************************************************** +MII utilities - dump mii registers +***************************************************************************/ +static void +evb64260_dump_mii(bd_t *bis, unsigned short phy) +{ + printf("mii reg 0 - 3: %04x %04x %04x %04x\n", + miiphy_read_ret(phy, 0x0), + miiphy_read_ret(phy, 0x1), + miiphy_read_ret(phy, 0x2), + miiphy_read_ret(phy, 0x3) + ); + printf(" 4 - 7: %04x %04x %04x %04x\n", + miiphy_read_ret(phy, 0x4), + miiphy_read_ret(phy, 0x5), + miiphy_read_ret(phy, 0x6), + miiphy_read_ret(phy, 0x7) + ); + printf(" 8: %04x\n", + miiphy_read_ret(phy, 0x8) + ); + printf(" 16-19: %04x %04x %04x %04x\n", + miiphy_read_ret(phy, 0x10), + miiphy_read_ret(phy, 0x11), + miiphy_read_ret(phy, 0x12), + miiphy_read_ret(phy, 0x13) + ); + printf(" 20,30: %04x %04x\n", + miiphy_read_ret(phy, 20), + miiphy_read_ret(phy, 30) + ); +} +#endif + /************************************************************************** PROBE - Look for an adapter, this routine's visible to the outside ***************************************************************************/ int evb64260_eth0_probe(bd_t *bis) { + static int initted=0; + unsigned long temp; + int i; + + if(initted) { + GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080); + return 0; + } + + initted=1; #ifdef DEBUG printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", GTREGREAD(COMM_UNIT_ARBITER_CONTROL), GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); #endif - GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); - GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); + + // clear MIB counters + for(i=0;i<255; i++) + temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + REG_OFF +i); + +#ifdef ZUMA_NTL + /* for intel LXT972 */ + + /* led 1: 0x1=txact + led 2: 0xc=link/rxact + led 3: 0x2=rxact (N/C) + strch: 0,2=30 ms, enable */ + miiphy_write(ETHER_PORT_PHY, 20, 0x1c22); + + /* 2.7ns port rise time */ + //miiphy_write(ETHER_PORT_PHY, 30, 0x0<<10); +#else + /* already set up in mpsc.c */ + //GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); /* b400 */ + + /* already set up in sdram_init.S... */ + /* MPSC0, MPSC1, RMII */ + //GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); /* f010 */ +#endif + GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, + ether_port_phy_addr[0] | + (ether_port_phy_addr[1]<<5) | + (ether_port_phy_addr[2]<<10)); /* 2000 */ + + /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) + * 9 - 1: RIFB - interrupt on frame boundaries only + * 6:7 - 00: big endian rx and tx + * 5:2 - 1111: 15 retries */ GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + REG_OFF, - 0x0000303c); - GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, &temp); + (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ + +#ifndef USE_SOFTWARE_CACHE_MANAGEMENT + /* enable rx/tx desc/buffer cache snoop */ + GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + CONFIG_ETHER_PORT*0x20, + &temp); /* f200 */ + temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); + GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + CONFIG_ETHER_PORT*0x20, + temp); +#endif + + /* 31 28 27 24 23 20 19 16 + * 0000 0000 0000 0000 [0004] + * 15 12 11 8 7 4 3 0 + * 1000 1101 0000 0000 [4d00] + * 20 - 0=MII 1=RMII + * 19 - 0=speed autoneg + * 15:14 - framesize 1536 + * 11 - no force link pass + * 10 - 1=disable fctl autoneg + * 8 - override prio ?? */ + temp = 0x00004d00; +#ifndef CONFIG_ETHER_PORT_MII + temp |= (1<<20); // RMII +#endif + /* set En */ + GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + REG_OFF, + temp); /* 2408 */ - /* turn on autonegotiation */ - temp |= 0x00000081; + /* hardcode E1 also? */ + /* -- according to dox, this is safer due to extra pulldowns? */ + GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + 1 * 0x400, + temp); /* 2408 */ + /* wake up MAC */ /* 2400 */ + GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, &temp); + temp |= (1<<7); /* enable port */ +#ifdef USE_MAC_HASH_TABLE + temp |= (1<<12); /* hash size 1/2k */ +#else + temp |= 1; /* promisc */ +#endif GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, temp); - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + REG_OFF, - 0x00104d00); + /* 2400 */ + +#ifdef RESTART_AUTONEG + /* if link is up, restart PHY autoneg - something screwy with FD/HD + * unless we do this */ + if(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF) & 8) { + miiphy_write(ETHER_PORT_PHY,0, + miiphy_read_ret(ETHER_PORT_PHY,0) | (1<<9)); + udelay(10000); /* the EVB's GT takes a while to notice phy + went down and up */ + } +#endif + + printf("Waiting for link up..\n"); + /* wait for link back up */ + while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF) & 8)){ + udelay(10); + } + printf("OK!\n"); /* we're dealing with the first ethernet only for this stripped down * driver */ @@ -209,8 +533,11 @@ evb64260_eth0_probe(bd_t *bis) ð0_rx_desc[(temp+1)%NR].buff_size_byte_count; } - sync(); - + FLUSH_DCACHE((unsigned int)ð0_tx_desc[0], + (unsigned int)ð0_tx_desc[NR]); + FLUSH_DCACHE((unsigned int)ð0_rx_desc[0], + (unsigned int)ð0_rx_desc[NR]); + GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF, (unsigned int) eth0_tx_desc); GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + REG_OFF, @@ -237,8 +564,31 @@ evb64260_eth0_probe(bd_t *bis) *(unsigned int *) ((unsigned int)eth0_rx_desc + 0xc)); #endif +#ifdef DEBUG + evb64260_dump_mii(bis,ETHER_PORT_PHY); +#endif + +#ifdef USE_MAC_HASH_TABLE + { + u8 *b=bis->bi_enetaddr; + u32 macH= (b[0]<<8) | b[1]; + u32 macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; + + /* mode 0, size 0x800 */ + unsigned int hashtable_base =initAddressTable(CONFIG_ETHER_PORT,0,1); + + if(!hashtable_base) { + printf("initAddressTable failed\n"); + return -1; + } + + addAddressTableEntry(CONFIG_ETHER_PORT, macH, macL, 1, 0); + GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + REG_OFF, + hashtable_base); + } +#endif + /* Start Rx*/ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080); - return 0; } diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h index b11a3c2..3c3bc7f 100644 --- a/board/evb64260/eth.h +++ b/board/evb64260/eth.h @@ -51,8 +51,9 @@ typedef struct eth0_rx_desc_struct { #define NT 20 /* Number of Transmit buffers */ #define NR 20 /* Number of Receive buffers */ #define EVB64260_ETH0_INT_THRE 20 -#define CACHE_LINE_SIZE 0 // 32 +// #define CACHE_LINE_SIZE 0 // 32 #define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) // 1600 +#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/ unsigned int EVB64260_ETH0_irq; @@ -72,5 +73,4 @@ int evb64260_eth0_poll(void); int evb64260_eth0_transmit(unsigned int s, volatile char *p); void evb64260_eth0_disable(void); int evb64260_eth0_probe(bd_t *bis); - #endif diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c new file mode 100644 index 0000000..a95bd98 --- /dev/null +++ b/board/evb64260/eth_addrtbl.c @@ -0,0 +1,193 @@ +#include +#include +#include +#include +#include +#include "eth.h" +#include "eth_addrtbl.h" + +#define MAX_NUMBER_OF_ETHERNET_PORTS 3 +#define TRUE 1 +#define FALSE 0 + +#define PRINTF printf + +static u32 addressTableHashMode[ MAX_NUMBER_OF_ETHERNET_PORTS ]; +static u32 addressTableHashSize[ MAX_NUMBER_OF_ETHERNET_PORTS ]; +static addrTblEntry *addressTableBase[ MAX_NUMBER_OF_ETHERNET_PORTS ]; + +static const u32 hashLength[ MAX_NUMBER_OF_ETHERNET_PORTS ] = { + (0x8000), /* 8K * 4 entries */ + (0x8000/16), /* 512 * 4 entries */ +}; + +unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector) +{ + unsigned int tableBase; + int bytes=hashLength[hashSizeSelector] * sizeof(addrTblEntry); + + if(port<0 || port >= MAX_NUMBER_OF_ETHERNET_PORTS) + return 0; + + tableBase=(unsigned int) malloc(bytes+64); + + if(!tableBase) return 0; + + // align to octal byte + if(tableBase&63) tableBase=(tableBase+63) & ~63; + + addressTableHashMode[port] = hashMode; + addressTableHashSize[port] = hashSizeSelector; + addressTableBase[port] = (addrTblEntry *)tableBase; + + memset((void *)tableBase,0,bytes); + + return tableBase; +} + +/* + * ---------------------------------------------------------------------------- + * This function will calculate the hash function of the address. + * depends on the hash mode and hash size. + * Inputs + * macH - the 2 most significant bytes of the MAC address. + * macL - the 4 least significant bytes of the MAC address. + * hashMode - hash mode 0 or hash mode 1. + * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800) + * Outputs + * return the calculated entry. + */ +u32 +hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode) +{ + u32 hashResult; + u32 addrH; + u32 addrL; + u32 addr0; + u32 addr1; + u32 addr2; + u32 addr3; + u32 addrHSwapped; + u32 addrLSwapped; + + + addrH = NIBBLE_SWAPPING_16_BIT( macH ); + addrL = NIBBLE_SWAPPING_32_BIT( macL ); + + addrHSwapped = FLIP_4_BITS( addrH & 0xf ) + + ((FLIP_4_BITS( (addrH >> 4) & 0xf)) << 4) + + ((FLIP_4_BITS( (addrH >> 8) & 0xf)) << 8) + + ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12); + + addrLSwapped = FLIP_4_BITS( addrL & 0xf ) + + ((FLIP_4_BITS( (addrL >> 4) & 0xf)) << 4) + + ((FLIP_4_BITS( (addrL >> 8) & 0xf)) << 8) + + ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12) + + ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16) + + ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20) + + ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24) + + ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28); + + addrH = addrHSwapped; + addrL = addrLSwapped; + + if( hash_mode == 0 ) { + addr0 = (addrL >> 2) & 0x03f; + addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2; + addr2 = (addrL >> 15) & 0x1ff; + addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8); + } else { + addr0 = FLIP_6_BITS( addrL & 0x03f ); + addr1 = FLIP_9_BITS( ((addrL >> 6) & 0x1ff)); + addr2 = FLIP_9_BITS( (addrL >> 15) & 0x1ff); + addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8))); + } + + hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); + + if( HashSize == _8K_TABLE ) { + hashResult = hashResult & 0xffff; + } else { + hashResult = hashResult & 0x07ff; + } + + return( hashResult ); +} + + +/* + * ---------------------------------------------------------------------------- + * This function will add an entry to the address table. + * depends on the hash mode and hash size that was initialized. + * Inputs + * port - ETHERNET port number. + * macH - the 2 most significant bytes of the MAC address. + * macL - the 4 least significant bytes of the MAC address. + * skip - if 1, skip this address. + * rd - the RD field in the address table. + * Outputs + * address table entry is added. + * TRUE if success. + * FALSE if table full + */ +int +addAddressTableEntry( + u32 port, + u32 macH, + u32 macL, + u32 rd, + u32 skip ) +{ + addrTblEntry *entry; + u32 newHi; + u32 newLo; + u32 i; + + newLo = (((macH >> 4) & 0xf) << 15) + | (((macH >> 0) & 0xf) << 11) + | (((macH >> 12) & 0xf) << 7) + | (((macH >> 8) & 0xf) << 3) + | (((macL >> 20) & 0x1) << 31) + | (((macL >> 16) & 0xf) << 27) + | (((macL >> 28) & 0xf) << 23) + | (((macL >> 24) & 0xf) << 19) + | (skip << SKIP_BIT) | (rd << 2) | VALID; + + newHi = (((macL >> 4) & 0xf) << 15) + | (((macL >> 0) & 0xf) << 11) + | (((macL >> 12) & 0xf) << 7) + | (((macL >> 8) & 0xf) << 3) + | (((macL >> 21) & 0x7) << 0); + + /* + * Pick the appropriate table, start scanning for free/reusable + * entries at the index obtained by hashing the specified MAC address + */ + entry = addressTableBase[port]; + entry += hashTableFunction( macH, macL, addressTableHashSize[port], + addressTableHashMode[port] ); + for( i = 0; i < HOP_NUMBER; i++, entry++ ) { + if( !(entry->lo & VALID) /*|| (entry->lo & SKIP)*/ ) { + break; + } else { /* if same address put in same position */ + if( ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8)) + && (entry->hi == newHi) ) + { + break; + } + } + } + + if( i == HOP_NUMBER ) { + PRINTF( "addGT64260addressTableEntry: table section is full\n" ); + return( FALSE ); + } + + /* + * Update the selected entry + */ + entry->hi = newHi; + entry->lo = newLo; + DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE ); + return( TRUE ); +} diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h new file mode 100644 index 0000000..0b515ab --- /dev/null +++ b/board/evb64260/eth_addrtbl.h @@ -0,0 +1,84 @@ +#ifndef _ADDRESS_TABLE_H +#define _ADDRESS_TABLE_H 1 + +/* + * ---------------------------------------------------------------------------- + * addressTable.h - this file has all the declarations of the address table + */ + +#define _8K_TABLE 0 +#define ADDRESS_TABLE_ALIGNMENT 8 +#define HASH_DEFAULT_MODE 14 +#define HASH_MODE 13 +#define HASH_SIZE 12 +#define HOP_NUMBER 12 +#define MAC_ADDRESS_STRING_SIZE 12 +#define MAC_ENTRY_SIZE sizeof(addrTblEntry) +#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000 +#define PROMISCUOUS_MODE 0 +#define SKIP 1<<1 +#define SKIP_BIT 1 +#define VALID 1 + +/* + * ---------------------------------------------------------------------------- + * XXX_MIKE - potential sign-extension bugs lurk here... + */ +#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \ + | (((X) & 0x0f0f0f0f) << 4) ) + +#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \ + | (((X) & 0x00000f0f) << 4) ) + +#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \ + | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) ) + +#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \ + | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \ + | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) ) + +#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \ + | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \ + | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \ + | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) ) + +/* + * V: value we're operating on + * O: offset of rightmost bit in field + * W: width of field to shift + * S: distance to shift left + */ +#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1) +#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S)) +#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S)) + + +/* + * Push to main memory all cache lines associated with + * the specified range of virtual memory addresses + * + * A: Address of first byte in range to flush + * N: Number of bytes to flush + * Note - flush_dcache_range() does a "sync", does NOT invalidate + */ +#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) ) + + + +typedef struct addressTableEntryStruct { + u32 hi; + u32 lo; +} addrTblEntry; + +u32 +uncachedPages( u32 pages ); +u32 +hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode ); + +unsigned int +initAddressTable( u32 port, u32 hashMode, u32 hashSize ); + +int +addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip ); + +#endif /* #ifndef _ADDRESS_TABLE_H */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c index e6ede83..1147f58 100644 --- a/board/evb64260/evb64260.c +++ b/board/evb64260/evb64260.c @@ -36,6 +36,9 @@ #include "mpsc.h" #include "i2c.h" #include "64260.h" +#ifdef ZUMA_NTL +extern void zuma_mbox_init(void); +#endif #undef DEBUG #define MAP_PCI @@ -48,7 +51,15 @@ /* ------------------------------------------------------------------------- */ -/* this is the GT register space location where we want it to be */ +/* this is the current GT register space location */ +/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ + +/* Unfortunately, we cant change it while we are in flash, so we initialize it + * to the "final" value. This means that any debug_led calls before + * board_pre_init wont work right (like in cpu_init_f). + * See also my_remap_gt_regs below. (NTL) + */ + unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; /* ------------------------------------------------------------------------- */ @@ -56,6 +67,9 @@ unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; /* * This is a version of the GT register space remapping function that * doesn't touch globals (meaning, it's ok to run from flash.) + * + * Unfortunately, this has the side effect that a writable + * INTERNAL_REG_BASE_ADDR is impossible. Oh well. */ void @@ -76,6 +90,94 @@ my_remap_gt_regs(u32 cur_loc, u32 new_loc) while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); } +static void +gt_pci_config(void) +{ + /* move PCI stuff out of the way - NTL */ + /* map PCI Host 0 */ + pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE); + + pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0); + pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0); + pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0); + + pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE); + + /* map PCI Host 1 */ + pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE); + + pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0); + pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0); + pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0); + + pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE); + + /* PCI interface settings */ + GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); + GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); + GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); + GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); + + +} + +/* Setup CPU interface paramaters */ +static void +gt_cpu_config(void) +{ + cpu_t cpu = get_cpu_type(); + ulong tmp; + + /* cpu configuration register */ + tmp = GTREGREAD(CPU_CONFIGURATION); + + /* set the AACK delay bit + * see Res#14 */ + tmp |= CPU_CONF_AACK_DELAY; + tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */ + + if (cpu == CPU_750CX) { + tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */ + tmp &= ~CPU_CONF_AP_VALID; + tmp &= ~CPU_CONF_FAST_CLK; /* Yeah. RGF */ + } else { + tmp |= CPU_CONF_DP_VALID; + tmp |= CPU_CONF_AP_VALID; + } + + /* this only works with the MPX bus */ + tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */ + tmp &= ~CPU_CONF_PIPELINE; /* Safer RGF */ + tmp |= CPU_CONF_TA_DELAY; + + GT_REG_WRITE(CPU_CONFIGURATION, tmp); + + /* CPU master control register */ + tmp = GTREGREAD(CPU_MASTER_CONTROL); + + tmp |= CPU_MAST_CTL_ARB_EN; + + if ((cpu == CPU_7400) || + (cpu == CPU_7410) || + (cpu == CPU_7450)) { + + tmp |= CPU_MAST_CTL_CLEAN_BLK; + tmp |= CPU_MAST_CTL_FLUSH_BLK; + + } else { + /* cleanblock must be cleared for CPUs + * that do not support this command + * see Res#1 */ + tmp &= ~CPU_MAST_CTL_CLEAN_BLK; + tmp &= ~CPU_MAST_CTL_FLUSH_BLK; + } + GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); +} + /* * board_pre_init. * @@ -84,9 +186,7 @@ my_remap_gt_regs(u32 cur_loc, u32 new_loc) int board_pre_init(void) { - ulong tmp; uchar sram_boot = 0; - cpu_t cpu = get_cpu_type(); /* * set up the GT the way the kernel wants it @@ -97,6 +197,8 @@ board_pre_init(void) */ my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS); + gt_pci_config(); + /* mask all external interrupt sources */ GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0); GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); @@ -110,16 +212,21 @@ board_pre_init(void) GT_REG_WRITE(CPU_INT_3_MASK, 0); /* now, onto the configuration */ - GT_REG_WRITE(SDRAM_CONFIGURATION, 0xd8e10200); + GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG); /* ----- DEVICE BUS SETTINGS ------ */ /* - * 0 - SRAM + * EVB + * 0 - SRAM * 1 - RTC * 2 - UART * 3 - Flash * boot - BootCS + * + * Zuma + * 0 - Flash + * boot - BootCS */ /* @@ -128,21 +235,35 @@ board_pre_init(void) * on-board sram on the eval board, and updates the correct * registers to boot from the sram. (device0) */ +#ifdef ZUMA_NTL + /* Zuma has no SRAM */ + sram_boot = 0; +#else if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) sram_boot = 1; +#endif if (!sram_boot) - memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDevice1Space(CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDevice2Space(CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDevice3Space(CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + + memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); + memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); + memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); /* configure device timing */ +#ifdef CFG_DEV0_PAR if (!sram_boot) GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); +#endif + +#ifdef CFG_DEV1_PAR GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#endif +#ifdef CFG_DEV2_PAR GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#endif +#ifdef CFG_32BIT_BOOT_PAR /* detect if we are booting from the 32 bit flash */ if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ @@ -153,56 +274,12 @@ board_pre_init(void) GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); } +#else + /* 8 bit boot flash only */ + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); +#endif - /* cpu configuration register */ - tmp = GTREGREAD(CPU_CONFIGURATION); - - /* set the AACK delay bit - * see Res#14 */ - tmp |= CPU_CONF_AACK_DELAY; - - if (cpu == CPU_750CX) { - tmp |= CPU_CONF_DP_VALID; - tmp &= ~CPU_CONF_AP_VALID; - } else { - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - } - - /* this only works with the MPX bus */ - tmp &= ~CPU_CONF_RD_OOO; - tmp &= ~CPU_CONF_PIPELINE; - tmp |= CPU_CONF_TA_DELAY; - - GT_REG_WRITE(CPU_CONFIGURATION, tmp); - - /* CPU master control register */ - tmp = GTREGREAD(CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || - (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - - GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); - - /* PCI interface settings */ - GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); + gt_cpu_config(); /* MPP setup */ GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0); @@ -210,9 +287,8 @@ board_pre_init(void) GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2); GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3); - /* XXX */ - GT_REG_WRITE(GPP_LEVEL_CONTROL, 0x000002c6); - GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x00000102); + GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX); return 0; } @@ -222,6 +298,10 @@ board_pre_init(void) void misc_init_r(bd_t *bd) { + icache_enable(); +#ifdef CFG_L2 + l2cache_enable(); +#endif #ifdef CONFIG_MPSC mpsc_init2(); #endif @@ -233,6 +313,9 @@ misc_init_r(bd_t *bd) // invalidate_bats(); // dcache_disable(); #endif +#ifdef ZUMA_NTL + zuma_mbox_init(); +#endif } void @@ -243,8 +326,8 @@ after_reloc(bd_t *bd, ulong dest_addr) * memory at this point now */ if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) { - memoryMapDevice0Space(CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceBootSpace(CFG_FLASH_BASE, _1M); + memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M); } /* now, jump to the main ppcboot board init code */ @@ -266,16 +349,16 @@ checkboard (void) { int l_type = 0; - printf ("EVB64260\n"); + printf("%s\n", CFG_BOARD_NAME); return (l_type); } /* utility functions */ - void debug_led(int led, int mode) { +#ifndef ZUMA_NTL volatile int *addr; int dummy; @@ -310,6 +393,7 @@ debug_led(int led, int mode) } dummy = *addr; +#endif /* ZUMA_NTL */ } #if (CONFIG_COMMANDS & CFG_CMD_NET) @@ -322,14 +406,7 @@ debug_led(int led, int mode) int eth_init(bd_t *bis) { - static short init_done = 0; - - if (!init_done) { - init_done = 1; - return evb64260_eth0_probe(bis); - } - - return 0; + return evb64260_eth0_probe(bis); } int @@ -355,96 +432,50 @@ eth_halt(void) #endif /* CFG_CMD_NET */ -/* we're not using this right now...btw, it was lifted from the - * galileo code in Dink32 [josh] */ - -#if 0 - void display_mem_map(void) { - unsigned int base,size,width; - /* SDRAM */ - printf("SDRAM\n"); - base = memoryGetBankBaseAddress(BANK0); - size = memoryGetBankSize(BANK0); + int i,j; + unsigned int base,size,width; + /* SDRAM */ + printf("SDRAM\n"); + for(i=0;i<=BANK3;i++) { + base = memoryGetBankBaseAddress(i); + size = memoryGetBankSize(i); if(size !=0) { - printf("BANK0: base - 0x%x\tsize - %d bytes\n",base,size); + printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20); } - base = memoryGetBankBaseAddress(BANK1); - size = memoryGetBankSize(BANK1); - if(size !=0) - { - printf("BANK1: base - 0x%x\tsize - %d bytes\n",base,size); + } + + /* CPU's PCI windows */ + for(i=0;i<=PCI_HOST1;i++) { + printf("\nCPU's PCI %d windows\n", i); + base=pciGetSpaceBase(i,PCI_IO); + size=pciGetSpaceSize(i,PCI_IO); + printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20); + for(j=0;j<=PCI_REGION3;j++) { + base = pciGetSpaceBase(i,j); + size = pciGetSpaceSize(i,j); + printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base, + size>>20); } - base = memoryGetBankBaseAddress(BANK2); - size = memoryGetBankSize(BANK2); - if(size !=0) - { - printf("BANK2: base - 0x%x\tsize - %d bytes\n",base,size); - } - base = memoryGetBankBaseAddress(BANK3); - size = memoryGetBankSize(BANK3); - if(size !=0) - { - printf("BANK3: base - 0x%x\tsize - %d bytes\n",base,size); - } - /* Devices */ - printf("\nDEVICES\n"); - base = memoryGetDeviceBaseAddress(DEVICE0); /* SRAM */ - size = memoryGetDeviceSize(DEVICE0); - width= memoryGetDeviceWidth(DEVICE0) * 8; - printf("SRAM: base - 0x%x\tsize - %d bytes\twidth - %d bits\n", - base, size, width); - base = memoryGetDeviceBaseAddress(DEVICE1); /* RTC */ - size = memoryGetDeviceSize(DEVICE1); - width= memoryGetDeviceWidth(DEVICE1) * 8; - printf("RTC: base - 0x%x\tsize - %d bytes\twidth - %d bits\n", - base, size, width); - base = memoryGetDeviceBaseAddress(DEVICE2); /* UART */ - size = memoryGetDeviceSize(DEVICE2); - width= memoryGetDeviceWidth(DEVICE2) * 8; - printf("UART: base - 0x%x\tsize - %d bytes\twidth - %d bits\n", - base, size, width); - base = memoryGetDeviceBaseAddress(DEVICE3); /* Flash */ - size = memoryGetDeviceSize(DEVICE3); - width= memoryGetDeviceWidth(DEVICE3) * 8; - printf("FLASH: base - 0x%x\tsize - %d bytes\twidth - %d bits\n", - base, size, width); - base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize(BOOT_DEVICE); - width= memoryGetDeviceWidth(BOOT_DEVICE) * 8; - printf("BOOT: base - 0x%x\tsize - %d bytes\twidth - %d bits\n", - base, size, width); - /* CPU's PCI windows */ - printf("\nCPU's PCI 0 windows\n"); - base = pci0GetMemory0Base(); - size = pci0GetMemory0Size(); - printf("MEMORY 0: base - 0x%x\tsize - %d bytes\n",base,size); - base = pci0GetMemory1Base(); - size = pci0GetMemory1Size(); - printf("MEMORY 1: base - 0x%x\tsize - %d bytes\n",base,size); - base = pci0GetMemory2Base(); - size = pci0GetMemory2Size(); - printf("MEMORY 2: base - 0x%x\tsize - %d bytes\n",base,size); - base = pci0GetMemory3Base(); - size = pci0GetMemory3Size(); - printf("MEMORY 3: base - 0x%x\tsize - %d bytes\n",base,size); - - printf("\nCPU's PCI 1 windows\n"); - base = pci1GetMemory0Base(); - size = pci1GetMemory0Size(); - printf("MEMORY 0: base - 0x%x\tsize - %d bytes\n",base,size); - base = pci1GetMemory1Base(); - size = pci1GetMemory1Size(); - printf("MEMORY 1: base - 0x%x\tsize - %d bytes\n",base,size); - base = pci1GetMemory2Base(); - size = pci1GetMemory2Size(); - printf("MEMORY 2: base - 0x%x\tsize - %d bytes\n",base,size); - base = pci1GetMemory3Base(); - size = pci1GetMemory3Size(); - printf("MEMORY 3: base - 0x%x\tsize - %d bytes\n",base,size); + } + + /* Devices */ + printf("\nDEVICES\n"); + for(i=0;i<=DEVICE3;i++) { + base = memoryGetDeviceBaseAddress(i); + size = memoryGetDeviceSize(i); + width= memoryGetDeviceWidth(i) * 8; + printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", + i, base, size>>20, width); + } + + /* Bootrom */ + base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */ + size = memoryGetDeviceSize(BOOT_DEVICE); + width= memoryGetDeviceWidth(BOOT_DEVICE) * 8; + printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", + base, size>>20, width); } - -#endif diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c index e399c88..96f522d 100644 --- a/board/evb64260/flash.c +++ b/board/evb64260/flash.c @@ -31,6 +31,13 @@ #include #include #include +#include "intel_flash.h" + +#undef DEBUG + +/* Intel flash commands */ +int flash_erase_intel(flash_info_t *info, int s_first, int s_last); +int write_word_intel(bank_addr_t addr, bank_word_t value); flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -55,26 +62,34 @@ flash_init (void) for (i=0; i>20, base); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + if(i==1) { + printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", + base, size_b1, size_b1<<20); + } + break; + } + size_b1+=size; + base+=size; } -#endif flash_size = size_b0 + size_b1; return flash_size; @@ -86,33 +101,42 @@ static void flash_get_offsets (ulong base, flash_info_t *info) { int i; + int sector_size; + + if(!info->sector_count) return; /* set up sector start address table */ - if (info->flash_id & FLASH_AM040) { + switch(info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + case FLASH_28F128JA3: + case FLASH_28F640J3A: + case FLASH_RAM: /* this chip has uniformly spaced sectors */ + sector_size=info->size/info->sector_count; for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; + info->start[i] = base + (i * sector_size); + break; + default: + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } } } - } /*----------------------------------------------------------------------- @@ -130,6 +154,7 @@ flash_print_info (flash_info_t *info) switch (info->flash_id & FLASH_VENDMASK) { case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; default: printf ("Unknown Vendor "); break; } @@ -161,13 +186,30 @@ flash_print_info (flash_info_t *info) case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); break; + case FLASH_28F640J3A: + printf ("28F640J3A (64 Mbit)\n"); + break; + case FLASH_28F128JA3: + printf ("28F128JA3 (128 Mbit)\n"); + break; + case FLASH_ROM: + printf ("ROM\n"); + break; + case FLASH_RAM: + printf ("RAM\n"); + break; default: printf ("Unknown Chip Type\n"); break; } - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); + if((info->size >> 20) > 0 ) { + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + } else { + printf (" Size: %ld kB in %d Sectors\n", + info->size >> 10, info->sector_count); + } printf (" Sector Start Addresses:"); for (i=0; isector_count; ++i) { @@ -193,100 +235,217 @@ flash_print_info (flash_info_t *info) * The following code cannot be run from FLASH! */ +static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd) +{ + /* supports 1x8, 1x16, and 2x16 */ + /* 2x8 and 4x8 are not supported */ + if(width==4) { + /* assuming chips are in 16 bit mode */ + /* 2x16 */ + unsigned long cmd32=(cmd<<16)|cmd; + *(volatile unsigned long *)(addr+offset*2)=cmd32; + } else { + /* 1x16 or 1x8 */ + *(volatile unsigned char *)(addr+offset)=cmd; + } +} + static ulong flash_get_size (int fl_width, vu_long *addr, flash_info_t *info) { short i; - volatile unsigned char value; - volatile char *caddr = (char *)addr; - ulong base = (ulong)addr; + volatile unsigned char *caddr = (unsigned char *)addr; + volatile unsigned short *saddr = (unsigned short *)addr; + volatile unsigned long *laddr = (unsigned long *)addr; + char old[2], save; + ulong id, manu, base = (ulong)addr; + + info->width=fl_width; + + save = *caddr; + + flash_cmd(fl_width,caddr,0,0xf0); + flash_cmd(fl_width,caddr,0,0xf0); + + udelay(10); + + old[0] = caddr[0]; + old[1] = caddr[1]; + + + if(old[0]!=0xf0) { + flash_cmd(fl_width,caddr,0,0xf0); + flash_cmd(fl_width,caddr,0,0xf0); + + udelay(10); + + if(*caddr==0xf0) { + // this area is ROM + *caddr=save; + info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets(base, info); + return info->size; + } + } else { + *caddr=0; + + udelay(10); + + if(*caddr==0) { + // this area is RAM + *caddr=save; + info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets(base, info); + return info->size; + } + flash_cmd(fl_width,caddr,0,0xf0); + + udelay(10); + } /* Write auto select command: read Manufacturer ID */ - caddr[0x555] = 0xAA; - caddr[0x2AA] = 0x55; - caddr[0x555] = 0x90; + flash_cmd(fl_width,caddr,0x555,0xAA); + flash_cmd(fl_width,caddr,0x2AA,0x55); + flash_cmd(fl_width,caddr,0x555,0x90); udelay(10); - value = caddr[0]; + if ((caddr[0] == old[0]) && + (caddr[1] == old[1])) { + + // this area is ROM + info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets(base, info); + return info->size; +#ifdef DEBUG + } else { + printf("%px%d: %02x:%02x -> %02x:%02x\n", + caddr, fl_width, old[0], old[1], + caddr[0], caddr[1]); +#endif + } - switch (value) { - case 0x1: - info->flash_id = FLASH_MAN_AMD; + switch(fl_width) { + case 1: + manu = caddr[0]; + manu |= manu<<16; + id = caddr[1]; break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; + case 2: + manu = saddr[0]; + manu |= manu<<16; + id = saddr[1]; + id |= id<<16; break; - case MT_MANUFACT: - info->flash_id = FLASH_MAN_MT; + case 4: + manu = laddr[0]; + id = laddr[1]; break; - default: - printf("Unknown Mfr: 0x%x\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = caddr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ + } + +#ifdef DEBUG + printf("\n%08lx:%08lx:%08lx\n", base, manu, id); + printf("%08x %08x %08x %08x\n", + laddr[0],laddr[1],laddr[2],laddr[3]); +#endif + + switch (manu) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("Unknown Mfr [%08lx]:%08lx\n", manu, id); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + switch (id) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ #if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ #endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x80000; + break; + + case INTEL_ID_28F640JA3: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */ + if(info->width==4) info->size*=2; /* 2x16 */ + break; + + case INTEL_ID_28F128JA3: + info->flash_id += FLASH_28F128JA3; + info->sector_count = 128; + info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */ + if(info->width==4) info->size*=2; /* 2x16 */ + break; + + default: + printf("Unknown id %lx:[%lx]\n", manu, id); + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ } @@ -325,7 +484,14 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info) /* read sector protection at sector address, (A7 .. A0)=0x02 */ /* D0 = 1 if protected */ caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; + saddr = (volatile unsigned short *)(info->start[i]); + laddr = (volatile unsigned long *)(info->start[i]); + if(info->width==1) + info->protect[i] = caddr[2] & 1; + else if(info->width==2) + info->protect[i] = saddr[2] & 1; + else + info->protect[i] = laddr[2] & 1; } /* @@ -334,7 +500,7 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info) if (info->flash_id != FLASH_UNKNOWN) { caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ + flash_cmd(fl_width,caddr,0,0xF0); /* reset bank */ } return (info->size); @@ -347,6 +513,16 @@ flash_erase (flash_info_t *info, int s_first, int s_last) int flag, prot, sect, l_sect; ulong start, now, last; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + for (sect = s_first; sect<=s_last; sect++) { + int sector_size=info->size/info->sector_count; + addr = (char *)(info->start[sect]); + memset((void *)addr, 0, sector_size); + } + return 0; + } + if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { printf ("- missing\n"); @@ -356,12 +532,20 @@ flash_erase (flash_info_t *info, int s_first, int s_last) return 1; } + if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) { + return flash_erase_intel(info, + (unsigned short)s_first, + (unsigned short)s_last); + } + +#if 0 if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); return 1; } +#endif prot = 0; for (sect=s_first; sect<=s_last; ++sect) { @@ -382,17 +566,17 @@ flash_erase (flash_info_t *info, int s_first, int s_last) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x80; - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; + flash_cmd(info->width,addr,0x555,0xAA); + flash_cmd(info->width,addr,0x2AA,0x55); + flash_cmd(info->width,addr,0x555,0x80); + flash_cmd(info->width,addr,0x555,0xAA); + flash_cmd(info->width,addr,0x2AA,0x55); /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr = (char *)(info->start[sect]); - addr[0] = 0x30; + flash_cmd(info->width,addr,0,0x30); l_sect = sect; } } @@ -413,6 +597,7 @@ flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; addr = (volatile unsigned char *)(info->start[l_sect]); + /* broken for 2x16: TODO */ while ((addr[0] & 0x80) != 0x80) { if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); @@ -428,7 +613,8 @@ flash_erase (flash_info_t *info, int s_first, int s_last) DONE: /* reset to read mode */ addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ + flash_cmd(info->width,addr,0,0xf0); + flash_cmd(info->width,addr,0,0xf0); printf (" done\n"); return 0; @@ -441,12 +627,21 @@ DONE: * 2 - Flash not erased */ +/* broken for 2x16: TODO */ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; + if(info->width==4) return 1; + + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + memcpy((void *)addr, src, cnt); + return 0; + } + wp = (addr & ~3); /* get lower word aligned address */ /* @@ -512,6 +707,7 @@ write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ +/* broken for 2x16: TODO */ static int write_word (flash_info_t *info, ulong dest, ulong data) { @@ -519,6 +715,23 @@ write_word (flash_info_t *info, ulong dest, ulong data) ulong start; int flag, i; + if(info->width==4) return 1; + + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + *(unsigned long *)dest=data; + return 0; + } + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + unsigned short low = data & 0xffff; + unsigned short hi = (data >> 16) & 0xffff; + int ret = write_word_intel((bank_addr_t)dest, hi); + + if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low); + + return ret; + } + /* Check if Flash is (sufficiently) erased */ if ((*((vu_long *)dest) & data) != data) { return (2); diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c new file mode 100644 index 0000000..b053382 --- /dev/null +++ b/board/evb64260/intel_flash.c @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00 + */ + +#include +#include +#include +#include +#include "intel_flash.h" + + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +static void +bank_reset(flash_info_t *info, int sect) +{ + bank_addr_t addrw, eaddrw; + + addrw = (bank_addr_t)info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD(addrw); + + while (addrw < eaddrw) { +#ifdef FLASH_DEBUG + printf(" writing reset cmd to addr 0x%08lx\n", + (unsigned long)addrw); +#endif + *addrw = BANK_CMD_RST; + addrw++; + } +} + +static void +bank_erase_init(flash_info_t *info, int sect) +{ + bank_addr_t addrw, saddrw, eaddrw; + int flag; + +#ifdef FLASH_DEBUG + printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); + printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); + printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); + printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); + printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); + printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); + printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); +#endif + + saddrw = (bank_addr_t)info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD(saddrw); + +#ifdef FLASH_DEBUG + printf("erasing sector %d, start addr = 0x%08lx " + "(bank next word addr = 0x%08lx)\n", sect, + (unsigned long)saddrw, (unsigned long)eaddrw); +#endif + + /* Disable intrs which might cause a timeout here */ + flag = disable_interrupts(); + + for (addrw = saddrw; addrw < eaddrw; addrw++) { +#ifdef FLASH_DEBUG + printf(" writing erase cmd to addr 0x%08lx\n", + (unsigned long)addrw); +#endif + *addrw = BANK_CMD_ERASE1; + *addrw = BANK_CMD_ERASE2; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); +} + +static int +bank_erase_poll(flash_info_t *info, int sect) +{ + bank_addr_t addrw, saddrw, eaddrw; + int sectdone, haderr; + + saddrw = (bank_addr_t)info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD(saddrw); + + sectdone = 1; + haderr = 0; + + for (addrw = saddrw; addrw < eaddrw; addrw++) { + bank_word_t stat = *addrw; + +#ifdef FLASH_DEBUG + printf(" checking status at addr " + "0x%08x [0x%08x]\n", + (unsigned long)addrw, stat); +#endif + if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) + sectdone = 0; + else if ((stat & BANK_STAT_ERR) != 0) { + printf(" failed on sector %d " + "(stat = 0x%08x) at " + "address 0x%p\n", + sect, stat, addrw); + *addrw = BANK_CMD_CLR_STAT; + haderr = 1; + } + } + + if (haderr) + return (-1); + else + return (sectdone); +} + +int +write_word_intel(bank_addr_t addr, bank_word_t value) +{ + bank_word_t stat; + ulong start; + int flag, retval; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = BANK_CMD_PROG; + + *addr = value; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + retval = 0; + + /* data polling for D7 */ + start = get_timer (0); + do { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + retval = 1; + goto done; + } + stat = *addr; + } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); + + if ((stat & BANK_STAT_ERR) != 0) { + printf("flash program failed (stat = 0x%08lx) " + "at address 0x%08lx\n", (ulong)stat, (ulong)addr); + *addr = BANK_CMD_CLR_STAT; + retval = 3; + } + +done: + /* reset to read mode */ + *addr = BANK_CMD_RST; + + return (retval); +} + +/*----------------------------------------------------------------------- + */ + +int +flash_erase_intel(flash_info_t *info, int s_first, int s_last) +{ + int prot, sect, haderr; + ulong start, now, last; + +#ifdef FLASH_DEBUG + printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" + " Bank # %d: ", s_last - s_first + 1, s_first, s_last, + (info - flash_info) + 1); + flash_print_info(info); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sector%s will not be erased!\n", + prot, (prot > 1 ? "s" : "")); + } + + start = get_timer (0); + last = 0; + haderr = 0; + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + ulong estart; + int sectdone; + + bank_erase_init(info, sect); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + estart = get_timer(start); + + do { + now = get_timer(start); + + if (now - estart > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (sect %d)\n", sect); + haderr = 1; + break; + } + +#ifndef FLASH_DEBUG + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } +#endif + + sectdone = bank_erase_poll(info, sect); + + if (sectdone < 0) { + haderr = 1; + break; + } + + } while (!sectdone); + + if (haderr) + break; + } + } + + if (haderr > 0) + printf (" failed\n"); + else + printf (" done\n"); + + /* reset to read mode */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + bank_reset(info, sect); + } + } + return haderr; +} diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h new file mode 100644 index 0000000..dc2aa00 --- /dev/null +++ b/board/evb64260/intel_flash.h @@ -0,0 +1,160 @@ +/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ + +/* + * acceptable chips types are: + * + * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A + */ + +/* register addresses, valid only following an CHIP_CMD_RD_ID command */ +#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ +#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ +#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ +#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ + +/* Commands */ +#define CHIP_CMD_RST 0xFF /* reset flash */ +#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ +#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ +#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ +#define CHIP_CMD_PROG 0x40 /* program word command */ +#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ +#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ +#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ +#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ +#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ +#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ +#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ + +/* status register bits */ +#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ +#define CHIP_STAT_VPPS 0x08 /* VPP Status */ +#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ +#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ +#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ +#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ + +#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ + CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) + +/* ID and Lock Configuration */ +#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ +#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ +#define CHIP_RD_ID_DEV CFG_FLASH_ID + +/* dimensions */ +#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ +#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ +#define CHIP_NBLOCKS 128 +#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ +#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) + +/********************** DEFINES for Hymod Flash ******************************/ + +/* + * The hymod board has 2 x 28F320J5 chips running in + * 16 bit mode, for a 32 bit wide bank. + */ + +typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ +typedef volatile bank_word_t *bank_addr_t; +typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ + +#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ +#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ + +#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) +#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) +#define BANK_NBLOCKS CHIP_NBLOCKS +#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) +#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) + +#define MAX_BANKS 1 /* only one bank possible */ + +/* align bank addresses and sizes to bank word boundaries */ +#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_WIDTH - 1))) +#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ + (bank_size_t)(s) + (BANK_WIDTH - 1))) + +/* align bank addresses and sizes to bank block boundaries */ +#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_BLKSZ - 1))) +#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ + (bank_size_t)(s) + (BANK_BLKSZ - 1))) + +/* align bank addresses and sizes to bank boundaries */ +#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_SIZE - 1))) +#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ + (bank_size_t)(s) + (BANK_SIZE - 1))) + +/* add an offset to a bank address */ +#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ + (bank_size_t)(o)) + +/* get base address of bank b, given flash base address a */ +#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + (bank_size_t)(b) * BANK_SIZE) + +/* adjust a bank address to start of next word, block or bank */ +#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ + BANK_WIDTH) +#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ + BANK_BLKSZ) +#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + BANK_SIZE) + +/* get bank address of chip register r given a bank base address a */ +#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + ((bank_size_t)(r) << BANK_WSHIFT)) + +/* make a bank address for each chip register address */ + +#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) +#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) +#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) +#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) + +/* + * replicate a chip cmd/stat/rd value into each byte position within a word + * so that multiple chips are accessed in a single word i/o operation + * + * this must be as wide as the bank_word_t type, and take into account the + * chip width and bank layout + */ + +#define BANK_FILL_WORD(o) ((bank_word_t)(o)) + +/* make a bank word value for each chip cmd/stat/rd value */ + +/* Commands */ +#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) +#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) +#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) +#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) +#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) +#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) +#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) +#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) +#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) +#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) +#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) + +/* status register bits */ +#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) +#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) +#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) +#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) +#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) +#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) +#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) + +#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) + +/* ID and Lock Configuration */ +#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) +#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) +#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c index 9f304b6..ef924de 100644 --- a/board/evb64260/memory.c +++ b/board/evb64260/memory.c @@ -17,29 +17,27 @@ * OUTPUT: N/A * RETURNS: Memory bank base address. *********************************************************************/ -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) +static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank) { - unsigned int base; - unsigned int regOffset; - switch (bank) { - case BANK0: - regOffset = SCS_0_LOW_DECODE_ADDRESS; - break; - case BANK1: - regOffset = SCS_1_LOW_DECODE_ADDRESS; - break; - case BANK2: - regOffset = SCS_2_LOW_DECODE_ADDRESS; - break; - case BANK3: - regOffset = SCS_3_LOW_DECODE_ADDRESS; - break; - default: - regOffset = SCS_0_LOW_DECODE_ADDRESS; /* default value */ - break; + case BANK0: + return SCS_0_LOW_DECODE_ADDRESS; + case BANK1: + return SCS_1_LOW_DECODE_ADDRESS; + case BANK2: + return SCS_2_LOW_DECODE_ADDRESS; + case BANK3: + return SCS_3_LOW_DECODE_ADDRESS; } + return SCS_0_LOW_DECODE_ADDRESS; /* default value */ +} + +unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) +{ + unsigned int base; + unsigned int regOffset=memoryGetBankRegOffset(bank); + GT_REG_READ(regOffset,&base); base = base << 20; return base; @@ -54,33 +52,35 @@ unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) * OUTPUT: N/A * RETURNS: Device base address. *********************************************************************/ -unsigned int memoryGetDeviceBaseAddress(DEVICE device) +static unsigned int memoryGetDeviceRegOffset(DEVICE device) { - unsigned int regBase; - unsigned int regOffset; - switch (device) { - case DEVICE0: - regOffset = CS_0_LOW_DECODE_ADDRESS; - break; - case DEVICE1: - regOffset = CS_1_LOW_DECODE_ADDRESS; - break; - case DEVICE2: - regOffset = CS_2_LOW_DECODE_ADDRESS; - break; - case DEVICE3: - regOffset = CS_3_LOW_DECODE_ADDRESS; - break; - case BOOT_DEVICE: - regOffset = BOOTCS_LOW_DECODE_ADDRESS; - break; - default: - regOffset = CS_0_LOW_DECODE_ADDRESS; /* default value */ - break; + case DEVICE0: + return CS_0_LOW_DECODE_ADDRESS; + case DEVICE1: + return CS_1_LOW_DECODE_ADDRESS; + case DEVICE2: + return CS_2_LOW_DECODE_ADDRESS; + case DEVICE3: + return CS_3_LOW_DECODE_ADDRESS; + case BOOT_DEVICE: + return BOOTCS_LOW_DECODE_ADDRESS; } + return CS_0_LOW_DECODE_ADDRESS; /* default value */ +} + +unsigned int memoryGetDeviceBaseAddress(DEVICE device) +{ + unsigned int regBase; + unsigned int regEnd; + unsigned int regOffset=memoryGetDeviceRegOffset(device); + GT_REG_READ(regOffset, ®Base); + GT_REG_READ(regOffset+8, ®End); + + if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ + regBase = regBase << 20; return regBase; } @@ -96,26 +96,9 @@ unsigned int memoryGetDeviceBaseAddress(DEVICE device) unsigned int memoryGetBankSize(MEMORY_BANK bank) { unsigned int size,base; - unsigned int highAddress; unsigned int highValue; - switch (bank) - { - case BANK0: - highAddress = SCS_0_HIGH_DECODE_ADDRESS; - break; - case BANK1: - highAddress = SCS_1_HIGH_DECODE_ADDRESS; - break; - case BANK2: - highAddress = SCS_2_HIGH_DECODE_ADDRESS; - break; - case BANK3: - highAddress = SCS_3_HIGH_DECODE_ADDRESS; - break; - default: - highAddress = SCS_0_HIGH_DECODE_ADDRESS; /* default value */ - break; - } + unsigned int highAddress=memoryGetBankRegOffset(bank)+8; + base = memoryGetBankBaseAddress(bank); GT_REG_READ(highAddress,&highValue); highValue = (highValue + 1) << 20; @@ -137,39 +120,19 @@ unsigned int memoryGetBankSize(MEMORY_BANK bank) unsigned int memoryGetDeviceSize(DEVICE device) { unsigned int size,base; - unsigned int highAddress; unsigned int highValue; + unsigned int highAddress=memoryGetDeviceRegOffset(device)+8; - switch (device) - { - case DEVICE0: - highAddress = CS_0_HIGH_DECODE_ADDRESS; - break; - case DEVICE1: - highAddress = CS_1_HIGH_DECODE_ADDRESS; - break; - case DEVICE2: - highAddress = CS_2_HIGH_DECODE_ADDRESS; - break; - case DEVICE3: - highAddress = CS_3_HIGH_DECODE_ADDRESS; - break; - case BOOT_DEVICE: - highAddress = BOOTCS_HIGH_DECODE_ADDRESS; - break; - default: - highAddress = CS_0_HIGH_DECODE_ADDRESS; /* default value */ - break; - } base = memoryGetDeviceBaseAddress(device); GT_REG_READ(highAddress,&highValue); if (highValue == 0xfff) { - size = (~base) + 1; + size = (~base) + 1; /* what the heck is this? */ return size; } else highValue = (highValue + 1) << 20; + if(base > highValue) size=0; else @@ -209,373 +172,53 @@ unsigned int memoryGetDeviceWidth(DEVICE device) } } -/******************************************************************** -* memoryMapBank0 - Sets new bases and boundaries for memory banks 0 -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It is the programmer`s responsibility to make sure -* there are no conflicts with other memory spaces!!! -* - If a bank needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int bank0Base - required bank 0 base address. -* unsigned int bank0Length - required bank 0 size. -* RETURNS: true on success, false on failure or if one of the parameters is -* wrong. -*********************************************************************/ -bool memoryMapBank0(unsigned int bank0Base,unsigned int bank0Length) +bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength) { - unsigned int memBank0Base , bank0Top; - unsigned int mainBank0Top = bank0Base + bank0Length; - unsigned int currentLow; - unsigned int baseOld; - - GT_REG_READ(SCS_0_LOW_DECODE_ADDRESS,¤tLow); - baseOld = currentLow << 20; - memBank0Base = bank0Base >> 20; - memBank0Base = memBank0Base & 0xffff; - bank0Top = mainBank0Top >> 20; - if ((bank0Base >= baseOld) && (baseOld < mainBank0Top)) - { - GT_REG_WRITE(SCS_0_LOW_DECODE_ADDRESS,memBank0Base); - GT_REG_WRITE(SCS_0_HIGH_DECODE_ADDRESS,bank0Top - 1); - return true; - } - else - { - GT_REG_WRITE(SCS_0_LOW_DECODE_ADDRESS,0xffff); - if(bank0Length != 0) - { - GT_REG_WRITE(SCS_0_HIGH_DECODE_ADDRESS,bank0Top - 1); - GT_REG_WRITE(SCS_0_LOW_DECODE_ADDRESS,memBank0Base); - } - else - { - GT_REG_WRITE(SCS_0_HIGH_DECODE_ADDRESS,0x0); - } - return true; - } -} + unsigned int low=0xfff; + unsigned int high=0x0; + unsigned int regOffset=memoryGetBankRegOffset(bank); -/******************************************************************** -* memoryMapBank1 - Sets new bases and boundaries for memory banks 1 -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It is the programmer`s responsibility to make sure -* there are no conflicts with other memory spaces!!! -* - If a bank needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int bank1Base - required bank 0 base address. -* unsigned int bank1Length - required bank 0 size. -* RETURNS: true on success, false on failure or if one of the parameters is -* wrong. -*********************************************************************/ -bool memoryMapBank1(unsigned int bank1Base,unsigned int bank1Length) -{ - unsigned int memBank1Base , bank1Top; - unsigned int mainBank1Top = bank1Base + bank1Length; - unsigned int currentLow; - unsigned int baseOld; - - GT_REG_READ(SCS_1_LOW_DECODE_ADDRESS,¤tLow); - baseOld = currentLow << 20; - memBank1Base = bank1Base >> 20; - memBank1Base = memBank1Base & 0xffff; - bank1Top = mainBank1Top >> 20; - if ((bank1Base >= baseOld) && (baseOld < mainBank1Top)) - { - GT_REG_WRITE(SCS_1_LOW_DECODE_ADDRESS,memBank1Base); - GT_REG_WRITE(SCS_1_HIGH_DECODE_ADDRESS,bank1Top - 1); - return true; + if(bankLength!=0) { + low = (bankBase >> 20) & 0xffff; + high=((bankBase+bankLength)>>20)-1; } - else - { - GT_REG_WRITE(SCS_1_LOW_DECODE_ADDRESS,0xffff); - if(bank1Length != 0) - { - GT_REG_WRITE(SCS_1_HIGH_DECODE_ADDRESS,bank1Top - 1); - GT_REG_WRITE(SCS_1_LOW_DECODE_ADDRESS,memBank1Base); - } - else - { - GT_REG_WRITE(SCS_1_HIGH_DECODE_ADDRESS,0x0); - } - return true; - } -} -/******************************************************************** -* memoryMapBank2 - Sets new bases and boundaries for memory bank 2. -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It`s the programmer`s responsibility to make sure there -* are no conflicts with other memory spaces!!! -* - If a bank needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int bank2Base - required bank 2 base address. -* unsigned int bank2Length - required bank 2 size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapBank2(unsigned int bank2Base,unsigned int bank2Length) -{ - unsigned int memBank2Base , bank2Top; - unsigned int mainBank2Top = bank2Base + bank2Length; - unsigned int currentLow; - unsigned int baseOld; - - GT_REG_READ(SCS_2_LOW_DECODE_ADDRESS,¤tLow); - baseOld = currentLow << 20; - memBank2Base = bank2Base >> 20; - memBank2Base = (memBank2Base & 0xffff) | (currentLow & 0xffff0000); - bank2Top = mainBank2Top >> 20; - if ((bank2Base >= baseOld) && (baseOld < mainBank2Top)) - { - GT_REG_WRITE(SCS_2_LOW_DECODE_ADDRESS,memBank2Base); - GT_REG_WRITE(SCS_2_HIGH_DECODE_ADDRESS,bank2Top - 1); - return true; - } - else +#ifdef DEBUG { - GT_REG_WRITE(SCS_2_LOW_DECODE_ADDRESS,0xffff); - if(bank2Length != 0) - { - GT_REG_WRITE(SCS_2_HIGH_DECODE_ADDRESS,bank2Top - 1); - GT_REG_WRITE(SCS_2_LOW_DECODE_ADDRESS,memBank2Base); - } - else - { - GT_REG_WRITE(SCS_2_HIGH_DECODE_ADDRESS,0x0); - } - return true; - } -} + unsigned int oldLow, oldHigh; + GT_REG_READ(regOffset,&oldLow); + GT_REG_READ(regOffset+8,&oldHigh); -/******************************************************************** -* memoryMapBank3 - Sets new bases and boundaries for memory bank 3. -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It`s the programmer`s responsibility to make sure there -* are no conflicts with other memory spaces!!! -* - If a bank needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int bank3Base - required bank 3 base address. -* unsigned int bank3Length - required bank 3 size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapBank3(unsigned int bank3Base,unsigned int bank3Length) -{ - - unsigned int memBank3Base , bank3Top; - unsigned int mainBank3Top = bank3Base + bank3Length; - unsigned int currentLow; - unsigned int baseOld; - - GT_REG_READ(SCS_3_LOW_DECODE_ADDRESS,¤tLow); - baseOld = currentLow << 20; - memBank3Base = bank3Base >> 20; - memBank3Base = (memBank3Base & 0xffff) | (currentLow & 0xffff0000); - bank3Top = mainBank3Top >> 20; - if ((bank3Base >= baseOld) && (baseOld < mainBank3Top)) - { - GT_REG_WRITE(SCS_3_LOW_DECODE_ADDRESS,memBank3Base); - GT_REG_WRITE(SCS_3_HIGH_DECODE_ADDRESS,bank3Top - 1); - return true; - } - else - { - GT_REG_WRITE(SCS_3_LOW_DECODE_ADDRESS,0xffff); - if(bank3Length != 0) - { - GT_REG_WRITE(SCS_3_HIGH_DECODE_ADDRESS,bank3Top - 1); - GT_REG_WRITE(SCS_3_LOW_DECODE_ADDRESS,memBank3Base); - } - else - { - GT_REG_WRITE(SCS_3_HIGH_DECODE_ADDRESS,0x0); - } - return true; - } -} - -/******************************************************************** -* memoryMapDevice0Space - Sets new bases and boundaries for device 0. -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It`s the programmer`s responsibility to make sure -* there are no conflicts with other memory spaces!!! -* - If a device needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int device0Base - required cs_0 base address. -* unsigned int device0Length - required cs_0 size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapDevice0Space(unsigned int device0Base,unsigned int device0Length) -{ - unsigned int bank0Base,bank0Top; - unsigned int deviceBank0Top = (unsigned int)(device0Base + device0Length); - - bank0Base = device0Base >> 20; - bank0Top = deviceBank0Top >> 20; - GT_REG_WRITE(CS_0_LOW_DECODE_ADDRESS,0xffff); - if(device0Length != 0) - { - GT_REG_WRITE(CS_0_HIGH_DECODE_ADDRESS,bank0Top -1); - GT_REG_WRITE(CS_0_LOW_DECODE_ADDRESS,bank0Base); + printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high); } - else - { - GT_REG_WRITE(CS_0_HIGH_DECODE_ADDRESS,0x0); - } - return true; -} +#endif -/******************************************************************** -* memoryMapDevice1Space - Sets new bases and boundaries for device 1. -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It`s the programmer`s responsibility to make sure there -* are no conflicts with other memory spaces!!! -* - If a device needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int device1Base - required cs_1 base address. -* unsigned int device1Length - required cs_1 size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapDevice1Space(unsigned int device1Base,unsigned int device1Length) -{ - unsigned int bank1Base,bank1Top; - unsigned int deviceBank1Top = (unsigned int)(device1Base + device1Length); + GT_REG_WRITE(regOffset,low); + GT_REG_WRITE(regOffset+8,high); - bank1Base = device1Base >> 20; - bank1Top = deviceBank1Top >> 20; - GT_REG_WRITE(CS_1_LOW_DECODE_ADDRESS,0xffff); - if(device1Length != 0) - { - GT_REG_WRITE(CS_1_HIGH_DECODE_ADDRESS,bank1Top -1); - GT_REG_WRITE(CS_1_LOW_DECODE_ADDRESS,bank1Base); - } - else - { - GT_REG_WRITE(CS_1_HIGH_DECODE_ADDRESS,0x0); - } return true; } - -/******************************************************************** -* memoryMapDevice2Space - Sets new bases and boundaries for device 2. -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It`s the programmer`s responsibility to make sure there -* are no conflicts with other memory spaces!!! -* - If a device needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int device2Base - required cs_2 base address. -* unsigned int device2Length - required cs_2 size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapDevice2Space(unsigned int device2Base,unsigned int device2Length) +bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength) { - unsigned int bank2Base,bank2Top; - unsigned int deviceBank2Top = (unsigned int)(device2Base + device2Length); - - bank2Base = device2Base >> 20; - bank2Top = deviceBank2Top >> 20; - GT_REG_WRITE(CS_2_LOW_DECODE_ADDRESS,0xffff); - if(device2Length != 0) - { - GT_REG_WRITE( CS_2_HIGH_DECODE_ADDRESS, bank2Top - 1); - GT_REG_WRITE(CS_2_LOW_DECODE_ADDRESS,bank2Base); + /* TODO: what are appropriate "unmapped" values? */ + unsigned int low=0xfff; + unsigned int high=0x0; + unsigned int regOffset=memoryGetDeviceRegOffset(device); + + if(deviceLength != 0) { + low=deviceBase>>20; + high=((deviceBase+deviceLength)>>20)-1; + } else { + /* big problems in here... */ + /* this will HANG */ } - else - { - GT_REG_WRITE(CS_2_HIGH_DECODE_ADDRESS,0x0); - } - return true; -} - - -/******************************************************************** -* memoryMapDevice3Space - Sets new bases and boundaries for device: 3 -* - Pay attention to the PCI mappings and make sure to -* coordinate between the two interfaces!!! -* - It is the programmer`s responsibility to make sure -* there are no conflicts with other memory spaces!!! -* - If a device needs to be closed , it gives the LOW max -* value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int device3Base - required cs_3 base address. -* unsigned int device3Length - required cs_3 size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapDevice3Space(unsigned int device3Base,unsigned int device3Length) -{ - unsigned int bank3Base,bank3Top; - unsigned int deviceBank3Top = (unsigned int)(device3Base + device3Length); - bank3Base = device3Base >> 20; - bank3Top = deviceBank3Top >> 20; - GT_REG_WRITE(CS_3_LOW_DECODE_ADDRESS,0xffff); - if(device3Length != 0) - { - GT_REG_WRITE( CS_3_HIGH_DECODE_ADDRESS,bank3Top - 1); - GT_REG_WRITE(CS_3_LOW_DECODE_ADDRESS,bank3Base); - } - else - { - GT_REG_WRITE( CS_3_HIGH_DECODE_ADDRESS, 0x0); - } + GT_REG_WRITE(regOffset,low); + GT_REG_WRITE(regOffset+8,high); + return true; } -/******************************************************************** -* memoryMapDeviceBootSpace - Sets new bases and boundaries for device: boot -* - Pay attention to the PCI mappings and make sure -* to coordinate between the two interfaces!!! -* - It is the programmer`s responsibility to make sure -* there are no conflicts with other memory spaces!!! -* - If a device needs to be closed , it gives the LOW -* max value (0xffff) and to the HIGH min value (0x0). -* -* -* INPUTS: unsigned int bootDeviceBase - required cs_boot base address. -* unsigned int bootDeviceLength - required cs_boot size. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapDeviceBootSpace(unsigned int bootDeviceBase, - unsigned int bootDeviceLength) -{ - unsigned int bootBankBase,bootBankTop; - unsigned int bootDeviceBankTop = - (unsigned int)(bootDeviceBase + bootDeviceLength); - - bootBankBase = bootDeviceBase >> 20; - bootBankTop = bootDeviceBankTop >> 20; - GT_REG_WRITE(BOOTCS_LOW_DECODE_ADDRESS,0xffff); - if(bootDeviceLength != 0) - { - GT_REG_WRITE(BOOTCS_HIGH_DECODE_ADDRESS,bootBankTop -1); - GT_REG_WRITE(BOOTCS_LOW_DECODE_ADDRESS,bootBankBase); - } - else - { - GT_REG_WRITE(BOOTCS_HIGH_DECODE_ADDRESS,0x0); - } - return true; -} /******************************************************************** * memoryMapInternalRegistersSpace - Sets new base address for the internals diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S index 31d42f8..6e31731 100644 --- a/board/evb64260/misc.S +++ b/board/evb64260/misc.S @@ -30,14 +30,14 @@ board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ - + /* now that we're running from ram, init the rest of main memory * for ECC use */ lis r8, CFG_MONITOR_LEN@h ori r8, r8, CFG_MONITOR_LEN@l divw r3, r10, r8 - + /* set up the counter, and init the starting address */ mtctr r3 li r12, 0 @@ -118,6 +118,40 @@ stop_idma_engine_0: stwbrx r5, 0, (r6) blr +#endif + +#ifdef CFG_BOARD_ASM_INIT + /* NOTE: trashes r3-r7 */ + .globl board_asm_init +board_asm_init: + /* just move the GT registers to where they belong */ + lis r3, CFG_DFL_GT_REGS@h + ori r3, r3, CFG_DFL_GT_REGS@l + lis r4, CFG_GT_REGS@h + ori r4, r4, CFG_GT_REGS@l + li r5, INTERNAL_SPACE_DECODE + + /* test to see if we've already moved */ + lwbrx r6, r5, r4 + andi. r6, r6, 0xffff + rlwinm r7, r4, 12, 16, 31 + cmp cr0, r7, r6 + beqlr + + /* nope, have to move the registers */ + lwbrx r6, r5, r3 + andis. r6, r6, 0xffff + or r6, r6, r7 + stwbrx r6, r5, r3 + + /* now, poll for the change */ + lwbrx r7, r5, r4 +1: cmp cr0, r7, r6 + bne 1b + + /* done! */ + blr +#endif /* For use of the debug LEDs */ .global led_on0 @@ -137,7 +171,7 @@ led_on1: stw r18, 0x0(r18) sync blr - + .global led_on2 led_on2: xor r18, r18, r18 @@ -146,4 +180,3 @@ led_on2: stw r18, 0x0(r18) sync blr -#endif diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c index 57b78ab..05eaaa7 100644 --- a/board/evb64260/mpsc.c +++ b/board/evb64260/mpsc.c @@ -27,17 +27,18 @@ #include #include +#include #include #include "mpsc.h" -unsigned int *rx_desc_base; -unsigned int rx_desc_index; -unsigned int *tx_desc_base; -unsigned int tx_desc_index; - int (*mpsc_putchar)(char ch) = mpsc_putchar_early; +static volatile unsigned int *rx_desc_base=NULL; +static unsigned int rx_desc_index=0; +static volatile unsigned int *tx_desc_base=NULL; +static unsigned int tx_desc_index=0; + /* local function declarations */ static int galmpsc_connect(int channel, int connect); static int galmpsc_route_serial(int channel, int connect); @@ -51,6 +52,7 @@ static int galmpsc_set_parity(int mpsc, int value); static int galmpsc_enter_hunt(int mpsc); static int galmpsc_set_brkcnt(int mpsc, int value); static int galmpsc_set_tcschar(int mpsc, int value); +static int galmpsc_set_snoop(int mpsc, int value); static int galmpsc_shutdown(int mpsc); static int galsdma_set_RFT(int channel); @@ -65,102 +67,112 @@ static int galbrg_enable(int channel); static int galbrg_disable(int channel); static int galbrg_set_clksrc(int channel, int value); static int galbrg_set_CUV(int channel, int value); -#if 0 -static int galbrg_reset(int channel); + +static void galsdma_enable_rx(void); + +// static int galbrg_reset(int channel); + +#define SOFTWARE_CACHE_MANAGEMENT + +#ifdef SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +#define FLUSH_DCACHE(a,b) +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) #endif -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int -mpsc_putchar_early(char ch) -{ - unsigned int tx_buffers[20] = { [0 ... 19] = 0 }; - unsigned int temp; - unsigned int *tx_descriptor; - memset(tx_buffers, 0, 20 * sizeof(unsigned int)); +/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */ - /* align the descriptor */ - tx_descriptor = (unsigned int *)((unsigned int)(&tx_buffers[4]) & - 0xFFFFFFF0); +#define GT_REG_WRITE_MIRROR_G(a,d) {mh->a ## _M = d; GT_REG_WRITE(a,d);} +#define GTREGREAD_MIRROR_G(a) (mh->a ## _M) - tx_descriptor[5] = (unsigned int)ch; - tx_descriptor[3] = (unsigned int)&tx_descriptor[4]; - tx_descriptor[2] = (unsigned int)&tx_descriptor[0]; - tx_descriptor[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - tx_descriptor[0] = 0x00010000; +#define GT_REG_WRITE_MIRROR(a,i,g,d) {mh->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);} +#define GTREGREAD_MIRROR(a,i,g) (mh->a ## _M[i]) -#if 0 - tx_descriptor[9] = DESC_FIRST | DESC_LAST; - tx_descriptor[10] = (unsigned int)&tx_descriptor[0]; - tx_descriptor[11] = (unsigned int)&tx_descriptor[12]; -#endif +/* make sure this isn't bigger than 16 long words (ppcboot.h) */ +struct _tag_mirror_hack { + unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */ + unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */ + unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */ + unsigned GALBRG_0_CONFREG_M[2]; /* b200 */ - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&tx_descriptor[0]); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&tx_descriptor[0]); + unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */ + unsigned GALMPSC_RxC_ROUTE_M; /* b404 */ + unsigned GALMPSC_TxC_ROUTE_M; /* b408 */ - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); + unsigned int baudrate; /* current baudrate, for tsc delay calc */ +}; + +static struct _tag_mirror_hack *const mh = + (struct _tag_mirror_hack *)((init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET))->mirror_hack; + + +/* special function for running out of flash. doesn't modify any + * global variables [josh] */ +int +mpsc_putchar_early(char ch) +{ + int mpsc=CHANNEL; + int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); + galmpsc_set_tcschar(mpsc,ch); + GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200); - while(tx_descriptor[1] & DESC_OWNER); +#define MAGIC_FACTOR (10*1000000) + udelay(MAGIC_FACTOR / mh->baudrate); return 0; } -/* this function is for use after we relocate and aren't running out - * of flash any more. Currently, it's not used, since mpsc_putchar_early - * seems to be working just fine. [josh] */ -int -mpsc_putchar_full(char ch) +/* This is used after relocation, see serial.c and mpsc_init2 */ +static int +mpsc_putchar_sdma(char ch) { + volatile unsigned int *p; unsigned int temp; - tx_desc_index = (tx_desc_index + 1) % TX_DESC; - tx_desc_base[(tx_desc_index*8) + 5] = (unsigned int)ch; - tx_desc_base[(tx_desc_index*8) + 4] = (unsigned int)0x0; - tx_desc_base[(tx_desc_index*8) + 3] = - (unsigned int)&tx_desc_base[(tx_desc_index*8) + 4]; + /* align the descriptor */ + p = tx_desc_base; + memset((void *)p, 0, 8 * sizeof(unsigned int)); - tx_desc_base[(tx_desc_index*8) + 2] = - (unsigned int)&tx_desc_base[(tx_desc_index*8) + 0]; + /* fill one 64 bit buffer */ + /* word swap, pad with 0 */ + p[4] = 0; /* x */ + p[5] = (unsigned int)ch; /* x */ - tx_desc_base[(tx_desc_index*8) + 1] = - DESC_OWNER | DESC_FIRST | DESC_LAST; + /* CHANGED completely according to GT64260A dox - NTL */ + p[0] = 0x00010001; /* 0 */ + p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */ + p[2] = 0; /* 8 */ + p[3] = (unsigned int)&p[4]; /* c */ - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[(tx_desc_index*8) + 0] = - 0x00010001; +#if 0 + p[9] = DESC_FIRST | DESC_LAST; + p[10] = (unsigned int)&p[0]; + p[11] = (unsigned int)&p[12]; +#endif + + FLUSH_DCACHE(&p[0], &p[8]); GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&tx_desc_base[0]); + (unsigned int)&p[0]); GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&tx_desc_base[0]); + (unsigned int)&p[0]); temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND); + temp |= (TX_DEMAND | TX_STOP); GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - while(tx_desc_base[(tx_desc_index*8) + 1] & DESC_OWNER); - tx_desc_base[(tx_desc_index*8) + 5] = (unsigned int)0x0; - tx_desc_base[(tx_desc_index*8) + 4] = (unsigned int)0x0; - tx_desc_base[(tx_desc_index*8) + 3] = - (unsigned int)&tx_desc_base[(tx_desc_index*8) + 4]; + INVALIDATE_DCACHE(&p[1], &p[2]); - tx_desc_base[(tx_desc_index*8) + 2] = - (unsigned int)&tx_desc_base[(tx_desc_index*8) + 0]; - - tx_desc_base[(tx_desc_index*8) + 1] = - DESC_OWNER | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[(tx_desc_index*8) + 0] = 0x00010001; - - tx_desc_index = (tx_desc_index - 1) % TX_DESC; + while(p[1] & DESC_OWNER) { + udelay(100); + INVALIDATE_DCACHE(&p[1], &p[2]); + } return 0; } @@ -168,93 +180,101 @@ mpsc_putchar_full(char ch) char mpsc_getchar(void) { - unsigned int temp; - volatile char ch; -#if 0 - int nextindex; -#endif + static unsigned int done = 0; + volatile char ch; + unsigned int len=0, idx, temp; -#if 0 - /* set SDMA Receive Enable */ - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); + volatile unsigned int *p; - if (!(temp & RX_ENABLE)) { -#define DEBUG -#ifdef DEBUG - mpsc_putchar_early('!'); -#endif - temp |= RX_ENABLE; - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), - temp); - - galmpsc_enter_hunt(CHANNEL); - - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&rx_desc_base[(rx_desc_index*8)]); - } -#endif - while (rx_desc_base[(rx_desc_index*8) + 1] & DESC_OWNER) ; + do { + p=&rx_desc_base[rx_desc_index*8]; - if (rx_desc_base[(rx_desc_index * 8) + 1] & (1 << 15)) { - printf("oops, error: %08x\n", - rx_desc_base[(rx_desc_index * 8) + 1]); + INVALIDATE_DCACHE(&p[0], &p[1]); + /* Wait for character */ + while (p[1] & DESC_OWNER){ + udelay(100); + INVALIDATE_DCACHE(&p[0], &p[1]); + } - temp = GTREGREAD(GALMPSC_CHANNELREG_2); + /* Handle error case */ + if (p[1] & (1<<15)) { + printf("oops, error: %08x\n", p[1]); + + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP); temp |= (1 << 23); - GT_REG_WRITE(GALMPSC_CHANNELREG_2, temp); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp); - while (GTREGREAD(GALMPSC_CHANNELREG_2) & (1 << 23)) ; + /* Can't poll on abort bit, so we just wait. */ + udelay(100); - galmpsc_enter_hunt(CHANNEL); + galsdma_enable_rx(); } - ch = (char)(rx_desc_base[(rx_desc_index*8) + 5] & 0x000000FF); - - rx_desc_base[(rx_desc_index*8) + 1] = - DESC_OWNER | DESC_FIRST | DESC_LAST; - - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - -#if 0 - nextindex = (rx_desc_index + 1) % RX_DESC; - - rx_desc_base[(rx_desc_index*8) + 0] = 0x00010000; - - rx_desc_base[(rx_desc_index*8) + 1] = - DESC_OWNER | DESC_FIRST | DESC_LAST; + /* Number of bytes left in this descriptor */ + len = p[0] & 0xffff; - rx_desc_base[(rx_desc_index*8) + 2] = - (unsigned int)&rx_desc_base[(nextindex*8) + 0]; + if (len) { + /* Where to look */ + idx = 5; + if (done > 3) idx = 4; + if (done > 7) idx = 7; + if (done > 11) idx = 6; - rx_desc_base[(rx_desc_index*8) + 3] = - (unsigned int)&rx_desc_base[(rx_desc_index*8) + 4]; + INVALIDATE_DCACHE(&p[idx], &p[idx+1]); + ch = p[idx] & 0xff; + done++; + } - rx_desc_base[(rx_desc_index*8) + 5] = 0; + if (done < len) { + /* this descriptor has more bytes still + * shift down the char we just read, and leave the + * buffer in place for the next time around + */ + p[idx] = p[idx] >> 8; + FLUSH_DCACHE(&p[idx], &p[idx+1]); + } - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&rx_desc_base[(rx_desc_index*8)]); -#endif + if (done == len) { + /* nothing left in this descriptor. + * go to next one + */ + p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; + p[0] = 0x00100000; + FLUSH_DCACHE(&p[0], &p[1]); + /* Next descriptor */ + rx_desc_index = (rx_desc_index + 1) % RX_DESC; + done = 0; + } + } while (len==0); /* galileo bug.. len might be zero */ - return ch; + return ch; } int mpsc_test_char(void) { - if (rx_desc_base[(rx_desc_index*8) + 1] & DESC_OWNER) - return 0; - else - return 1; + volatile unsigned int *p=&rx_desc_base[rx_desc_index*8]; + + INVALIDATE_DCACHE(&p[1], &p[2]); + + if (p[1] & DESC_OWNER) return 0; + else return 1; } int mpsc_init(int baud) { + memset(mh, 0, sizeof(struct _tag_mirror_hack)); + mh->GALMPSC_ROUTING_REGISTER_M=0x3fffffff; /* BRG CONFIG */ galbrg_set_baudrate(CHANNEL, baud); +#ifdef ZUMA_NTL + galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */ +#else galbrg_set_clksrc(CHANNEL,0); +#endif galbrg_set_CUV(CHANNEL, 0); galbrg_enable(CHANNEL); @@ -268,7 +288,7 @@ mpsc_init(int baud) galmpsc_shutdown(CHANNEL); /* SDMA CONFIG */ - galsdma_set_burstsize(CHANNEL, 8); + galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */ galsdma_set_txle(CHANNEL); galsdma_set_rxle(CHANNEL); galsdma_set_RC(CHANNEL, 0xf); @@ -282,67 +302,76 @@ mpsc_init(int baud) galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */ galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ + /* COMM_MPSC CONFIG */ +#ifdef SOFTWARE_CACHE_MANAGEMENT + galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ +#else + galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ +#endif + return 0; } void mpsc_init2(void) { - int i, temp; + int i; - mpsc_putchar = mpsc_putchar_full; + mpsc_putchar = mpsc_putchar_sdma; + /* RX descriptors */ rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) * - sizeof(unsigned int)); + sizeof(unsigned int)); - /* align at a 4 word boundry */ + /* align descriptors */ rx_desc_base = (unsigned int *) (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0); rx_desc_index = 0; - memset(rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int)); + memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int)); for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i*8 + 5] = (unsigned int)0x0; - rx_desc_base[i*8 + 4] = (unsigned int)0x0; - rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; - rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[i*8 + 8]; - rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - rx_desc_base[i*8] = 0x00010000; + rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */ + rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */ + rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */ + rx_desc_base[i*8] = 0x00100000; } - rx_desc_base[i*8 - 6] = (unsigned int)&rx_desc_base[0]; + rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0]; + + FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]); + GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), + (unsigned int)&rx_desc_base[0]); + + /* TX descriptors */ + tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) * + sizeof(unsigned int)); + + /* align descriptors */ + tx_desc_base = (unsigned int *) + (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0); - tx_desc_base = (unsigned int *)malloc((TX_DESC*8) * - sizeof(unsigned int)); tx_desc_index = -1; - memset(tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int)); + memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int)); for (i = 0; i < TX_DESC; i++) { tx_desc_base[i*8 + 5] = (unsigned int)0x23232323; tx_desc_base[i*8 + 4] = (unsigned int)0x23232323; tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4]; - tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[i*8 + 8]; + tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8]; tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* set sbytecnt and shadow byte cnt to 1 */ tx_desc_base[i*8] = 0x00010001; } - tx_desc_base[i*8 - 6] = (unsigned int)&tx_desc_base[0]; + tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0]; - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&rx_desc_base[0]); + FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]); udelay(100); - - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt(CHANNEL); + + galsdma_enable_rx(); return; } @@ -354,12 +383,19 @@ galbrg_set_baudrate(int channel, int rate) galbrg_disable(channel); +#ifdef ZUMA_NTL + /* from tclk */ + clock = (CFG_BUS_HZ/(16*rate)) - 1; +#else clock = (3686400/(16*rate)) - 1; +#endif galbrg_set_CDV(channel, clock); galbrg_enable(channel); + mh->baudrate = rate; + return 0; } @@ -372,10 +408,10 @@ galbrg_set_CDV(int channel, int value) { unsigned int temp; - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); temp &= 0xFFFF0000; temp |= (value & 0x0000FFFF); - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp); return 0; } @@ -385,9 +421,9 @@ galbrg_enable(int channel) { unsigned int temp; - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); temp |= 0x00010000; - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP),temp); + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); return 0; } @@ -397,9 +433,9 @@ galbrg_disable(int channel) { unsigned int temp; - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); temp &= 0xFFFEFFFF; - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP),temp); + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); return 0; } @@ -409,10 +445,10 @@ galbrg_set_clksrc(int channel, int value) { unsigned int temp; - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP); temp &= 0xFF83FFFF; temp |= (value << 18); - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP),temp); + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp); return 0; } @@ -541,7 +577,7 @@ galmpsc_connect(int channel, int connect) { unsigned int temp; - temp = GTREGREAD(GALMPSC_ROUTING_REGISTER); + temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER); if ((channel == 0) && connect) temp &= ~0x00000007; @@ -555,7 +591,7 @@ galmpsc_connect(int channel, int connect) /* Just in case... */ temp &= 0x3fffffff; - GT_REG_WRITE(GALMPSC_ROUTING_REGISTER, temp); + GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp); return 0; } @@ -586,14 +622,14 @@ galmpsc_route_rx_clock(int channel, int brg) { unsigned int temp; - temp = GTREGREAD(GALMPSC_RxC_ROUTE); + temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE); if (channel == 0) temp |= brg; else temp |= (brg << 8); - GT_REG_WRITE(GALMPSC_RxC_ROUTE,temp); + GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp); return 0; } @@ -603,14 +639,14 @@ galmpsc_route_tx_clock(int channel, int brg) { unsigned int temp; - temp = GTREGREAD(GALMPSC_TxC_ROUTE); + temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE); if (channel == 0) temp |= brg; else temp |= (brg << 8); - GT_REG_WRITE(GALMPSC_TxC_ROUTE,temp); + GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp); return 0; } @@ -619,13 +655,19 @@ static int galmpsc_write_config_regs(int mpsc, int mode) { if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode */ + /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP), 0x000004c4); /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP), 0x024003f8); + // 22 2222 1111 + // 54 3210 9876 + // 0000 0010 0000 0000 + // 1 + // 098 7654 3210 + // 0000 0011 1111 1000 } else return -1; @@ -635,9 +677,9 @@ galmpsc_write_config_regs(int mpsc, int mode) static int galmpsc_config_channel_regs(int mpsc) { - GT_REG_WRITE(GALMPSC_CHANNELREG_1+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1); GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0); GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0); GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0); @@ -657,10 +699,10 @@ galmpsc_set_brkcnt(int mpsc, int value) { unsigned int temp; - temp = GTREGREAD(GALMPSC_CHANNELREG_1+(mpsc*GALMPSC_REG_GAP)); + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); temp &= 0x0000FFFF; temp |= (value << 16); - GT_REG_WRITE(GALMPSC_CHANNELREG_1+(mpsc*GALMPSC_REG_GAP), temp); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); return 0; } @@ -670,10 +712,10 @@ galmpsc_set_tcschar(int mpsc, int value) { unsigned int temp; - temp = GTREGREAD(GALMPSC_CHANNELREG_1+(mpsc*GALMPSC_REG_GAP)); + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); temp &= 0xFFFF0000; temp |= value; - GT_REG_WRITE(GALMPSC_CHANNELREG_1+(mpsc*GALMPSC_REG_GAP), temp); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); return 0; } @@ -683,10 +725,10 @@ galmpsc_set_char_length(int mpsc, int value) { unsigned int temp; - temp = GTREGREAD(GALMPSC_PROTOCONF_REG + (mpsc*GALMPSC_REG_GAP)); + temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); temp &= 0xFFFFCFFF; temp |= (value << 12); - GT_REG_WRITE(GALMPSC_PROTOCONF_REG + (mpsc*GALMPSC_REG_GAP), temp); + GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp); return 0; } @@ -696,9 +738,9 @@ galmpsc_set_stop_bit_length(int mpsc, int value) { unsigned int temp; - temp = GTREGREAD(GALMPSC_PROTOCONF_REG + (mpsc*GALMPSC_REG_GAP)); + temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); temp |= (value << 14); - GT_REG_WRITE(GALMPSC_PROTOCONF_REG + (mpsc*GALMPSC_REG_GAP),temp); + GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp); return 0; } @@ -708,7 +750,7 @@ galmpsc_set_parity(int mpsc, int value) { unsigned int temp; - temp = GTREGREAD(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP)); + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); if (value != -1) { temp &= 0xFFF3FFF3; temp |= ((value << 18) | (value << 2)); @@ -717,7 +759,7 @@ galmpsc_set_parity(int mpsc, int value) temp &= 0xFFF1FFF1; } - GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); return 0; } @@ -725,30 +767,30 @@ galmpsc_set_parity(int mpsc, int value) static int galmpsc_enter_hunt(int mpsc) { - unsigned int temp; - - GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), 0x80000000); + int temp; - /* read reg 10 to see when we actually ENTER hunt mode */ - temp=GTREGREAD(GALMPSC_CHANNELREG_10); + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); + temp |= 0x80000000; + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - while (temp & 0x00000020) { - temp = GTREGREAD(GALMPSC_CHANNELREG_10); - } + /* Should Poll on Enter Hunt bit, but the register is write-only */ + /* errata suggests pausing 100 system cycles */ + udelay(100); return 0; } + static int galmpsc_shutdown(int mpsc) { unsigned int temp; /* cause RX abort (clears RX) */ - temp = GTREGREAD(GALMPSC_CHANNELREG_2); + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE(GALMPSC_CHANNELREG_2, temp); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp); GT_REG_WRITE(GALSDMA_0_COM_REG, 0); GT_REG_WRITE(GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); @@ -756,7 +798,7 @@ galmpsc_shutdown(int mpsc) /* shut down the MPSC */ GT_REG_WRITE(GALMPSC_MCONF_LOW, 0); GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE(GALMPSC_PROTOCONF_REG, 0); + GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0); udelay(100); @@ -775,3 +817,29 @@ galmpsc_shutdown(int mpsc) return 0; } + +static void +galsdma_enable_rx(void) +{ + int temp; + + /* Enable RX processing */ + temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); + temp |= RX_ENABLE; + GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); + + galmpsc_enter_hunt(CHANNEL); +} + +static int +galmpsc_set_snoop(int mpsc, int value) +{ + int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW; + int temp=GTREGREAD(reg); + if(value) + temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30); + else + temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30)); + GT_REG_WRITE(reg, temp); + return 0; +} diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h index e805268..5afad2f 100644 --- a/board/evb64260/mpsc.h +++ b/board/evb64260/mpsc.h @@ -35,18 +35,17 @@ int mpsc_init(int baud); void mpsc_init2(void); -int mpsc_putchar_early(char ch); -int mpsc_putchar_full(char ch); char mpsc_getchar(void); int mpsc_test_char(void); int galbrg_set_baudrate(int channel, int rate); +int mpsc_putchar_early(char ch); extern int (*mpsc_putchar)(char ch); #define CHANNEL CONFIG_MPSC_PORT #define TX_DESC 5 -#define RX_DESC 5 +#define RX_DESC 20 #define DESC_FIRST 0x00010000 #define DESC_LAST 0x00020000 diff --git a/board/evb64260/ns16550.c b/board/evb64260/ns16550.c index 703b1ae..06a3ea8 100644 --- a/board/evb64260/ns16550.c +++ b/board/evb64260/ns16550.c @@ -10,6 +10,9 @@ #include #include "ns16550.h" +#ifdef ZUMA_NTL +/* no 16550 device */ +#else const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), (NS16550_t) (CFG_DUART_IO + 0x20) }; @@ -63,3 +66,4 @@ NS16550_tstc(volatile struct NS16550 *com_port) { return ((com_port->lsr & LSR_DR) != 0); } +#endif diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c index 5bd4629..8f59553 100644 --- a/board/evb64260/pci.c +++ b/board/evb64260/pci.c @@ -2,12 +2,138 @@ /* Copyright - Galileo technology. */ -#include +#include #include -#include + +#undef DEBUG +#undef IDE_SET_NATIVE_MODE + +static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { +#ifdef ZUMA_NTL + {0,0,0,0,0,0,0,29, [8 ... PCI_MAX_DEVICES-1]=0}, + {0,0,0,0,0,0,0,28, [8 ... PCI_MAX_DEVICES-1]=0} +#else /* EVB??? This is a guess */ + {0,0,0,0,0,0,0,27,27, [9 ... PCI_MAX_DEVICES-1]=0}, + {0,0,0,0,0,0,0,29,29, [9 ... PCI_MAX_DEVICES-1]=0} +#endif +}; + +static const unsigned int BAR_REG[]={BAR0,BAR1,BAR2,BAR3,BAR4,BAR5}; + +static PCI_DEVICE pci_dev_list[2][PCI_MAX_DEVICES]; +static unsigned int pci_mem_bar_alloc[2]={CFG_PCI0_MEM_BASE,CFG_PCI1_MEM_BASE}; +static unsigned int pci_io_bar_alloc[2]={CFG_PCI0_IO_SPACE_PCI,CFG_PCI1_IO_SPACE_PCI}; + +static void decode_class(char *buf, int class) +{ + static const char * const decode_legend[] = { + "Old generation device", /* 0 */ + "Mass storage controller", /* 1 */ + "Network controller", /* 2 */ + "Display controller", /* 3 */ + "Multimedia device", /* 4 */ + "Memory controller", /* 5 */ + "Bridge Device", /* 6 */ + "Simple Communication controllers", /* 7 */ + "Base system peripherals", /* 8 */ + "Input Devices", /* 9 */ + "Docking stations", /* a */ + "Processors", /* b */ + "Serial bus controllers", /* c */ + "Wireless controllers", /* d */ + "Intelligent I/O controllers", /* e */ + "Satellite communication controllers", /* f */ + "Encryption/Decryption controllers", /* 10 */ + "Data acquisition and signal processing controllers", /* 11 */ + "\0" + }; + + if(class>=0 && class<=0x11) + strncpy(buf,decode_legend[class],40); + else if(class==0xff) + strncpy(buf,"Other",40); + else + sprintf(buf,"Unknown class 0x%x", class); +} + +static const unsigned int pci_p2p_configuration_reg[]={ + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION}; + +static const unsigned int pci_configuration_address[]={ + PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS}; + +static const unsigned int pci_configuration_data[]={ + PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, + PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER}; + +static const unsigned int pci_error_cause_reg[]={ + PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE}; + +static const unsigned int pci_arbiter_control[]={ + PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL}; + +static const unsigned int pci_snoop_control_base_0_low[]={ + PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW}; +static const unsigned int pci_snoop_control_top_0[]={ + PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0}; + +static const unsigned int pci_access_control_base_0_low[]={ + PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW}; +static const unsigned int pci_access_control_top_0[]={ + PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0}; + +static const unsigned int pci_scs_bank_size[2][4] = { + {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, + PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, + {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, + PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}}; + +static const unsigned int pci_p2p_configuration[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION}; + +static u32 size_bar(int host, int barnum, int device, PCI_BAR *bar) +{ + u32 detect, size=0; + + pciWriteConfigReg(host,BAR_REG[barnum],device,0x0); + if((((detect=pciReadConfigReg(host,BAR_REG[barnum],device))&~1)!=0x0)) { + static const int ide_bar[]={8,4,8,4,0,0}; + u32 classCode = pciReadConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID, + device); + if((classCode>>16)!=0x0101) { + printf(" %d:%d weird bar and not PCI/IDE (classCode=%08x)\n", + device,barnum,classCode); + printf(" %d:%d 0->bar: BAR:%x\n", device,barnum,detect); + pciWriteConfigReg(host,BAR_REG[barnum],device,0xffffffff); + detect=pciReadConfigReg(host,BAR_REG[barnum],device); + printf(" %d:%d f->bar: BAR:%x\n", device,barnum,detect); + return 0; + } + + bar->type &= ~BAR_MEM_TYPE_MASK; /* set to type 0 */ + return ide_bar[barnum]; + } + + pciWriteConfigReg(host,BAR_REG[barnum],device,0xffffffff); + bar->detectBase = pciReadConfigReg(host,BAR_REG[barnum],device); + + if(bar->detectBase == 0) { /* case of an empty BAR */ + return 0; + } + + if (bar->type & BAR_SEL_MEM_IO) { + bar->type &= BAR_SEL_MEM_IO; + size = ~(bar->detectBase & 0xfffffffc) + 1; + } else { + size = ~(bar->detectBase & 0xfffffff0) + 1; + } + + return size; + +} /******************************************************************** -* pci0ScanDevices - This function scan PCI0 bus, if found any device on +* pciScanDevices - This function scan PCIn bus, if found any device on * this bus it interrogate the Device for the information * it can discover. * The fields with all information are the following: @@ -15,489 +141,95 @@ * unsigned int deviceNum; * unsigned int venID; * unsigned int deviceID; -* unsigned int bar0Base; -* unsigned int bar0Size; -* unsigned int bar1Base; -* unsigned int bar1Size; -* unsigned int bar2Base; -* unsigned int bar2Size; -* unsigned int bar3Base; -* unsigned int bar3Size; -* unsigned int bar4Base; -* unsigned int bar4Size; -* unsigned int bar5Base; -* unsigned int bar5Size; +* struct { +* unsigned int base; +* unsigned int size; +* unsigned int type; +* } bar[6]; * -* Inputs: PCI0_DEVICE* pci0Detect - Pointer to an array of STRUCT PCI0_DEVICE. -* unsigned int numberOfElment - The PCI0_DEVICE Array length. +* Inputs: PCI_DEVICE* pciDetect - Pointer to an array of STRUCT PCI_DEVICE. +* unsigned int numberOfElment - The PCI_DEVICE Array length. * Output: None. *********************************************************************/ -void pci0ScanDevices(PCI_DEVICE* pci0Detect,unsigned int numberOfElment) +void pciScanDevices(PCI_HOST host, PCI_DEVICE* pciDetect,unsigned int numberOfElment) { - PCI_DEVICE* pci0ArrayPointer = pci0Detect; + PCI_DEVICE* pciArrayPointer = pciDetect; unsigned int id; /* PCI Configuration register 0x0.*/ unsigned int device; /* device`s Counter.*/ unsigned int classCode; /* PCI Configuration register 0x8 */ unsigned int arrayCounter = 0; unsigned int memBaseAddress; - unsigned int memSize; - unsigned int pci0Cause; - - RESET_REG_BITS(PCI_0ERROR_CAUSE,BIT8); /* clears PCI_0 cause. */ - PCI0_MASTER_ENABLE(SELF); - /* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ - for(device = 1 ; device < 22 ; device ++) + unsigned int pciCause; + + RESET_REG_BITS(pci_error_cause_reg[host],BIT8); /* clears PCI_0 cause. */ + + PCI_MASTER_ENABLE(host,SELF); + + for(device = 0 ; device < PCI_MAX_DEVICES ; device ++) { - id = pci0ReadConfigReg(PCI_DEVICE_AND_VENDOR_ID,device); - GT_REG_READ(PCI_0ERROR_CAUSE,&pci0Cause); - /* Clearing bit 8 of in the Cause Register 0x1d58 by writing 0. */ - RESET_REG_BITS(PCI_0ERROR_CAUSE,BIT8); /* clears PCI_0 cause. */ - if ( (id != 0xffffffff) && !(pci0Cause & BIT8) ) /* agent was found */ - { - classCode = pci0ReadConfigReg(PCI_CLASS_CODE_AND_REVISION_ID, + id = pciReadConfigReg(host, PCI_DEVICE_AND_VENDOR_ID,device); + GT_REG_READ(pci_error_cause_reg[host],&pciCause); + /* Clearing bit 8 of in the Cause Register by writing 0. */ + RESET_REG_BITS(pci_error_cause_reg[host],BIT8); /* clears PCI_n cause. */ + if ( (id != 0xffffffff) && !(pciCause & BIT8) ) { /* agent was found */ + int i; +#if 0 + if(device!=0) { + int statcmd = pciReadConfigReg(host,PCI_STATUS_AND_COMMAND, + device); + statcmd &= ~(MASTER_ENABLE | MEMORY_ENABLE | I_O_ENABLE); + /* disable this device */ + pciWriteConfigReg(host,PCI_STATUS_AND_COMMAND, device, statcmd); + } +#endif + + classCode = pciReadConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID, device); - pci0ArrayPointer->deviceNum = device; - pci0ArrayPointer->venID = ( id & 0xffff); - pci0ArrayPointer->deviceID = ( ( id & 0xffff0000) >> 16 ); - /* BAR0 parameters */ - memBaseAddress = pci0ReadConfigReg(BAR0,device); - pci0ArrayPointer->bar0Type = memBaseAddress & BIT0; - pci0ArrayPointer->bar0Base = memBaseAddress & 0xfffff000; - pci0WriteConfigReg(BAR0,device,0xffffffff); - memSize = pci0ReadConfigReg(BAR0,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci0ArrayPointer->bar0Size = 0; - } - else - { - if (pci0ArrayPointer->bar0Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci0ArrayPointer->bar0Size = memSize; - } - /* restore the previous value to BAR_0 base */ - pci0WriteConfigReg(BAR0,device,memBaseAddress); - /* BAR1 parameters */ - memBaseAddress = pci0ReadConfigReg(BAR1,device); - pci0ArrayPointer->bar1Type = memBaseAddress & BIT0; - pci0ArrayPointer->bar1Base = memBaseAddress & 0xfffff000; - pci0WriteConfigReg(BAR1,device,0xffffffff); - memSize = pci0ReadConfigReg(BAR1,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci0ArrayPointer->bar1Size = 0; - } - else - { - if (pci0ArrayPointer->bar1Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci0ArrayPointer->bar1Size = memSize; - } - /* restore the previous value to BAR_1 base */ - pci0WriteConfigReg(BAR1,device,memBaseAddress); - /* BAR2 parameters */ - memBaseAddress = pci0ReadConfigReg(BAR2,device); - pci0ArrayPointer->bar2Type = memBaseAddress & BIT0; - pci0ArrayPointer->bar2Base = memBaseAddress & 0xfffff000; - pci0WriteConfigReg(BAR2,device,0xffffffff); - memSize = pci0ReadConfigReg(BAR2,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci0ArrayPointer->bar2Size = 0; - } - else - { - if (pci0ArrayPointer->bar2Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci0ArrayPointer->bar2Size = memSize; - } - /* restore the previous value to BAR_2 base */ - pci0WriteConfigReg(BAR2,device,memBaseAddress); - /* BAR3 parameters */ - memBaseAddress = pci0ReadConfigReg(BAR3,device); - pci0ArrayPointer->bar3Type = memBaseAddress & BIT0; - pci0ArrayPointer->bar3Base = memBaseAddress & 0xfffff000; - pci0WriteConfigReg(BAR3,device,0xffffffff); - memSize = pci0ReadConfigReg(BAR3,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci0ArrayPointer->bar3Size = 0; - } - else - { - if (pci0ArrayPointer->bar3Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci0ArrayPointer->bar3Size = memSize; - } - /* restore the previous value to BAR_3 base */ - pci0WriteConfigReg(BAR3,device,memBaseAddress); - /* BAR4 parameters */ - memBaseAddress = pci0ReadConfigReg(BAR4,device); - pci0ArrayPointer->bar4Type = memBaseAddress & BIT0; - pci0ArrayPointer->bar4Base = memBaseAddress & 0xfffff000; - pci0WriteConfigReg(BAR4,device,0xffffffff); - memSize = pci0ReadConfigReg(BAR4,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci0ArrayPointer->bar4Size = 0; - } - else - { - if (pci0ArrayPointer->bar4Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci0ArrayPointer->bar4Size = memSize; - } - /* restore the previous value to BAR_4 base */ - pci0WriteConfigReg(BAR4,device,memBaseAddress); - /* BAR5 parameters */ - memBaseAddress = pci0ReadConfigReg(BAR5,device); - pci0ArrayPointer->bar5Type = memBaseAddress & BIT0; - pci0ArrayPointer->bar5Base = memBaseAddress & 0xfffff000; - pci0WriteConfigReg(BAR5,device,0xffffffff); - memSize = pci0ReadConfigReg(BAR5,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci0ArrayPointer->bar5Size = 0; - } - else - { - if (pci0ArrayPointer->bar5Type == 1) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci0ArrayPointer->bar5Size = memSize; - } - /* restore the previous value to BAR_5 base */ - pci0WriteConfigReg(BAR5,device,memBaseAddress); - /* End of BARs Detection. */ - - classCode = ( (classCode & 0xff000000 ) >> 24 ); - switch(classCode) { - case 0x0: - strcpy(pci0ArrayPointer->type,"Old generation device"); - break; - case 0x1: - strcpy(pci0ArrayPointer->type,"Mass storage controller"); - break; - case 0x2: - strcpy(pci0ArrayPointer->type,"Network controller"); - break; - case 0x3: - strcpy(pci0ArrayPointer->type,"Display controller"); - break; - case 0x4: - strcpy(pci0ArrayPointer->type,"Multimedia device"); - break; - case 0x5: - strcpy(pci0ArrayPointer->type,"Memory controller"); - break; - case 0x6: - strcpy(pci0ArrayPointer->type,"Bridge Device"); - break; - case 0x7: - strcpy(pci0ArrayPointer->type,"Simple Communication controllers"); - break; - case 0x8: - strcpy(pci0ArrayPointer->type,"Base system peripherals"); - break; - case 0x9: - strcpy(pci0ArrayPointer->type,"Input Devices"); - break; - case 0xa: - strcpy(pci0ArrayPointer->type,"Docking stations"); - break; - case 0xb: - strcpy(pci0ArrayPointer->type,"Processors"); - break; - case 0xc: - strcpy(pci0ArrayPointer->type,"Serial bus controllers"); - break; - case 0xd: - strcpy(pci0ArrayPointer->type,"Wireless controllers"); - break; - case 0xe: - strcpy(pci0ArrayPointer->type,"Intelligent I/O controllers"); - break; - case 0xf: - strcpy(pci0ArrayPointer->type,"Satellite communication controllers"); - break; - case 0x10: - strcpy(pci0ArrayPointer->type,"Encryption/Decryption controllers"); - break; - case 0x11: - strcpy(pci0ArrayPointer->type,"Data acquisition and \ - signal processing controllers"); - break; - default: - break; - - } - arrayCounter++; /* point to the next element in the Array. */ - if(arrayCounter == numberOfElment) - return; /* When the Array is fully used, return. */ - /* Else, points to next free Element.*/ - pci0ArrayPointer = &pci0Detect[arrayCounter]; - } - } - pci0ArrayPointer->deviceNum = 0; /* 0 => End of List */ -} + pciArrayPointer->host = host; + pciArrayPointer->deviceNum = device; + pciArrayPointer->venID = ( id & 0xffff); + pciArrayPointer->deviceID = ( ( id & 0xffff0000) >> 16 ); + +#ifdef IDE_SET_NATIVE_MODE + if ((classCode >> 16) == 0x0101) { /* IDE/PCI hack to set to native mode */ +#ifdef DEBUG + printf("%d:%d setting PCI IDE native mode\n", host, device); +#endif + pciWriteConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID,device, + classCode | 0x0500); + + for(i=0x50;i<0x5b;i+=4) { + printf("%x: %08x\n",i, pciReadConfigReg(host,i,device)); + } + } +#endif + + for(i=0;i<6;i++) { + PCI_BAR *pbar=&pciArrayPointer->bar[i]; + /* BARn parameters */ + memBaseAddress = pciReadConfigReg(host,BAR_REG[i],device); + pbar->type = memBaseAddress & BAR_CONFIG_MASK; + pbar->base = memBaseAddress & 0xfffff000; + pbar->size = size_bar(host,i,device, pbar); + /* restore the previous value to BAR_n base */ + pciWriteConfigReg(host,BAR_REG[i],device,memBaseAddress); + } + + decode_class(pciArrayPointer->type, classCode>>24); -/******************************************************************** -* pci1ScanDevices - This function scan PCI1 bus, if found any device on -* this bus it interrogate the Device for the information -* it can discover. -* The fields with all information are the following: -* char type[20]; -* unsigned int deviceNum; -* unsigned int venID; -* unsigned int deviceID; -* unsigned int bar0Base; -* unsigned int bar0Size; -* unsigned int bar1Base; -* unsigned int bar1Size; -* unsigned int bar2Base; -* unsigned int bar2Size; -* unsigned int bar3Base; -* unsigned int bar3Size; -* unsigned int bar4Base; -* unsigned int bar4Size; -* unsigned int bar5Base; -* unsigned int bar5Size; -* -* Inputs: Pointer to an array of STRUCT PCI1_DEVICE. -* Output: None. -*********************************************************************/ -void pci1ScanDevices(PCI_DEVICE* pci1Detect,unsigned int numberOfElment) -{ - PCI_DEVICE* pci1ArrayPointer = pci1Detect; - unsigned int id; /* PCI Configuration register 0x0.*/ - unsigned int device; /* device`s Counter.*/ - unsigned int classCode; /* PCI Configuration register 0x8 */ - unsigned int arrayCounter=0; - unsigned int memBaseAddress; - unsigned int memSize; - unsigned int pci1Cause; - - RESET_REG_BITS(PCI_1ERROR_CAUSE,BIT8); /* clears PCI_0 cause. */ - PCI1_MASTER_ENABLE(SELF); - /* According to PCI REV 2.1 MAX agents on the bus are -21- */ - for(device = 1 ; device < 22 ; device ++) - { - id = pci1ReadConfigReg(PCI_DEVICE_AND_VENDOR_ID,device); - GT_REG_READ(PCI_1ERROR_CAUSE,&pci1Cause); - /* Clearing bit 8 of in the Cause Register 0x1d58 by writing 0. */ - RESET_REG_BITS(PCI_1ERROR_CAUSE,BIT8); /* clears PCI_1 cause. */ - if ( (id != 0xffffffff) && !(pci1Cause & 0x40000) ) - { - classCode = pci1ReadConfigReg(PCI_CLASS_CODE_AND_REVISION_ID,device); - pci1ArrayPointer->deviceNum = device; - pci1ArrayPointer->venID = ( id & 0xffff); - pci1ArrayPointer->deviceID = ( ( id & 0xffff0000) >> 16 ); - - /* BAR0 parameters */ - memBaseAddress = pci1ReadConfigReg(BAR0,device); - pci1ArrayPointer->bar0Type = memBaseAddress & BIT0; - pci1ArrayPointer->bar0Base = memBaseAddress & 0xfffff000; - pci1WriteConfigReg(BAR0,device,0xffffffff); - memSize = pci1ReadConfigReg(BAR0,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci1ArrayPointer->bar0Size = 0; - } - else - { - if (pci1ArrayPointer->bar0Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci1ArrayPointer->bar0Size = memSize; - } - /* restore the previous value to BAR_0 base */ - pci1WriteConfigReg(BAR0,device,memBaseAddress); - /* BAR1 parameters */ - memBaseAddress = pci1ReadConfigReg(BAR1,device); - pci1ArrayPointer->bar1Type = memBaseAddress & BIT0; - pci1ArrayPointer->bar1Base = memBaseAddress & 0xfffff000; - pci1WriteConfigReg(BAR1,device,0xffffffff); - memSize = pci1ReadConfigReg(BAR1,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci1ArrayPointer->bar1Size = 0; - } - else - { - if (pci1ArrayPointer->bar1Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci1ArrayPointer->bar1Size = memSize; - } - /* restore the previous value to BAR_1 base */ - pci1WriteConfigReg(BAR1,device,memBaseAddress); - /* BAR2 parameters */ - memBaseAddress = pci1ReadConfigReg(BAR2,device); - pci1ArrayPointer->bar2Type = memBaseAddress & BIT0; - pci1ArrayPointer->bar2Base = memBaseAddress & 0xfffff000; - pci1WriteConfigReg(BAR2,device,0xffffffff); - memSize = pci1ReadConfigReg(BAR2,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci1ArrayPointer->bar2Size = 0; - } - else - { - if (pci1ArrayPointer->bar2Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci1ArrayPointer->bar2Size = memSize; - } - /* restore the previous value to BAR_2 base */ - pci1WriteConfigReg(BAR2,device,memBaseAddress); - /* BAR3 parameters */ - memBaseAddress = pci1ReadConfigReg(BAR3,device); - pci1ArrayPointer->bar3Type = memBaseAddress & BIT0; - pci1ArrayPointer->bar3Base = memBaseAddress & 0xfffff000; - pci1WriteConfigReg(BAR3,device,0xffffffff); - memSize = pci1ReadConfigReg(BAR3,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci1ArrayPointer->bar3Size = 0; - } - else - { - if (pci1ArrayPointer->bar3Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci1ArrayPointer->bar3Size = memSize; - } - /* restore the previous value to BAR_3 base */ - pci1WriteConfigReg(BAR3,device,memBaseAddress); - /* BAR4 parameters */ - memBaseAddress = pci1ReadConfigReg(BAR4,device); - pci1ArrayPointer->bar4Type = memBaseAddress & BIT0; - pci1ArrayPointer->bar4Base = memBaseAddress & 0xfffff000; - pci1WriteConfigReg(BAR4,device,0xffffffff); - memSize = pci1ReadConfigReg(BAR4,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci1ArrayPointer->bar4Size = 0; - } - else - { - if (pci1ArrayPointer->bar4Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci1ArrayPointer->bar4Size = memSize; - } - /* restore the previous value to BAR_4 base */ - pci1WriteConfigReg(BAR4,device,memBaseAddress); - /* BAR5 parameters */ - memBaseAddress = pci1ReadConfigReg(BAR5,device); - pci1ArrayPointer->bar5Type = memBaseAddress & BIT0; - pci1ArrayPointer->bar5Base = memBaseAddress & 0xfffff000; - pci1WriteConfigReg(BAR5,device,0xffffffff); - memSize = pci1ReadConfigReg(BAR5,device); - if(memSize == 0) /* case of an empty BAR */ - { - pci1ArrayPointer->bar5Size = 0; - } - else - { - if (pci1ArrayPointer->bar5Type == 0) /* memory space */ - memSize = ~(memSize & 0xfffffff0) + 1; - else /* IO space */ - memSize = ~(memSize & 0xfffffffc) + 1; - pci1ArrayPointer->bar5Size = memSize; - } - /* restore the previous value to BAR_5 base */ - pci1WriteConfigReg(BAR5,device,memBaseAddress); - /* End of BARs Detection. */ - - classCode = ( (classCode & 0xff000000 ) >> 24 ); - - switch(classCode) { - case 0x0: - strcpy(pci1ArrayPointer->type,"Old generation device"); - break; - case 0x1: - strcpy(pci1ArrayPointer->type,"Mass storage controller"); - break; - case 0x2: - strcpy(pci1ArrayPointer->type,"Network controller"); - break; - case 0x3: - strcpy(pci1ArrayPointer->type,"Display controller"); - break; - case 0x4: - strcpy(pci1ArrayPointer->type,"Multimedia device"); - break; - case 0x5: - strcpy(pci1ArrayPointer->type,"Memory controller"); - break; - case 0x6: - strcpy(pci1ArrayPointer->type,"Bridge Device"); - break; - case 0x7: - strcpy(pci1ArrayPointer->type,"Simple Communication controllers"); - break; - case 0x8: - strcpy(pci1ArrayPointer->type,"Base system peripherals"); - break; - case 0x9: - strcpy(pci1ArrayPointer->type,"Input Devices"); - break; - case 0xa: - strcpy(pci1ArrayPointer->type,"Docking stations"); - break; - case 0xb: - strcpy(pci1ArrayPointer->type,"Processors"); - break; - case 0xc: - strcpy(pci1ArrayPointer->type,"Serial bus controllers"); - break; - case 0xd: - strcpy(pci1ArrayPointer->type,"Wireless controllers"); - break; - case 0xe: - strcpy(pci1ArrayPointer->type,"Intelligent I/O controllers"); - break; - case 0xf: - strcpy(pci1ArrayPointer->type,"Satellite communication controllers"); - break; - case 0x10: - strcpy(pci1ArrayPointer->type,"Encryption/Decryption controllers"); - break; - case 0x11: - strcpy(pci1ArrayPointer->type,"Data acquisition and \ - signal processing controllers"); - break; - } arrayCounter++; /* point to the next element in the Array. */ if(arrayCounter == numberOfElment) return; /* When the Array is fully used, return. */ /* Else, points to next free Element.*/ - pci1ArrayPointer = &pci1Detect[arrayCounter]; + pciArrayPointer = &pciDetect[arrayCounter]; } } - pci1ArrayPointer->deviceNum = 0; /* 0 => End of List */ + pciArrayPointer->deviceNum = -1; /* -1 => End of List */ } /******************************************************************** -* pci0WriteConfigReg - Write to a PCI configuration register +* pciWriteConfigReg - Write to a PCI configuration register * - Make sure the GT is configured as a master before writing * to another device on the PCI. * - The function takes care of Big/Little endian conversion. @@ -514,66 +246,32 @@ void pci1ScanDevices(PCI_DEVICE* pci1Detect,unsigned int numberOfElment) * |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ -void pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,unsigned int data) -{ - volatile unsigned int DataForRegCf8; - unsigned int functionNum; - unsigned int busNum = 0; - - if(pciDevNum > 32) /* illegal device Number */ - return; - if(pciDevNum == SELF) /* configure our configuration space. */ - { - pciDevNum = (GTREGREAD(PCI_0P2P_CONFIGURATION) >> 24) & 0x1f; - busNum = GTREGREAD(PCI_0P2P_CONFIGURATION) & 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForRegCf8 = ( regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); - GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,data); -} - -/******************************************************************** -* pci1WriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,unsigned int data) +void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,unsigned int pciDevNum,unsigned int data) { - volatile unsigned int DataForRegCf8; + volatile unsigned int DataForAddrReg; unsigned int functionNum; unsigned int busNum = 0; + unsigned int addr; if(pciDevNum > 32) /* illegal device Number */ return; if(pciDevNum == SELF) /* configure our configuration space. */ { - pciDevNum = (GTREGREAD(PCI_1P2P_CONFIGURATION) >> 24) & 0x1f; - busNum = GTREGREAD(PCI_1P2P_CONFIGURATION) & 0xff0000; + pciDevNum = (GTREGREAD(pci_p2p_configuration_reg[host]) >> 24) & 0x1f; + busNum = GTREGREAD(pci_p2p_configuration_reg[host]) & 0xff0000; } - functionNum = regOffset & 0x00000700; + functionNum = regOffset & 0x00000700; pciDevNum = pciDevNum << 11; regOffset = regOffset & 0xfc; - DataForRegCf8 = ( regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS,DataForRegCf8); - GT_REG_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,data); + DataForAddrReg = ( regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE(pci_configuration_address[host],DataForAddrReg); + GT_REG_READ(pci_configuration_address[host], &addr); + if (addr != DataForAddrReg) return; + GT_REG_WRITE(pci_configuration_data[host],data); } /******************************************************************** -* pci0ReadConfigReg - Read from a PCI0 configuration register +* pciReadConfigReg - Read from a PCI0 configuration register * - Make sure the GT is configured as a master before reading * from another device on the PCI. * - The function takes care of Big/Little endian conversion. @@ -590,9 +288,9 @@ void pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,unsigned i * |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ -unsigned int pci0ReadConfigReg (unsigned int regOffset,unsigned int pciDevNum) +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,unsigned int pciDevNum) { - volatile unsigned int DataForRegCf8; + volatile unsigned int DataForAddrReg; unsigned int data; unsigned int functionNum; unsigned int busNum = 0; @@ -601,123 +299,25 @@ unsigned int pci0ReadConfigReg (unsigned int regOffset,unsigned int pciDevNum) return 0xffffffff; if(pciDevNum == SELF) /* configure our configuration space. */ { - pciDevNum = (GTREGREAD(PCI_0P2P_CONFIGURATION) >> 24) & 0x1f; - busNum = GTREGREAD(PCI_0P2P_CONFIGURATION) & 0xff0000; + pciDevNum = (GTREGREAD(pci_p2p_configuration_reg[host]) >> 24) & 0x1f; + busNum = GTREGREAD(pci_p2p_configuration_reg[host]) & 0xff0000; } functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; + pciDevNum = pciDevNum << 11; regOffset = regOffset & 0xfc; - DataForRegCf8 = (regOffset | pciDevNum | functionNum | busNum) | BIT31 ; - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); - GT_REG_READ(PCI_0CONFIGURATION_ADDRESS, &data); - if (data != DataForRegCf8) - return 0xffffffff; - GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, &data); - return data; -} - -/******************************************************************** -* pci1ReadConfigReg - Read from a PCI1 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pci1ReadConfigReg (unsigned int regOffset,unsigned int pciDevNum) -{ - volatile unsigned int DataForRegCf8; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if(pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if(pciDevNum == SELF) /* configure our configuration space. */ - { - pciDevNum = (GTREGREAD(PCI_1P2P_CONFIGURATION) >> 24) & 0x1f; - busNum = GTREGREAD(PCI_1P2P_CONFIGURATION) & 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - DataForRegCf8 = (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS,DataForRegCf8); - GT_REG_READ(PCI_1CONFIGURATION_ADDRESS, &data); - if (data != DataForRegCf8) + DataForAddrReg = (regOffset | pciDevNum | functionNum | busNum) | BIT31 ; + GT_REG_WRITE(pci_configuration_address[host],DataForAddrReg); + GT_REG_READ(pci_configuration_address[host], &data); + if (data != DataForAddrReg) return 0xffffffff; - GT_REG_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, &data); + GT_REG_READ(pci_configuration_data[host], &data); return data; } /******************************************************************** -* pci0OverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pci0OverBridgeWriteConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data) -{ - unsigned int DataForRegCf8; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if(pciDevNum == SELF) /* This board */ - { - DataForRegCf8 = ( regOffset | pciDevNum | functionNum) | BIT0; - } - else - { - DataForRegCf8 = ( regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); - if(pciDevNum == SELF) /* This board */ - { - GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,data); - } - else /* configuration Transaction over the pci. */ - { - /* The PCI is working in LE Mode So it swap the Data. */ - GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,WORD_SWAP(data)); - } -} - -/******************************************************************** -* pci1OverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. +* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. * * Inputs: unsigned int regOffset - The register offset as it apears in the * GT spec (or any other PCI device spec). @@ -736,11 +336,12 @@ void pci0OverBridgeWriteConfigReg(unsigned int regOffset, * PCI spec referring to P2P. * *********************************************************************/ -void pci1OverBridgeWriteConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data) +void pciOverBridgeWriteConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum,unsigned int data) { - unsigned int DataForRegCf8; + unsigned int DataForReg; unsigned int functionNum; functionNum = regOffset & 0x00000700; @@ -749,88 +350,33 @@ void pci1OverBridgeWriteConfigReg(unsigned int regOffset, busNum = busNum << 16; if(pciDevNum == SELF) /* This board */ { - DataForRegCf8 = ( regOffset | pciDevNum | functionNum | 0x80) | BIT31; - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); + DataForReg = ( regOffset | pciDevNum | functionNum) | BIT0; } else { - DataForRegCf8 = ( regOffset | pciDevNum | functionNum | busNum) | + DataForReg = ( regOffset | pciDevNum | functionNum | busNum) | BIT31 | BIT0; - GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS,DataForRegCf8); } + GT_REG_WRITE(pci_configuration_address[host],DataForReg); if(pciDevNum == SELF) /* This board */ { - GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,data); + GT_REG_WRITE(pci_configuration_data[host],data); } else /* configuration Transaction over the pci. */ { /* The PCI is working in LE Mode So it swap the Data. */ - GT_REG_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,WORD_SWAP(data)); + GT_REG_WRITE(pci_configuration_data[host],WORD_SWAP(data)); } } -/******************************************************************** -* pci0OverBridgeReadConfigReg - Read from a PCI0 configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pci0OverBridgeReadConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForRegCf8; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) /* This board */ - { - DataForRegCf8 = (regOffset | pciDevNum | functionNum) | BIT31 ; - } - else /* agent on another bus */ - { - DataForRegCf8 = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31 ; - } - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); - if (pciDevNum == SELF) /* This board */ - { - GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, &data); - return data; - } - else /* The PCI is working in LE Mode So it swap the Data. */ - { - GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, &data); - return WORD_SWAP(data); - } -} /******************************************************************** -* pci1OverBridgeReadConfigReg - Read from a PCI_1 configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. +* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI * spec). (configuration register offset.) * pciDevNum: The device number needs to be addressed. @@ -845,707 +391,148 @@ unsigned int pci0OverBridgeReadConfigReg(unsigned int regOffset, * |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ -unsigned int pci1OverBridgeReadConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) +unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum) { - unsigned int DataForRegCf8; - unsigned int data; + unsigned int DataForReg; + unsigned int data; unsigned int functionNum; functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; + pciDevNum = pciDevNum << 11; regOffset = regOffset & 0xff; busNum = busNum << 16; if (pciDevNum == SELF) /* This board */ { - DataForRegCf8 = (regOffset | pciDevNum | functionNum) | 0x80 | BIT31 ; - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); + DataForReg = (regOffset | pciDevNum | functionNum) | BIT31 ; } else /* agent on another bus */ { - DataForRegCf8 = (regOffset | pciDevNum | functionNum | busNum) | + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | BIT0 | BIT31 ; - GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS,DataForRegCf8); } - GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS,DataForRegCf8); + GT_REG_WRITE(pci_configuration_address[host],DataForReg); if (pciDevNum == SELF) /* This board */ { - GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, &data); + GT_REG_READ(pci_configuration_data[host], &data); return data; } else /* The PCI is working in LE Mode So it swap the Data. */ { - GT_REG_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, &data); + GT_REG_READ(pci_configuration_data[host], &data); return WORD_SWAP(data); } } -/******************************************************************** -* pci0MapIOspace - Maps PCI_0 IO space from the CPU side. -* -* -* Inputs: base and length of pci0 IO -* Return: N/A -*********************************************************************/ -void pci0MapIOspace(unsigned int pci0IoBase,unsigned int pci0IoLength) -{ - unsigned int pci0IoTop = (unsigned int)(pci0IoBase + pci0IoLength); - unsigned int currentLow; - - GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS,¤tLow); - pci0IoBase = pci0IoBase >> 20; - pci0IoBase = (pci0IoBase & 0xffff) | (currentLow & 0xffff0000); - pci0IoTop = pci0IoTop >> 20; - GT_REG_WRITE(PCI_0I_O_LOW_DECODE_ADDRESS,0xffff); - if(pci0IoLength != 0) - { - GT_REG_WRITE(PCI_0I_O_HIGH_DECODE_ADDRESS,pci0IoTop - 1); - GT_REG_WRITE(PCI_0I_O_LOW_DECODE_ADDRESS,pci0IoBase); - } - else - { - GT_REG_WRITE(PCI_0I_O_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci1MapIOspace - Maps PCI_1 IO space for the master. -* Inputs: base and length of pci1Io -*********************************************************************/ -void pci1MapIOspace(unsigned int pci1IoBase,unsigned int pci1IoLength) -{ - unsigned int pci1IoTop = (unsigned int)(pci1IoBase + pci1IoLength); - unsigned int currentLow; - - GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS,¤tLow); - pci1IoBase = pci1IoBase >> 20; - pci1IoBase = (pci1IoBase & 0xffff) | (currentLow & 0xffff0000); - pci1IoTop = pci1IoTop >> 20; - GT_REG_WRITE(PCI_1I_O_LOW_DECODE_ADDRESS,0xffff); - if(pci1IoLength != 0) - { - GT_REG_WRITE(PCI_1I_O_HIGH_DECODE_ADDRESS,pci1IoTop - 1); - GT_REG_WRITE(PCI_1I_O_LOW_DECODE_ADDRESS,pci1IoBase); - } - else - { - GT_REG_WRITE(PCI_1I_O_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci0MapMemory0space - Maps PCI_0 memory0 space for the master. -* Inputs: base and length of pci0Mem0 -*********************************************************************/ -void pci0MapMemory0space(unsigned int pci0Mem0Base,unsigned int pci0Mem0Length) -{ - unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length; - unsigned int currentLow; - - GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS,¤tLow); - pci0Mem0Base = pci0Mem0Base >> 20; - pci0Mem0Base = (pci0Mem0Base & 0xffff) | (currentLow & 0xffff0000); - pci0Mem0Top = pci0Mem0Top >> 20; - GT_REG_WRITE(PCI_0MEMORY0_LOW_DECODE_ADDRESS,0xffff); - if(pci0Mem0Length != 0) - { - GT_REG_WRITE(PCI_0MEMORY0_HIGH_DECODE_ADDRESS,pci0Mem0Top - 1); - GT_REG_WRITE(PCI_0MEMORY0_LOW_DECODE_ADDRESS,pci0Mem0Base); - } - else - { - GT_REG_WRITE(PCI_0MEMORY0_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci1MapMemory0space - Maps PCI_1 memory0 space for the master. -* Inputs: base and length of pci1Mem0 -*********************************************************************/ -void pci1MapMemory0space(unsigned int pci1Mem0Base,unsigned int pci1Mem0Length) -{ - unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length; - unsigned int currentLow; - - GT_REG_READ(PCI_1MEMORY0_LOW_DECODE_ADDRESS,¤tLow); - pci1Mem0Base = pci1Mem0Base >> 20; - pci1Mem0Base = (pci1Mem0Base & 0xffff) | (currentLow & 0xffff0000); - pci1Mem0Top = pci1Mem0Top >> 20; - GT_REG_WRITE(PCI_1MEMORY0_LOW_DECODE_ADDRESS,0xffff); - if(pci1Mem0Length != 0) - { - GT_REG_WRITE(PCI_1MEMORY0_HIGH_DECODE_ADDRESS,pci1Mem0Top - 1); - GT_REG_WRITE(PCI_1MEMORY0_LOW_DECODE_ADDRESS,pci1Mem0Base); - } - else - { - GT_REG_WRITE(PCI_1MEMORY0_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci0MapMemory1space - Maps PCI_0 memory1 space for the master. -* Inputs: base and length of pci0Mem1 -*********************************************************************/ -void pci0MapMemory1space(unsigned int pci0Mem1Base,unsigned int pci0Mem1Length) -{ - unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length; - unsigned int currentLow; - - GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS,¤tLow); - pci0Mem1Base = pci0Mem1Base >> 20; - pci0Mem1Base = (pci0Mem1Base & 0xffff) | (currentLow & 0xffff0000); - pci0Mem1Top = pci0Mem1Top >> 20; - GT_REG_WRITE(PCI_0MEMORY1_LOW_DECODE_ADDRESS,0xffff); - if(pci0Mem1Length != 0) - { - GT_REG_WRITE(PCI_0MEMORY1_HIGH_DECODE_ADDRESS,pci0Mem1Top - 1); - GT_REG_WRITE(PCI_0MEMORY1_LOW_DECODE_ADDRESS,pci0Mem1Base); - } - else - { - GT_REG_WRITE(PCI_0MEMORY1_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci1MapMemory1space - Maps PCI_1 memory1 space for the master. -* Inputs: base and length of pci1Mem1 -*********************************************************************/ -void pci1MapMemory1space(unsigned int pci1Mem1Base,unsigned int pci1Mem1Length) -{ - unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length; - unsigned int currentLow; - - GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS,¤tLow); - pci1Mem1Base = pci1Mem1Base >> 20; - pci1Mem1Base = (pci1Mem1Base & 0xffff) | (currentLow & 0xffff0000); - pci1Mem1Top = pci1Mem1Top >> 20; - GT_REG_WRITE(PCI_1MEMORY1_LOW_DECODE_ADDRESS,0xffff); - if(pci1Mem1Length != 0) - { - GT_REG_WRITE(PCI_1MEMORY1_HIGH_DECODE_ADDRESS,pci1Mem1Top - 1); - GT_REG_WRITE(PCI_1MEMORY1_LOW_DECODE_ADDRESS,pci1Mem1Base); - } - else - { - GT_REG_WRITE(PCI_1MEMORY1_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci0MapMemory2space - Maps PCI_0 memory2 space for the master. -* Inputs: base and length of pci0Mem2 -*********************************************************************/ -void pci0MapMemory2space(unsigned int pci0Mem2Base,unsigned int pci0Mem2Length) -{ - unsigned int pci0Mem2Top = pci0Mem2Base + pci0Mem2Length; - unsigned int currentLow; - - GT_REG_READ(PCI_0MEMORY2_LOW_DECODE_ADDRESS,¤tLow); - pci0Mem2Base = pci0Mem2Base >> 20; - pci0Mem2Base = (pci0Mem2Base & 0xffff) | (currentLow & 0xffff0000); - pci0Mem2Top = pci0Mem2Top >> 20; - GT_REG_WRITE(PCI_0MEMORY2_LOW_DECODE_ADDRESS,0xffff); - if(pci0Mem2Length != 0) - { - GT_REG_WRITE(PCI_0MEMORY2_HIGH_DECODE_ADDRESS,pci0Mem2Top - 1); - GT_REG_WRITE(PCI_0MEMORY2_LOW_DECODE_ADDRESS,pci0Mem2Base); - } - else - { - GT_REG_WRITE(PCI_0MEMORY2_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci1MapMemory2space - Maps PCI_1 memory2 space for the master. -* Inputs: base and length of pci1Mem2 -*********************************************************************/ -void pci1MapMemory2space(unsigned int pci1Mem2Base,unsigned int pci1Mem2Length) -{ - unsigned int pci1Mem2Top = pci1Mem2Base + pci1Mem2Length; - unsigned int currentLow; - - GT_REG_READ(PCI_1MEMORY2_LOW_DECODE_ADDRESS,¤tLow); - pci1Mem2Base = pci1Mem2Base >> 20; - pci1Mem2Base = (pci1Mem2Base & 0xffff) | (currentLow & 0xffff0000); - pci1Mem2Top = pci1Mem2Top >> 20; - GT_REG_WRITE(PCI_1MEMORY2_LOW_DECODE_ADDRESS,0xffff); - if(pci1Mem2Length != 0) - { - GT_REG_WRITE(PCI_1MEMORY2_HIGH_DECODE_ADDRESS,pci1Mem2Top - 1); - GT_REG_WRITE(PCI_1MEMORY2_LOW_DECODE_ADDRESS,pci1Mem2Base); - } - else - { - GT_REG_WRITE(PCI_1MEMORY2_HIGH_DECODE_ADDRESS,0x0); - } -} - - -/******************************************************************** -* pci0MapMemory3space - Maps PCI_0 memory3 space for the master. -* Inputs: base and length of pci0Mem3 -*********************************************************************/ -void pci0MapMemory3space(unsigned int pci0Mem3Base,unsigned int pci0Mem3Length) -{ - unsigned int pci0Mem3Top = pci0Mem3Base + pci0Mem3Length; - unsigned int currentLow; - - GT_REG_READ(PCI_0MEMORY3_LOW_DECODE_ADDRESS,¤tLow); - pci0Mem3Base = pci0Mem3Base >> 20; - pci0Mem3Base = (pci0Mem3Base & 0xffff) | (currentLow & 0xffff0000); - pci0Mem3Top = pci0Mem3Top >> 20; - GT_REG_WRITE(PCI_0MEMORY3_LOW_DECODE_ADDRESS,0xffff); - if(pci0Mem3Length != 0) - { - GT_REG_WRITE(PCI_0MEMORY3_HIGH_DECODE_ADDRESS,pci0Mem3Top - 1); - GT_REG_WRITE(PCI_0MEMORY3_LOW_DECODE_ADDRESS,pci0Mem3Base); - } - else - { - GT_REG_WRITE(PCI_0MEMORY3_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci1MapMemory3space - Maps PCI_1 memory3 space for the master. -* Inputs: base and length of pci1Mem3 -*********************************************************************/ -void pci1MapMemory3space(unsigned int pci1Mem3Base,unsigned int pci1Mem3Length) -{ - unsigned int pci1Mem3Top = pci1Mem3Base + pci1Mem3Length; - unsigned int currentLow; - - GT_REG_READ(PCI_1MEMORY3_LOW_DECODE_ADDRESS,¤tLow); - pci1Mem3Base = pci1Mem3Base >> 20; - pci1Mem3Base = (pci1Mem3Base & 0xffff) | (currentLow & 0xffff0000); - pci1Mem3Top = pci1Mem3Top >> 20; - GT_REG_WRITE(PCI_1MEMORY3_LOW_DECODE_ADDRESS,0xffff); - if(pci1Mem3Length != 0) - { - GT_REG_WRITE(PCI_1MEMORY3_HIGH_DECODE_ADDRESS,pci1Mem3Top - 1); - GT_REG_WRITE(PCI_1MEMORY3_LOW_DECODE_ADDRESS,pci1Mem3Base); - } - else - { - GT_REG_WRITE(PCI_1MEMORY3_HIGH_DECODE_ADDRESS,0x0); - } -} - -/******************************************************************** -* pci0GetIOspaceBase - Return PCI_0 IO Base Address. -* Inputs: N/A -* Returns: PCI0 IO Base Address. -*********************************************************************/ -unsigned int pci0GetIOspaceBase() -{ - unsigned int base; - - GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci0GetIOspaceSize - Return PCI_0 IO Bar Size. -* Inputs: N/A -* Returns: PCI0 IO Bar Size. -*********************************************************************/ -unsigned int pci0GetIOspaceSize() -{ - unsigned int top,base,size; - - GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_0I_O_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci0GetMemory0Base - Return PCI_0 Memory 0 Base Address. -* Inputs: N/A -* Returns: PCI0 Memory 0 Base Address. -*********************************************************************/ -unsigned int pci0GetMemory0Base() -{ - unsigned int base; - - GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci0GetMemory0Size - Return PCI_0 Memory 0 Bar Size. -* Inputs: N/A -* Returns: PCI0 Memory 0 Bar Size. -*********************************************************************/ -unsigned int pci0GetMemory0Size() -{ - unsigned int top,base,size; - - GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_0MEMORY0_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci0GetMemory1Base - Return PCI_0 Memory 1 Base Address. -* Inputs: N/A -* Returns: PCI0 Memory 1 Base Address. -*********************************************************************/ -unsigned int pci0GetMemory1Base() -{ - unsigned int base; - - GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci0GetMemory1Size - Return PCI_0 Memory 1 Bar Size. -* Inputs: N/A -* Returns: PCI0 Memory 1 Bar Size. -*********************************************************************/ -unsigned int pci0GetMemory1Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_0MEMORY1_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci0GetMemory2Base - Return PCI_0 Memory 2 Base Address. -* Inputs: N/A -* Returns: PCI0 Memory 2 Base Address. -*********************************************************************/ -unsigned int pci0GetMemory2Base() -{ - unsigned int base; - GT_REG_READ(PCI_0MEMORY2_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci0GetMemory2Size - Return PCI_0 Memory 2 Bar Size. -* Inputs: N/A -* Returns: PCI0 Memory 2 Bar Size. -*********************************************************************/ -unsigned int pci0GetMemory2Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_0MEMORY2_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_0MEMORY2_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci0GetMemory3Base - Return PCI_0 Memory 3 Base Address. -* Inputs: N/A -* Returns: PCI0 Memory 3 Base Address. -*********************************************************************/ -unsigned int pci0GetMemory3Base() -{ - unsigned int base; - GT_REG_READ(PCI_0MEMORY3_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci0GetMemory3Size - Return PCI_0 Memory 3 Bar Size. -* Inputs: N/A -* Returns: PCI0 Memory 3 Bar Size. -*********************************************************************/ -unsigned int pci0GetMemory3Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_0MEMORY3_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_0MEMORY3_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci1GetIOspaceBase - Return PCI_1 IO Base Address. -* Inputs: N/A -* Returns: PCI1 IO Base Address. -*********************************************************************/ -unsigned int pci1GetIOspaceBase() -{ - unsigned int base; - GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci1GetIOspaceSize - Return PCI_1 IO Bar Size. -* Inputs: N/A -* Returns: PCI1 IO Bar Size. -*********************************************************************/ -unsigned int pci1GetIOspaceSize() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_1I_O_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci1GetMemory0Base - Return PCI_1 Memory 0 Base Address. -* Inputs: N/A -* Returns: PCI1 Memory 0 Base Address. -*********************************************************************/ -unsigned int pci1GetMemory0Base() -{ - unsigned int base; - GT_REG_READ(PCI_1MEMORY0_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci1GetMemory0Size - Return PCI_1 Memory 0 Bar Size. -* Inputs: N/A -* Returns: PCI1 Memory 0 Bar Size. -*********************************************************************/ -unsigned int pci1GetMemory0Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_1MEMORY1_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci1GetMemory1Base - Return PCI_1 Memory 1 Base Address. -* Inputs: N/A -* Returns: PCI1 Memory 1 Base Address. -*********************************************************************/ -unsigned int pci1GetMemory1Base() -{ - unsigned int base; - GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci1GetMemory1Size - Return PCI_1 Memory 1 Bar Size. -* Inputs: N/A -* Returns: PCI1 Memory 1 Bar Size. -*********************************************************************/ -unsigned int pci1GetMemory1Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_1MEMORY1_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci1GetMemory1Base - Return PCI_1 Memory 2 Base Address. -* Inputs: N/A -* Returns: PCI1 Memory 2 Base Address. -*********************************************************************/ -unsigned int pci1GetMemory2Base() -{ - unsigned int base; - GT_REG_READ(PCI_1MEMORY2_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci1GetMemory1Size - Return PCI_1 Memory 2 Bar Size. -* Inputs: N/A -* Returns: PCI1 Memory 2 Bar Size. -*********************************************************************/ -unsigned int pci1GetMemory2Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_1MEMORY2_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_1MEMORY2_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - -/******************************************************************** -* pci1GetMemory3Base - Return PCI_1 Memory 3 Base Address. -* Inputs: N/A -* Returns: PCI1 Memory 3 Base Address. -*********************************************************************/ -unsigned int pci1GetMemory3Base() -{ - unsigned int base; - GT_REG_READ(PCI_1MEMORY3_LOW_DECODE_ADDRESS,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* pci1GetMemory3Size - Return PCI_1 Memory 3 Bar Size. -* Inputs: N/A -* Returns: PCI1 Memory 3 Bar Size. -*********************************************************************/ -unsigned int pci1GetMemory3Size() -{ - unsigned int top,base,size; - GT_REG_READ(PCI_1MEMORY3_LOW_DECODE_ADDRESS,&base); - base = base << 20; - GT_REG_READ(PCI_1MEMORY3_HIGH_DECODE_ADDRESS,&top); - top = (top << 20); - size = (top - base); - size = size | 0xfffff; - return (size + 1); -} - +#if 0 // FIXME eventually - this is crap /******************************************************************** * pci0ScanSelfBars - update in PCI_SELF_BARS struct all bars base and sizes. * * Inputs: PCI_SELF_BARS *pci0SelfBars - the struct which the data will be update * in. *********************************************************************/ -void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars) +void pci0ScanSelfBars(PCI_SELF_BARS *pciSelfBars) { unsigned int size; - pci0SelfBars->SCS0Base = pci0ReadConfigReg(PCI_SCS_0_BASE_ADDRESS,SELF) & + pciSelfBars->SCS0Base = pciReadConfigReg(0,PCI_SCS_0_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_0_BANK_SIZE); if(size) - pci0SelfBars->SCS0Size = size + 0x1000; + pciSelfBars->SCS0Size = size + 0x1000; else - pci0SelfBars->SCS0Size = 0; - pci0SelfBars->SCS1Base = pci0ReadConfigReg(PCI_SCS_1_BASE_ADDRESS,SELF) & + pciSelfBars->SCS0Size = 0; + pciSelfBars->SCS1Base = pciReadConfigReg(0,PCI_SCS_1_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_1_BANK_SIZE); if(size) - pci0SelfBars->SCS1Size = size + 0x1000; + pciSelfBars->SCS1Size = size + 0x1000; else - pci0SelfBars->SCS1Size = 0; - pci0SelfBars->SCS2Base = pci0ReadConfigReg(PCI_SCS_2_BASE_ADDRESS,SELF) & + pciSelfBars->SCS1Size = 0; + pciSelfBars->SCS2Base = pciReadConfigReg(0,PCI_SCS_2_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_2_BANK_SIZE); if(size) - pci0SelfBars->SCS2Size = size + 0x1000; + pciSelfBars->SCS2Size = size + 0x1000; else - pci0SelfBars->SCS2Size = 0; - pci0SelfBars->SCS3Base = pci0ReadConfigReg(PCI_SCS_3_BASE_ADDRESS,SELF) & + pciSelfBars->SCS2Size = 0; + pciSelfBars->SCS3Base = pciReadConfigReg(0,PCI_SCS_3_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_3_BANK_SIZE); if(size) - pci0SelfBars->SCS3Size = size + 0x1000; + pciSelfBars->SCS3Size = size + 0x1000; else size = 0; - pci0SelfBars->CS0Base = pci0ReadConfigReg(PCI_CS_0_BASE_ADDRESS,SELF) & + pciSelfBars->CS0Base = pciReadConfigReg(0,PCI_CS_0_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_0_BANK_SIZE); if(size) - pci0SelfBars->CS0Size = size + 0x1000; + pciSelfBars->CS0Size = size + 0x1000; else - pci0SelfBars->CS0Size = 0; - pci0SelfBars->CS1Base = pci0ReadConfigReg(PCI_CS_1_BASE_ADDRESS,SELF) & + pciSelfBars->CS0Size = 0; + pciSelfBars->CS1Base = pciReadConfigReg(0,PCI_CS_1_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_1_BANK_SIZE); if(size) - pci0SelfBars->CS1Size = size + 0x1000; + pciSelfBars->CS1Size = size + 0x1000; else - pci0SelfBars->CS1Size = 0; - pci0SelfBars->CS2Base = pci0ReadConfigReg(PCI_CS_2_BASE_ADDRESS,SELF) & + pciSelfBars->CS1Size = 0; + pciSelfBars->CS2Base = pciReadConfigReg(0,PCI_CS_2_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_2_BANK_SIZE); if(size) - pci0SelfBars->CS2Size = size + 0x1000; + pciSelfBars->CS2Size = size + 0x1000; else - pci0SelfBars->CS2Size = 0; - pci0SelfBars->CS3Base = pci0ReadConfigReg(PCI_CS_3_BASE_ADDRESS,SELF) & + pciSelfBars->CS2Size = 0; + pciSelfBars->CS3Base = pciReadConfigReg(0,PCI_CS_3_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_3_BANK_SIZE); if(size) - pci0SelfBars->CS3Size = size + 0x1000; + pciSelfBars->CS3Size = size + 0x1000; else - pci0SelfBars->CS3Size = 0; - pci0SelfBars->CSBootBase = pci0ReadConfigReg(PCI_BOOTCS_BASE_ADDRESS,SELF) & + pciSelfBars->CS3Size = 0; + pciSelfBars->CSBootBase = pciReadConfigReg(0,PCI_BOOTCS_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_BOOT_BANK_SIZE); if(size) - pci0SelfBars->CSBootSize = size + 0x1000; + pciSelfBars->CSBootSize = size + 0x1000; else - pci0SelfBars->CSBootSize = 0; - pci0SelfBars->internalMemBase = pci0ReadConfigReg( + pciSelfBars->CSBootSize = 0; + pciSelfBars->internalMemBase = pciReadConfigReg(0, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0xfffff000; - pci0SelfBars->internalIOBase = pci0ReadConfigReg( + pciSelfBars->internalIOBase = pciReadConfigReg(0, PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0xfffff000; - pci0SelfBars->P2PMem0Base = pci0ReadConfigReg(PCI_P2P_MEM0_BASE_ADDRESS,SELF) & + pciSelfBars->P2PMem0Base = pciReadConfigReg(0,PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0P2P_MEM0_BAR_SIZE); if(size) - pci0SelfBars->P2PMem0Size = size + 0x1000; + pciSelfBars->P2PMem0Size = size + 0x1000; else - pci0SelfBars->P2PMem0Size = 0; - pci0SelfBars->P2PMem1Base = pci0ReadConfigReg(PCI_P2P_MEM1_BASE_ADDRESS,SELF) & + pciSelfBars->P2PMem0Size = 0; + pciSelfBars->P2PMem1Base = pciReadConfigReg(0,PCI_P2P_MEM1_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0P2P_MEM1_BAR_SIZE); if(size) - pci0SelfBars->P2PMem1Size = size + 0x1000; + pciSelfBars->P2PMem1Size = size + 0x1000; else - pci0SelfBars->P2PMem1Size = 0; - pci0SelfBars->P2PIOBase = pci0ReadConfigReg(PCI_P2P_I_O_BASE_ADDRESS,SELF) & + pciSelfBars->P2PMem1Size = 0; + pciSelfBars->P2PIOBase = pciReadConfigReg(0,PCI_P2P_I_O_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0P2P_I_O_BAR_SIZE); if(size) - pci0SelfBars->P2PIOSize = size + 0x1000; + pciSelfBars->P2PIOSize = size + 0x1000; else - pci0SelfBars->P2PIOSize = 0; - pci0SelfBars->CPUBase = pci0ReadConfigReg(PCI_CPU_BASE_ADDRESS,SELF) & + pciSelfBars->P2PIOSize = 0; + pciSelfBars->CPUBase = pciReadConfigReg(0,PCI_CPU_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CPU_BAR_SIZE); if(size) - pci0SelfBars->CPUSize = size + 0x1000; + pciSelfBars->CPUSize = size + 0x1000; else - pci0SelfBars->CPUSize = 0; + pciSelfBars->CPUSize = 0; } /******************************************************************** @@ -1554,296 +541,305 @@ void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars) * Inputs: PCI_SELF_BARS *pci1SelfBars - the struct which the data will be update * in. *********************************************************************/ -void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars) +void pci1ScanSelfBars(PCI_SELF_BARS *pciSelfBars) { unsigned int size; - pci1SelfBars->SCS0Base = pci1ReadConfigReg(PCI_SCS_0_BASE_ADDRESS,SELF) & + pciSelfBars->SCS0Base = pciReadConfigReg(1,PCI_SCS_0_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_0_BANK_SIZE); if(size) - pci1SelfBars->SCS0Size = size + 0x1000; + pciSelfBars->SCS0Size = size + 0x1000; else - pci1SelfBars->SCS0Size = 0; - pci1SelfBars->SCS1Base = pci1ReadConfigReg(PCI_SCS_1_BASE_ADDRESS,SELF) & + pciSelfBars->SCS0Size = 0; + pciSelfBars->SCS1Base = pciReadConfigReg(1,PCI_SCS_1_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_1_BANK_SIZE); if(size) - pci1SelfBars->SCS1Size = size + 0x1000; + pciSelfBars->SCS1Size = size + 0x1000; else - pci1SelfBars->SCS1Size = 0; - pci1SelfBars->SCS2Base = pci1ReadConfigReg(PCI_SCS_2_BASE_ADDRESS,SELF) & + pciSelfBars->SCS1Size = 0; + pciSelfBars->SCS2Base = pciReadConfigReg(1,PCI_SCS_2_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_2_BANK_SIZE); if(size) - pci1SelfBars->SCS2Size = size + 0x1000; + pciSelfBars->SCS2Size = size + 0x1000; else - pci1SelfBars->SCS2Size = 0; - pci1SelfBars->SCS3Base = pci1ReadConfigReg(PCI_SCS_3_BASE_ADDRESS,SELF) & + pciSelfBars->SCS2Size = 0; + pciSelfBars->SCS3Base = pciReadConfigReg(1,PCI_SCS_3_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0SCS_3_BANK_SIZE); if(size) - pci1SelfBars->SCS3Size = size + 0x1000; + pciSelfBars->SCS3Size = size + 0x1000; else size = 0; - pci1SelfBars->CS0Base = pci1ReadConfigReg(PCI_CS_0_BASE_ADDRESS,SELF) & + pciSelfBars->CS0Base = pciReadConfigReg(1,PCI_CS_0_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_0_BANK_SIZE); if(size) - pci1SelfBars->CS0Size = size + 0x1000; + pciSelfBars->CS0Size = size + 0x1000; else - pci1SelfBars->CS0Size = 0; - pci1SelfBars->CS1Base = pci1ReadConfigReg(PCI_CS_1_BASE_ADDRESS,SELF) & + pciSelfBars->CS0Size = 0; + pciSelfBars->CS1Base = pciReadConfigReg(1,PCI_CS_1_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_1_BANK_SIZE); if(size) - pci1SelfBars->CS1Size = size + 0x1000; + pciSelfBars->CS1Size = size + 0x1000; else - pci1SelfBars->CS1Size = 0; - pci1SelfBars->CS2Base = pci1ReadConfigReg(PCI_CS_2_BASE_ADDRESS,SELF) & + pciSelfBars->CS1Size = 0; + pciSelfBars->CS2Base = pciReadConfigReg(1,PCI_CS_2_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_2_BANK_SIZE); if(size) - pci1SelfBars->CS2Size = size + 0x1000; + pciSelfBars->CS2Size = size + 0x1000; else - pci1SelfBars->CS2Size = 0; - pci1SelfBars->CS3Base = pci1ReadConfigReg(PCI_CS_3_BASE_ADDRESS,SELF) & + pciSelfBars->CS2Size = 0; + pciSelfBars->CS3Base = pciReadConfigReg(1,PCI_CS_3_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_3_BANK_SIZE); if(size) - pci1SelfBars->CS3Size = size + 0x1000; + pciSelfBars->CS3Size = size + 0x1000; else - pci1SelfBars->CS3Size = 0; - pci1SelfBars->CSBootBase = pci1ReadConfigReg(PCI_BOOTCS_BASE_ADDRESS,SELF) & + pciSelfBars->CS3Size = 0; + pciSelfBars->CSBootBase = pciReadConfigReg(1,PCI_BOOTCS_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CS_BOOT_BANK_SIZE); if(size) - pci1SelfBars->CSBootSize = size + 0x1000; + pciSelfBars->CSBootSize = size + 0x1000; else - pci1SelfBars->CSBootSize = 0; - pci1SelfBars->internalMemBase = pci1ReadConfigReg( + pciSelfBars->CSBootSize = 0; + pciSelfBars->internalMemBase = pciReadConfigReg(1, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0xfffff000; - pci1SelfBars->internalIOBase = pci1ReadConfigReg( + pciSelfBars->internalIOBase = pciReadConfigReg(1, PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0xfffff000; - pci1SelfBars->P2PMem0Base = pci1ReadConfigReg(PCI_P2P_MEM0_BASE_ADDRESS,SELF) & + pciSelfBars->P2PMem0Base = pciReadConfigReg(1,PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0P2P_MEM0_BAR_SIZE); if(size) - pci1SelfBars->P2PMem0Size = size + 0x1000; + pciSelfBars->P2PMem0Size = size + 0x1000; else - pci1SelfBars->P2PMem0Size = 0; - pci1SelfBars->P2PMem1Base = pci1ReadConfigReg(PCI_P2P_MEM1_BASE_ADDRESS,SELF) & + pciSelfBars->P2PMem0Size = 0; + pciSelfBars->P2PMem1Base = pciReadConfigReg(1,PCI_P2P_MEM1_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0P2P_MEM1_BAR_SIZE); if(size) - pci1SelfBars->P2PMem1Size = size + 0x1000; + pciSelfBars->P2PMem1Size = size + 0x1000; else - pci1SelfBars->P2PMem1Size = 0; - pci1SelfBars->P2PIOBase = pci1ReadConfigReg(PCI_P2P_I_O_BASE_ADDRESS,SELF) & + pciSelfBars->P2PMem1Size = 0; + pciSelfBars->P2PIOBase = pciReadConfigReg(1,PCI_P2P_I_O_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0P2P_I_O_BAR_SIZE); if(size) - pci1SelfBars->P2PIOSize = size + 0x1000; + pciSelfBars->P2PIOSize = size + 0x1000; else - pci1SelfBars->P2PIOSize = 0; - pci1SelfBars->CPUBase = pci1ReadConfigReg(PCI_CPU_BASE_ADDRESS,SELF) & + pciSelfBars->P2PIOSize = 0; + pciSelfBars->CPUBase = pciReadConfigReg(1,PCI_CPU_BASE_ADDRESS,SELF) & 0xfffff000; size = GTREGREAD(PCI_0CPU_BAR_SIZE); if(size) - pci1SelfBars->CPUSize = size + 0x1000; + pciSelfBars->CPUSize = size + 0x1000; else - pci1SelfBars->CPUSize = 0; + pciSelfBars->CPUSize = 0; } +#endif /******************************************************************** -* pci0MapInternalRegSpace - Maps the internal registers memory space for the -* slave. +* pciGetRegOffset - Gets the register offset for this region config. * -* Inputs: base of pci0 internal register +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI register base address *********************************************************************/ -void pci0MapInternalRegSpace(unsigned int pci0InternalBase) +static unsigned int pciGetRegOffset(PCI_HOST host, PCI_REGION region) { - pci0InternalBase = pci0InternalBase & 0xfffff000; - pci0InternalBase = pci0InternalBase | (pci0ReadConfigReg( - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF, - pci0InternalBase); + switch (host) + { + case PCI_HOST0: + switch(region) { + case PCI_IO: return PCI_0I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: return PCI_0MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: return PCI_0MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: return PCI_0MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: return PCI_0MEMORY3_LOW_DECODE_ADDRESS; + } + case PCI_HOST1: + switch(region) { + case PCI_IO: return PCI_1I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: return PCI_1MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: return PCI_1MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: return PCI_1MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: return PCI_1MEMORY3_LOW_DECODE_ADDRESS; + } + } + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; } -/******************************************************************** -* pci1MapInternalRegSpace - Maps the internal registers memory space for the -* slave. -* -* Inputs: base of pci1 internal register -*********************************************************************/ -void pci1MapInternalRegSpace(unsigned int pci1InternalBase) +static unsigned int pciGetRemapOffset(PCI_HOST host, PCI_REGION region) { - pci1InternalBase = pci1InternalBase & 0xfffff000; - pci1InternalBase = pci1InternalBase | (pci1ReadConfigReg( - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF, - pci1InternalBase); + switch (host) + { + case PCI_HOST0: + switch(region) { + case PCI_IO: return PCI_0I_O_ADDRESS_REMAP; + case PCI_REGION0: return PCI_0MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: return PCI_0MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: return PCI_0MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: return PCI_0MEMORY3_ADDRESS_REMAP; + } + case PCI_HOST1: + switch(region) { + case PCI_IO: return PCI_1I_O_ADDRESS_REMAP; + case PCI_REGION0: return PCI_1MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: return PCI_1MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: return PCI_1MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: return PCI_1MEMORY3_ADDRESS_REMAP; + } + } + return PCI_0MEMORY0_ADDRESS_REMAP; } /******************************************************************** -* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the -* slave. +* pciGetBaseAddress - Gets the base address of a PCI. +* - If the PCI size is 0 then this base address has no meaning!!! * -* Inputs: base of pci0 internal io register +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI base address. *********************************************************************/ -void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase) +unsigned int pciGetBaseAddress(PCI_HOST host, PCI_REGION region) { - pci0InternalBase = pci0InternalBase & 0xfffff000; - pci0InternalBase = pci0InternalBase | (pci0ReadConfigReg( - PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF, - pci0InternalBase); -} + unsigned int regBase; + unsigned int regEnd; + unsigned int regOffset=pciGetRegOffset(host, region); -/******************************************************************** -* pci1MapInternalRegIOSpace - Maps the internal registers IO space for the -* slave. -* Inputs: base of pci1 internal io register -*********************************************************************/ -void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase) -{ - pci1InternalBase = pci1InternalBase & 0xfffff000; - pci1InternalBase = pci1InternalBase | (pci1ReadConfigReg( - PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF, - pci1InternalBase); + GT_REG_READ(regOffset, ®Base); + GT_REG_READ(regOffset+8, ®End); + + if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ + + regBase = regBase << 20; + return regBase; } -/******************************************************************** -* pci0MapMemoryBank0 - Maps PCI0 memory bank 0 for the slave. -* -* Inputs: base and size of PCI0 SCS0 -*********************************************************************/ -void pci0MapMemoryBank0(unsigned int pci0Dram0Base,unsigned int pci0Dram0Size) +bool pciMapSpace(PCI_HOST host, PCI_REGION region, unsigned int remapBase, unsigned int bankBase,unsigned int bankLength) { - pci0Dram0Base = pci0Dram0Base & 0xfffff000; - pci0Dram0Base = pci0Dram0Base | (pci0ReadConfigReg( - PCI_SCS_0_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_SCS_0_BASE_ADDRESS,SELF,pci0Dram0Base); - if(pci0Dram0Size == 0) - pci0Dram0Size ++; - GT_REG_WRITE(PCI_0SCS_0_BANK_SIZE, pci0Dram0Size-1); + unsigned int low=0xfff; + unsigned int high=0x0; + unsigned int regOffset=pciGetRegOffset(host, region); + unsigned int remapOffset=pciGetRemapOffset(host, region); + + if(bankLength!=0) { + low = (bankBase >> 20) & 0xfff; + high=((bankBase+bankLength)>>20)-1; + } + + GT_REG_WRITE(regOffset, low | (1<<24)); /* no swapping */ + GT_REG_WRITE(regOffset+8, high); + + if(bankLength!=0) { /* must do AFTER writing maps */ + GT_REG_WRITE(remapOffset, remapBase>>20); /* sorry, 32 bits only. + dont support upper 32 + in this driver */ + } + return true; } -/******************************************************************** -* pci0MapMemoryBank1 - Maps PCI0 memory bank 1 for the slave. -* -* Inputs: base and size of PCI0 SCS1 -*********************************************************************/ -void pci0MapMemoryBank1(unsigned int pci0Dram1Base,unsigned int pci0Dram1Size) +unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region) { - pci0Dram1Base = pci0Dram1Base & 0xfffff000; - pci0Dram1Base = pci0Dram1Base | (pci0ReadConfigReg( - PCI_SCS_1_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_SCS_1_BASE_ADDRESS,SELF,pci0Dram1Base); - if(pci0Dram1Size == 0) - pci0Dram1Size ++; - GT_REG_WRITE(PCI_0SCS_1_BANK_SIZE, pci0Dram1Size-1); + unsigned int low; + unsigned int regOffset=pciGetRegOffset(host, region); + GT_REG_READ(regOffset,&low); + return (low&0xfff)<<20; } - -/******************************************************************** -* pci1MapMemoryBank0 - Maps PCI1 memory bank 0 for the slave. -* -* Inputs: base and size of PCI1 SCS0 -*********************************************************************/ -void pci1MapMemoryBank0(unsigned int pci1Dram0Base, - unsigned int pci1Dram0Size) +unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region) { - pci1Dram0Base = pci1Dram0Base & 0xfffff000; - pci1Dram0Base = pci1Dram0Base | (pci1ReadConfigReg( - PCI_SCS_0_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_SCS_0_BASE_ADDRESS,SELF,pci1Dram0Base); - if(pci1Dram0Size == 0) - pci1Dram0Size ++; - GT_REG_WRITE(PCI_1SCS_0_BANK_SIZE, pci1Dram0Size-1); + unsigned int low,high; + unsigned int regOffset=pciGetRegOffset(host, region); + GT_REG_READ(regOffset,&low); + GT_REG_READ(regOffset+8,&high); + high&=0xfff; + low&=0xfff; + if(high<=low) return 0; + return (high+1-low)<<20; } /******************************************************************** -* pci1MapMemoryBank1 - Maps PCI1 memory bank 1 for the slave. +* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. * -* Inputs: base and size of PCI1 SCS1 +* Inputs: base and size of PCI SCS *********************************************************************/ -void pci1MapMemoryBank1(unsigned int pci1Dram1Base,unsigned int pci1Dram1Size) +void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, unsigned int pciDramBase,unsigned int pciDramSize) { - pci1Dram1Base = pci1Dram1Base & 0xfffff000; - pci1Dram1Base = pci1Dram1Base | (pci1ReadConfigReg( - PCI_SCS_1_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_SCS_1_BASE_ADDRESS,SELF,pci1Dram1Base); - if(pci1Dram1Size == 0) - pci1Dram1Size ++; - GT_REG_WRITE(PCI_1SCS_1_BANK_SIZE, pci1Dram1Size-1); + pciDramBase = pciDramBase & 0xfffff000; + pciDramBase = pciDramBase | (pciReadConfigReg(host, + PCI_SCS_0_BASE_ADDRESS + 4*bank,SELF) & 0x00000fff); + pciWriteConfigReg(host,PCI_SCS_0_BASE_ADDRESS + 4*bank,SELF,pciDramBase); + if(pciDramSize == 0) + pciDramSize ++; + GT_REG_WRITE(pci_scs_bank_size[host][bank], pciDramSize-1); } - +#if 0 // FIXME eventually - this is crap /******************************************************************** -* pci0MapMemoryBank2 - Maps PCI0 memory bank 2 for the slave. +* pci0MapInternalRegSpace - Maps the internal registers memory space for the +* slave. * -* Inputs: base and size of PCI0 SCS2 +* Inputs: base of pci0 internal register *********************************************************************/ -void pci0MapMemoryBank2(unsigned int pci0Dram2Base,unsigned int pci0Dram2Size) +void pci0MapInternalRegSpace(unsigned int pci0InternalBase) { - pci0Dram2Base = pci0Dram2Base & 0xfffff000; - pci0Dram2Base = pci0Dram2Base | (pci0ReadConfigReg( - PCI_SCS_2_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_SCS_2_BASE_ADDRESS,SELF,pci0Dram2Base); - if(pci0Dram2Size == 0) - pci0Dram2Size++; - GT_REG_WRITE(PCI_0SCS_2_BANK_SIZE , pci0Dram2Size-1); + pci0InternalBase = pci0InternalBase & 0xfffff000; + pci0InternalBase = pci0InternalBase | (pciReadConfigReg(0, + PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0x00000fff); + pciWriteConfigReg(0,PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF, + pci0InternalBase); } /******************************************************************** -* pci0MapMemoryBank3 - Maps PCI0 memory bank 3 for the slave. +* pci1MapInternalRegSpace - Maps the internal registers memory space for the +* slave. * -* Inputs: base and size of PCI0 SCS3 +* Inputs: base of pci1 internal register *********************************************************************/ -void pci0MapMemoryBank3(unsigned int pci0Dram3Base,unsigned int pci0Dram3Size) +void pci1MapInternalRegSpace(unsigned int pci1InternalBase) { - pci0Dram3Base = pci0Dram3Base & 0xfffff000; - pci0Dram3Base = pci0Dram3Base | (pci0ReadConfigReg( - PCI_SCS_3_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_SCS_3_BASE_ADDRESS,SELF,pci0Dram3Base); - if(pci0Dram3Size == 0) - pci0Dram3Size++; - GT_REG_WRITE(PCI_0SCS_3_BANK_SIZE , pci0Dram3Size-1); + pci1InternalBase = pci1InternalBase & 0xfffff000; + pci1InternalBase = pci1InternalBase | (pciReadConfigReg(1, + PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF) & 0x00000fff); + pciWriteConfigReg(1,PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,SELF, + pci1InternalBase); } /******************************************************************** -* pci1MapMemoryBank2 - Maps PCI1 memory bank 2 for the slave. +* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the +* slave. * -* Inputs: base and size of PCI1 SCS2 +* Inputs: base of pci0 internal io register *********************************************************************/ -void pci1MapMemoryBank2(unsigned int pci1Dram2Base,unsigned int pci1Dram2Size) +void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase) { - pci1Dram2Base = pci1Dram2Base & 0xfffff000; - pci1Dram2Base = pci1Dram2Base | (pci1ReadConfigReg( - PCI_SCS_2_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_SCS_2_BASE_ADDRESS,SELF,pci1Dram2Base); - if(pci1Dram2Size == 0) - pci1Dram2Size++; - GT_REG_WRITE(PCI_1SCS_2_BANK_SIZE , pci1Dram2Size-1); + pci0InternalBase = pci0InternalBase & 0xfffff000; + pci0InternalBase = pci0InternalBase | (pciReadConfigReg(0, + PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0x00000fff); + pciWriteConfigReg(0,PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF, + pci0InternalBase); } /******************************************************************** -* pci1MapMemoryBank3 - Maps PCI1 memory bank 3 for the slave. -* -* Inputs: base and size of PCI1 SCS3 +* pci1MapInternalRegIOSpace - Maps the internal registers IO space for the +* slave. +* Inputs: base of pci1 internal io register *********************************************************************/ -void pci1MapMemoryBank3(unsigned int pci1Dram3Base,unsigned int pci1Dram3Size) +void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase) { - pci1Dram3Base = pci1Dram3Base & 0xfffff000; - pci1Dram3Base = pci1Dram3Base | (pci1ReadConfigReg( - PCI_SCS_3_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_SCS_3_BASE_ADDRESS,SELF,pci1Dram3Base); - if(pci1Dram3Size == 0) - pci1Dram3Size++; - GT_REG_WRITE(PCI_1SCS_3_BANK_SIZE , pci1Dram3Size-1); + pci1InternalBase = pci1InternalBase & 0xfffff000; + pci1InternalBase = pci1InternalBase | (pciReadConfigReg(1, + PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF) & 0x00000fff); + pciWriteConfigReg(1,PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,SELF, + pci1InternalBase); } /******************************************************************** @@ -1855,9 +851,9 @@ void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, unsigned int pci0Dev0Length) { pci0Dev0Base = pci0Dev0Base & 0xfffff000; - pci0Dev0Base = pci0Dev0Base | (pci0ReadConfigReg( + pci0Dev0Base = pci0Dev0Base | (pciReadConfigReg(0, PCI_CS_0_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_CS_0_BASE_ADDRESS,SELF,pci0Dev0Base ); + pciWriteConfigReg(0,PCI_CS_0_BASE_ADDRESS,SELF,pci0Dev0Base ); if(pci0Dev0Length == 0) pci0Dev0Length++; GT_REG_WRITE(PCI_0CS_0_BANK_SIZE,pci0Dev0Length-1); @@ -1872,9 +868,9 @@ void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, unsigned int pci0Dev1Length) { pci0Dev1Base = pci0Dev1Base & 0xfffff000; - pci0Dev1Base = pci0Dev1Base | (pci0ReadConfigReg( + pci0Dev1Base = pci0Dev1Base | (pciReadConfigReg(0, PCI_CS_1_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_CS_1_BASE_ADDRESS,SELF,pci0Dev1Base ); + pciWriteConfigReg(0,PCI_CS_1_BASE_ADDRESS,SELF,pci0Dev1Base ); if(pci0Dev1Length == 0) pci0Dev1Length++; GT_REG_WRITE(PCI_0CS_1_BANK_SIZE,pci0Dev1Length-1); @@ -1889,9 +885,9 @@ void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, unsigned int pci0Dev2Length) { pci0Dev2Base = pci0Dev2Base & 0xfffff000; - pci0Dev2Base = pci0Dev2Base | (pci0ReadConfigReg( + pci0Dev2Base = pci0Dev2Base | (pciReadConfigReg(0, PCI_CS_2_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_CS_2_BASE_ADDRESS,SELF,pci0Dev2Base ); + pciWriteConfigReg(0,PCI_CS_2_BASE_ADDRESS,SELF,pci0Dev2Base ); if(pci0Dev2Length == 0) pci0Dev2Length++; GT_REG_WRITE(PCI_0CS_2_BANK_SIZE,pci0Dev2Length-1); @@ -1906,9 +902,9 @@ void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, unsigned int pci1Dev0Length) { pci1Dev0Base = pci1Dev0Base & 0xfffff000; - pci1Dev0Base = pci1Dev0Base | (pci1ReadConfigReg( + pci1Dev0Base = pci1Dev0Base | (pciReadConfigReg(1, PCI_CS_0_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_CS_0_BASE_ADDRESS,SELF,pci1Dev0Base ); + pciWriteConfigReg(1,PCI_CS_0_BASE_ADDRESS,SELF,pci1Dev0Base ); if(pci1Dev0Length == 0) pci1Dev0Length++; GT_REG_WRITE(PCI_1CS_0_BANK_SIZE,pci1Dev0Length-1); @@ -1923,9 +919,9 @@ void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, unsigned int pci1Dev1Length) { pci1Dev1Base = pci1Dev1Base & 0xfffff000; - pci1Dev1Base = pci1Dev1Base | (pci1ReadConfigReg( + pci1Dev1Base = pci1Dev1Base | (pciReadConfigReg(1, PCI_CS_1_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_CS_1_BASE_ADDRESS,SELF,pci1Dev1Base); + pciWriteConfigReg(1,PCI_CS_1_BASE_ADDRESS,SELF,pci1Dev1Base); if(pci1Dev1Length == 0) pci1Dev1Length++; GT_REG_WRITE(PCI_1CS_1_BANK_SIZE,pci1Dev1Length-1); @@ -1940,9 +936,9 @@ void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, unsigned int pci1Dev2Length) { pci1Dev2Base = pci1Dev2Base & 0xfffff000; - pci1Dev2Base = pci1Dev2Base | (pci1ReadConfigReg( + pci1Dev2Base = pci1Dev2Base | (pciReadConfigReg(1, PCI_CS_2_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_CS_2_BASE_ADDRESS,SELF,pci1Dev2Base); + pciWriteConfigReg(1,PCI_CS_2_BASE_ADDRESS,SELF,pci1Dev2Base); if(pci1Dev2Length == 0) pci1Dev2Length++; GT_REG_WRITE(PCI_1CS_2_BANK_SIZE,pci1Dev2Length-1); @@ -1957,9 +953,9 @@ void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, unsigned int pci0Dev3Length) { pci0Dev3Base = pci0Dev3Base & 0xfffff000; - pci0Dev3Base = pci0Dev3Base | (pci0ReadConfigReg( + pci0Dev3Base = pci0Dev3Base | (pciReadConfigReg(0, PCI_CS_3_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_CS_3_BASE_ADDRESS,SELF,pci0Dev3Base ); + pciWriteConfigReg(0,PCI_CS_3_BASE_ADDRESS,SELF,pci0Dev3Base ); if(pci0Dev3Length == 0) pci0Dev3Length++; GT_REG_WRITE(PCI_0CS_3_BANK_SIZE , pci0Dev3Length-1); @@ -1974,9 +970,9 @@ void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, unsigned int pci0DevBootLength) { pci0DevBootBase = pci0DevBootBase & 0xfffff000; - pci0DevBootBase = pci0DevBootBase | (pci0ReadConfigReg( + pci0DevBootBase = pci0DevBootBase | (pciReadConfigReg(0, PCI_BOOTCS_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_BOOTCS_BASE_ADDRESS,SELF,pci0DevBootBase ); + pciWriteConfigReg(0,PCI_BOOTCS_BASE_ADDRESS,SELF,pci0DevBootBase ); if(pci0DevBootLength == 0) pci0DevBootLength++; GT_REG_WRITE(PCI_0CS_BOOT_BANK_SIZE , pci0DevBootLength-1); @@ -1991,9 +987,9 @@ void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, unsigned int pci1Dev3Length) { pci1Dev3Base = pci1Dev3Base & 0xfffff000; - pci1Dev3Base = pci1Dev3Base | (pci1ReadConfigReg( + pci1Dev3Base = pci1Dev3Base | (pciReadConfigReg(1, PCI_CS_3_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_CS_3_BASE_ADDRESS,SELF,pci1Dev3Base ); + pciWriteConfigReg(1,PCI_CS_3_BASE_ADDRESS,SELF,pci1Dev3Base ); if(pci1Dev3Length == 0) pci1Dev3Length++; GT_REG_WRITE(PCI_1CS_3_BANK_SIZE , pci1Dev3Length-1); @@ -2008,9 +1004,9 @@ void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, unsigned int pci1DevBootLength) { pci1DevBootBase = pci1DevBootBase & 0xfffff000; - pci1DevBootBase = pci1DevBootBase | (pci1ReadConfigReg( + pci1DevBootBase = pci1DevBootBase | (pciReadConfigReg(1, PCI_BOOTCS_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_BOOTCS_BASE_ADDRESS,SELF,pci1DevBootBase ); + pciWriteConfigReg(1,PCI_BOOTCS_BASE_ADDRESS,SELF,pci1DevBootBase ); if(pci1DevBootLength == 0) pci1DevBootLength++; GT_REG_WRITE(PCI_1CS_BOOT_BANK_SIZE , pci1DevBootLength-1); @@ -2026,9 +1022,9 @@ void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, { pci0P2pMem0Base = pci0P2pMem0Base & 0xfffff000; - pci0P2pMem0Base = pci0P2pMem0Base | (pci0ReadConfigReg( + pci0P2pMem0Base = pci0P2pMem0Base | (pciReadConfigReg(0, PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_P2P_MEM0_BASE_ADDRESS,SELF,pci0P2pMem0Base); + pciWriteConfigReg(0,PCI_P2P_MEM0_BASE_ADDRESS,SELF,pci0P2pMem0Base); if(pci0P2pMem0Length == 0) pci0P2pMem0Length++; GT_REG_WRITE(PCI_0P2P_MEM0_BAR_SIZE , pci0P2pMem0Length-1); @@ -2043,9 +1039,9 @@ void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, unsigned int pci1P2pMem0Length) { pci1P2pMem0Base = pci1P2pMem0Base & 0xfffff000; - pci1P2pMem0Base = pci1P2pMem0Base | (pci1ReadConfigReg( + pci1P2pMem0Base = pci1P2pMem0Base | (pciReadConfigReg(1, PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_P2P_MEM0_BASE_ADDRESS,SELF,pci1P2pMem0Base); + pciWriteConfigReg(1,PCI_P2P_MEM0_BASE_ADDRESS,SELF,pci1P2pMem0Base); if(pci1P2pMem0Length == 0) pci1P2pMem0Length++; GT_REG_WRITE(PCI_1P2P_MEM0_BAR_SIZE , pci1P2pMem0Length-1); @@ -2060,9 +1056,9 @@ void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, unsigned int pci0P2pMem1Length) { pci0P2pMem1Base = pci0P2pMem1Base & 0xfffff000; - pci0P2pMem1Base = pci0P2pMem1Base | (pci0ReadConfigReg( + pci0P2pMem1Base = pci0P2pMem1Base | (pciReadConfigReg(0, PCI_P2P_MEM1_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_P2P_MEM1_BASE_ADDRESS,SELF,pci0P2pMem1Base ); + pciWriteConfigReg(0,PCI_P2P_MEM1_BASE_ADDRESS,SELF,pci0P2pMem1Base ); if(pci0P2pMem1Length == 0) pci0P2pMem1Length++; GT_REG_WRITE(PCI_0P2P_MEM1_BAR_SIZE , pci0P2pMem1Length-1); @@ -2077,9 +1073,9 @@ void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, unsigned int pci1P2pMem1Length) { pci1P2pMem1Base = pci1P2pMem1Base & 0xfffff000; - pci1P2pMem1Base = pci1P2pMem1Base | (pci1ReadConfigReg( + pci1P2pMem1Base = pci1P2pMem1Base | (pciReadConfigReg(1, PCI_P2P_MEM1_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_P2P_MEM1_BASE_ADDRESS,SELF,pci1P2pMem1Base ); + pciWriteConfigReg(1,PCI_P2P_MEM1_BASE_ADDRESS,SELF,pci1P2pMem1Base ); if(pci1P2pMem1Length == 0) pci1P2pMem1Length++; GT_REG_WRITE(PCI_1P2P_MEM1_BAR_SIZE , pci1P2pMem1Length-1); @@ -2094,9 +1090,9 @@ void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, unsigned int pci0P2pIoLength) { pci0P2pIoBase = pci0P2pIoBase & 0xfffff000; - pci0P2pIoBase = pci0P2pIoBase | (pci0ReadConfigReg( + pci0P2pIoBase = pci0P2pIoBase | (pciReadConfigReg(0, PCI_P2P_MEM0_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_P2P_I_O_BASE_ADDRESS,SELF,pci0P2pIoBase ); + pciWriteConfigReg(0,PCI_P2P_I_O_BASE_ADDRESS,SELF,pci0P2pIoBase ); if(pci0P2pIoLength == 0) pci0P2pIoLength++; GT_REG_WRITE(PCI_0P2P_I_O_BAR_SIZE , pci0P2pIoLength-1); @@ -2111,9 +1107,9 @@ void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, unsigned int pci1P2pIoLength) { pci1P2pIoBase = pci1P2pIoBase & 0xfffff000; - pci1P2pIoBase = pci1P2pIoBase | (pci1ReadConfigReg( + pci1P2pIoBase = pci1P2pIoBase | (pciReadConfigReg(1, PCI_P2P_I_O_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_P2P_I_O_BASE_ADDRESS,SELF,pci1P2pIoBase); + pciWriteConfigReg(1,PCI_P2P_I_O_BASE_ADDRESS,SELF,pci1P2pIoBase); if(pci1P2pIoLength == 0) pci1P2pIoLength++; GT_REG_WRITE(PCI_1P2P_I_O_BAR_SIZE , pci1P2pIoLength-1); @@ -2127,9 +1123,9 @@ void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, unsigned int pci1P2pIoLength) void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs) { pci0CpuBase = pci0CpuBase & 0xfffff000; - pci0CpuBase = pci0CpuBase | (pci0ReadConfigReg( + pci0CpuBase = pci0CpuBase | (pciReadConfigReg(0, PCI_CPU_BASE_ADDRESS,SELF) & 0x00000fff); - pci0WriteConfigReg(PCI_CPU_BASE_ADDRESS,SELF,pci0CpuBase ); + pciWriteConfigReg(0,PCI_CPU_BASE_ADDRESS,SELF,pci0CpuBase ); if(pci0CpuLengs == 0) pci0CpuLengs++; GT_REG_WRITE(PCI_0CPU_BAR_SIZE , pci0CpuLengs-1); @@ -2143,17 +1139,18 @@ void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs) void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs) { pci1CpuBase = pci1CpuBase & 0xfffff000; - pci1CpuBase = pci1CpuBase | (pci1ReadConfigReg( + pci1CpuBase = pci1CpuBase | (pciReadConfigReg(1, PCI_CPU_BASE_ADDRESS,SELF) & 0x00000fff); - pci1WriteConfigReg(PCI_CPU_BASE_ADDRESS,SELF,pci1CpuBase ); + pciWriteConfigReg(1,PCI_CPU_BASE_ADDRESS,SELF,pci1CpuBase ); if(pci1CpuLengs == 0) pci1CpuLengs++; GT_REG_WRITE(PCI_1CPU_BAR_SIZE , pci1CpuLengs-1); } +#endif /******************************************************************** -* pci0SetRegionFeatures - This function modifys one of the 8 regions with +* pciSetRegionFeatures - This function modifys one of the 8 regions with * feature bits given as an input. * - Be advised to check the spec before modifying them. * Inputs: PCI_PROTECT_REGION region - one of the eight regions. @@ -2163,7 +1160,7 @@ void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs) * unsigned int topAddress - The region top Address. * Returns: false if one of the parameters is erroneous true otherwise. *********************************************************************/ -bool pci0SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, +bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,unsigned int features, unsigned int baseAddress,unsigned int regionLength) { unsigned int accessLow; @@ -2172,7 +1169,7 @@ bool pci0SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, if(regionLength == 0) /* close the region. */ { - pci0DisableAccessRegion(region); + pciDisableAccessRegion(host, region); return true; } /* base Address is store is bits [11:0] */ @@ -2181,152 +1178,61 @@ bool pci0SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, the safe side we disable bits: [11:0] */ accessLow = accessLow | (features & 0xfffff000); /* write to the Low Access Region register */ - GT_REG_WRITE(PCI_0ACCESS_CONTROL_BASE_0_LOW + 0x10*region,accessLow); - accessHigh = (accessTop & 0xfff00000) >> 20; - if(regionLength != 0) - { - /* write to the High Access Region register */ - GT_REG_WRITE(PCI_0ACCESS_CONTROL_TOP_0 + 0x10*region,accessHigh - 1); - } - else - { - GT_REG_WRITE(PCI_0ACCESS_CONTROL_TOP_0 + 0x10*region,0); - } - return true; -} - -/******************************************************************** -* pci1SetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pci1SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, - unsigned int baseAddress,unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; + GT_REG_WRITE( pci_access_control_base_0_low[host] + 0x10*region,accessLow); - if(regionLength == 0) /* close the region. */ - { - pci1DisableAccessRegion(region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE(PCI_1ACCESS_CONTROL_BASE_0_LOW + 0x10*region,accessLow); accessHigh = (accessTop & 0xfff00000) >> 20; - if(regionLength != 0) - { - /* write to the High Access Region register */ - GT_REG_WRITE(PCI_1ACCESS_CONTROL_TOP_0 + 0x10*region,accessHigh - 1); - } - else - { - GT_REG_WRITE(PCI_1ACCESS_CONTROL_TOP_0 + 0x10*region,0); - } - return true; -} -/******************************************************************** -* pci0DisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pci0DisableAccessRegion(PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE(PCI_0ACCESS_CONTROL_BASE_0_LOW + 0x10*region,0x01001fff); - GT_REG_WRITE(PCI_0ACCESS_CONTROL_TOP_0 + 0x10*region,0); + /* write to the High Access Region register */ + GT_REG_WRITE(pci_access_control_top_0[host] + 0x10*region,accessHigh - 1); + return true; } /******************************************************************** -* pci1DisableAccessRegion - Disable The given Region by writing MAX size +* pciDisableAccessRegion - Disable The given Region by writing MAX size * to its low Address and MIN size to its high Address. * * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. * Returns: N/A. *********************************************************************/ -void pci1DisableAccessRegion(PCI_ACCESS_REGIONS region) +void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region) { /* writing back the registers default values. */ - GT_REG_WRITE(PCI_1ACCESS_CONTROL_BASE_0_LOW + 0x10*region,0x01001fff); - GT_REG_WRITE(PCI_1ACCESS_CONTROL_TOP_0 + 0x10*region,0); -} - -/******************************************************************** -* pci0ArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pci0ArbiterEnable() -{ - unsigned int regData; - - GT_REG_READ(PCI_0ARBITER_CONTROL,®Data); - GT_REG_WRITE(PCI_0ARBITER_CONTROL,regData | BIT31); - return true; + GT_REG_WRITE(pci_access_control_base_0_low[host] + 0x10*region,0x01001fff); + GT_REG_WRITE(pci_access_control_top_0[host] + 0x10*region,0); } /******************************************************************** -* pci1ArbiterEnable - Enables PCI-1`s Arbitration mechanism. +* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. * * Inputs: N/A * Returns: true. *********************************************************************/ -bool pci1ArbiterEnable() +bool pciArbiterEnable(PCI_HOST host) { unsigned int regData; - GT_REG_READ(PCI_1ARBITER_CONTROL,®Data); - GT_REG_WRITE(PCI_1ARBITER_CONTROL,regData | BIT31); + GT_REG_READ(pci_arbiter_control[host],®Data); + GT_REG_WRITE(pci_arbiter_control[host],regData | BIT31); return true; } /******************************************************************** -* pci0ArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pci0ArbiterDisable() -{ - unsigned int regData; - - GT_REG_READ(PCI_0ARBITER_CONTROL,®Data); - GT_REG_WRITE(PCI_0ARBITER_CONTROL,regData & 0x7fffffff); - return true; -} -/******************************************************************** -* pci1ArbiterDisable - Disable PCI-1`s Arbitration mechanism. +* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. * * Inputs: N/A * Returns: true *********************************************************************/ -bool pci1ArbiterDisable() +bool pciArbiterDisable(PCI_HOST host) { unsigned int regData; - GT_REG_READ(PCI_1ARBITER_CONTROL,®Data); - GT_REG_WRITE(PCI_1ARBITER_CONTROL,regData & 0x7fffffff); + GT_REG_READ(pci_arbiter_control[host],®Data); + GT_REG_WRITE(pci_arbiter_control[host],regData & 0x7fffffff); return true; } /******************************************************************** -* pci0SetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) +* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) * * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. @@ -2337,7 +1243,7 @@ bool pci1ArbiterDisable() * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. * Returns: true *********************************************************************/ -bool pci0SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent, +bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, PCI_AGENT_PRIO externalAgent0, PCI_AGENT_PRIO externalAgent1, PCI_AGENT_PRIO externalAgent2, @@ -2348,88 +1254,18 @@ bool pci0SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent, unsigned int regData; unsigned int writeData; - GT_REG_READ(PCI_0ARBITER_CONTROL,®Data); + GT_REG_READ(pci_arbiter_control[host],®Data); writeData = (internalAgent << 7) + (externalAgent0 << 8) + (externalAgent1 << 9) + (externalAgent2 << 10) + (externalAgent3 << 11) + (externalAgent4 << 12) + (externalAgent5 << 13); - regData = (regData & 0xffffc07f) + writeData; - GT_REG_WRITE(PCI_0ARBITER_CONTROL,regData & regData); - return true; -} - -/******************************************************************** -* pci1SetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pci1SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ(PCI_1ARBITER_CONTROL,®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + \ - (externalAgent1 << 9) + (externalAgent2 << 10) + \ - (externalAgent3 << 11) + (externalAgent4 << 12) + \ - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) + writeData; - GT_REG_WRITE(PCI_1ARBITER_CONTROL,regData & regData); - return true; -} - -/******************************************************************** -* pci0ParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pci0ParkingDisable(PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ(PCI_0ARBITER_CONTROL,®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + \ - (externalAgent1 << 16) + (externalAgent2 << 17) + \ - (externalAgent3 << 18) + (externalAgent4 << 19) + \ - (externalAgent5 << 20); - regData = (regData & 0xffffc07f) + writeData; - regData = (regData & 0xffe03fff) + writeData; - GT_REG_WRITE(PCI_0ARBITER_CONTROL,regData & regData); + regData = (regData & 0xffffc07f) | writeData; + GT_REG_WRITE(pci_arbiter_control[host],regData & regData); return true; } /******************************************************************** -* pci1ParkingDisable - Park on last option disable, with this function you can +* pciParkingDisable - Park on last option disable, with this function you can * disable the park on last mechanism for each agent. * disabling this option for all agents results parking * on the internal master. @@ -2443,7 +1279,7 @@ bool pci0ParkingDisable(PCI_AGENT_PARK internalAgent, * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. * Returns: true *********************************************************************/ -bool pci1ParkingDisable(PCI_AGENT_PARK internalAgent, +bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, PCI_AGENT_PARK externalAgent0, PCI_AGENT_PARK externalAgent1, PCI_AGENT_PARK externalAgent2, @@ -2454,42 +1290,18 @@ bool pci1ParkingDisable(PCI_AGENT_PARK internalAgent, unsigned int regData; unsigned int writeData; - GT_REG_READ(PCI_1ARBITER_CONTROL,®Data); + GT_REG_READ(pci_arbiter_control[host],®Data); writeData = (internalAgent << 14) + (externalAgent0 << 15) + \ (externalAgent1 << 16) + (externalAgent2 << 17) + \ (externalAgent3 << 18) + (externalAgent4 << 19) + \ (externalAgent5 << 20); - regData = (regData & 0xffffc07f) + writeData; - regData = (regData & 0xffe03fff) + writeData; - GT_REG_WRITE(PCI_1ARBITER_CONTROL,regData & regData); - return true; -} - -/******************************************************************** -* pci0EnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pci0EnableBrokenAgentDetection(unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ(PCI_0ARBITER_CONTROL,®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE(PCI_0ARBITER_CONTROL,regData | BIT1); + regData = (regData & ~(0x7f<<14)) | writeData; + GT_REG_WRITE(pci_arbiter_control[host],regData); return true; } /******************************************************************** -* pci1EnableBrokenAgentDetection - A master is said to be broken if it fails to +* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to * respond to grant assertion within a window specified in * the input value: 'brokenValue'. * @@ -2497,7 +1309,7 @@ bool pci0EnableBrokenAgentDetection(unsigned char brokenValue) * grant without asserting frame. * Returns: Error for illegal broken value otherwise true. *********************************************************************/ -bool pci1EnableBrokenAgentDetection(unsigned char brokenValue) +bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue) { unsigned int data; unsigned int regData; @@ -2505,14 +1317,14 @@ bool pci1EnableBrokenAgentDetection(unsigned char brokenValue) if (brokenValue > 0xf) return false; /* brokenValue must be 4 bit */ data = brokenValue << 3; - GT_REG_READ(PCI_1ARBITER_CONTROL,®Data); + GT_REG_READ(pci_arbiter_control[host],®Data); regData = (regData & 0xffffff87) | data; - GT_REG_WRITE(PCI_1ARBITER_CONTROL,regData | BIT1); + GT_REG_WRITE(pci_arbiter_control[host],regData | BIT1); return true; } /******************************************************************** -* pci0DisableBrokenAgentDetection - This function disable the Broken agent +* pciDisableBrokenAgentDetection - This function disable the Broken agent * Detection mechanism. * NOTE: This operation may cause a dead lock on the * pci0 arbitration. @@ -2520,37 +1332,18 @@ bool pci1EnableBrokenAgentDetection(unsigned char brokenValue) * Inputs: N/A * Returns: true. *********************************************************************/ -bool pci0DisableBrokenAgentDetection() -{ - unsigned int regData; - - GT_REG_READ(PCI_0ARBITER_CONTROL,®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE(PCI_0ARBITER_CONTROL,regData); - return true; -} - -/******************************************************************** -* disablePci1BrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci1 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pci1DisableBrokenAgentDetection() +bool pciDisableBrokenAgentDetection(PCI_HOST host) { unsigned int regData; - GT_REG_READ(PCI_1ARBITER_CONTROL,®Data); + GT_REG_READ(pci_arbiter_control[host],®Data); regData = regData & 0xfffffffd; - GT_REG_WRITE(PCI_1ARBITER_CONTROL,regData); + GT_REG_WRITE(pci_arbiter_control[host],regData); return true; } /******************************************************************** -* pci0P2PConfig - This function set the PCI_0 P2P configurate. +* pciP2PConfig - This function set the PCI_n P2P configurate. * For more information on the P2P read PCI spec. * * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower @@ -2563,45 +1356,21 @@ bool pci1DisableBrokenAgentDetection() * * Returns: true. *********************************************************************/ -bool pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE(PCI_0P2P_CONFIGURATION,regData); - return true; -} - -/******************************************************************** -* pci1P2PConfig - This function set the PCI_1 P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum) +bool pciP2PConfig(PCI_HOST host, unsigned int SecondBusLow, + unsigned int SecondBusHigh, + unsigned int busNum,unsigned int devNum) { unsigned int regData; regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE(PCI_1P2P_CONFIGURATION,regData); + GT_REG_WRITE(pci_p2p_configuration[host],regData); return true; } /******************************************************************** -* pci0SetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_0 interface. +* pciSetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency in the PCI_n interface. * Inputs: region - One of the four regions. * snoopType - There is four optional Types: * 1. No Snoop. @@ -2612,7 +1381,7 @@ bool pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, * regionLength - Region length. * Returns: false if one of the parameters is wrong otherwise return true. *********************************************************************/ -bool pci0SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, +bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, unsigned int baseAddress, unsigned int regionLength) { @@ -2623,8 +1392,8 @@ bool pci0SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, if( (region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB) ) return false; - snoopXbaseAddress = PCI_0SNOOP_CONTROL_BASE_0_LOW + 0x10 * region; - snoopXtopAddress = PCI_0SNOOP_CONTROL_TOP_0 + 0x10 * region; + snoopXbaseAddress = pci_snoop_control_base_0_low[host] + 0x10 * region; + snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; if(regionLength == 0) /* closing the region */ { GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); @@ -2639,42 +1408,160 @@ bool pci0SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, return true; } -/******************************************************************** -* pci1SetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_1 interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pci1SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) +PCI_DEVICE * +pciFindDevice(unsigned short vendorID, unsigned short deviceID) { - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; + int host; + PCI_DEVICE *dev; + for(host=PCI_HOST0;host<=PCI_HOST1;host++) { + for(dev=pci_dev_list[host];dev->deviceNum!=-1;dev++) { + if(vendorID==dev->venID && deviceID==dev->deviceID) return dev; + } + } + return NULL; +} - if( (region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB) ) - return false; - snoopXbaseAddress = PCI_1SNOOP_CONTROL_BASE_0_LOW + 0x10 * region; - snoopXtopAddress = PCI_1SNOOP_CONTROL_TOP_0 + 0x10 * region; - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); - GT_REG_WRITE(snoopXtopAddress,0); - return true; +static const char * const pci_type_legend[]= + {"32 bit","below 1M","64 bit", "reserved"}; + +static const char * const pci_timing_legend[]= + {"Slow","Medium","Fast","???"}; + +static int pci_alloc_bar(PCI_DEVICE *dev, int index) +{ + PCI_BAR *bar=&dev->bar[index]; + unsigned int *alloc, reg=BAR0+index*4; + + if(!bar) { + printf("error, no bar\n"); + return -1; + } + + if (bar->type & BAR_SEL_MEM_IO) { + alloc=&pci_io_bar_alloc[dev->host]; + } else { + alloc=&pci_mem_bar_alloc[dev->host]; + } + + bar->base=((*alloc)+bar->size-1)&~(bar->size-1); + pciWriteConfigReg(dev->host, reg, dev->deviceNum, bar->base); + bar->base=pciReadConfigReg(dev->host, reg, dev->deviceNum)&(~1); + *alloc=bar->base+bar->size; + + return 0; +} + +#ifdef DEBUG +static char * smart_print(unsigned val, char *buf) +{ + char *unit="b"; + + if(val>_1G) val/=_1G, unit="G"; + else if(val>_1M) val/=_1M, unit="M"; + else if(val>1024) val/=1024, unit="k"; + + sprintf(buf, "%3d%s", val, unit); + return buf; +} +#endif + +static void setup_pci_devices(PCI_DEVICE *list) +{ + PCI_DEVICE *dev; + int i,irq_pin; + int command=0; + + for(dev=list;dev->deviceNum!=-1;dev++) { + int statcmd = pciReadConfigReg(dev->host,PCI_STATUS_AND_COMMAND, + dev->deviceNum); + + printf("%2d: %04x %04x (%s)\n", dev->deviceNum, dev->venID, + dev->deviceID, dev->type); + + /* latency=64, cache linesize (in words), clear bist */ + pciWriteConfigReg(dev->host, + PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE, + dev->deviceNum, (0x04 << 8) | (CACHE_LINE_SIZE / 4)); + + command = 0; + if(dev->deviceNum!=0) { + statcmd &= ~(MASTER_ENABLE | MEMORY_ENABLE | I_O_ENABLE); + /* disable this device */ + pciWriteConfigReg(dev->host,PCI_STATUS_AND_COMMAND,dev->deviceNum, + statcmd); + + } + + irq_pin=pciReadConfigReg(dev->host,PCI_INTERRUPT_PIN_AND_LINE, dev->deviceNum); + if(((irq_pin>>8)&0xff)==1) { /* only allow INT A */ + unsigned char irq=pci_irq_swizzle[dev->host][dev->deviceNum]; + if(irq) { + irq_pin&=~0xff; + irq_pin|=(irq|64); + printf(" IRQ %d\n", irq); + pciWriteConfigReg(dev->host,PCI_INTERRUPT_PIN_AND_LINE, dev->deviceNum, irq_pin); + } + } + + /* for each BAR */ + for(i=0;i<5;i++) { + if(dev->bar[i].size) { + if(dev->deviceNum!=0) { + command |= MASTER_ENABLE; + + if(dev->bar[i].type & BAR_SEL_MEM_IO) command |= I_O_ENABLE; + else command |= MEMORY_ENABLE; + + pci_alloc_bar(dev, i); + } +#ifdef DEBUG + { + char buf[10]; + printf(" BAR %d: %08x %s %s, %s%s\n",i, + dev->bar[i].base, + smart_print(dev->bar[i].size, buf), + dev->bar[i].type & BAR_SEL_MEM_IO ?"I/O":"MEM", + pci_type_legend[(dev->bar[i].type&BAR_MEM_TYPE_MASK)>>1], + dev->bar[i].type & BAR_PREFETCHABLE ?", prefetchable":"" + ); + } +#endif + } + } + + if(command) { + pciWriteConfigReg(dev->host,PCI_STATUS_AND_COMMAND,dev->deviceNum, + command | statcmd); + statcmd = pciReadConfigReg(dev->host,PCI_STATUS_AND_COMMAND, + dev->deviceNum); + } + + printf(" %s%s%s%s%dMHz, %s%s timing\n", + statcmd & (1<<0)?"I/O, ":"", + statcmd & (1<<1)?"MEM, ":"", + statcmd & (1<<2)?"Master, ":"", + statcmd & (1<<20)?"Capability list, ":"", + statcmd & (1<<21)?66:33, + statcmd & (1<<23)?"Fast back to back capable, ":"", + pci_timing_legend[(statcmd>>25)&3]); + } +} + +void +pci_init(bd_t *bd) +{ + PCI_HOST host; + + printf("PCI scan...\n"); + for(host=PCI_HOST0; host<=PCI_HOST1; host++) { + pciArbiterEnable(host); + + pciParkingDisable(host,1,1,1,1,1,1,1); + memset(pci_dev_list[host],0,sizeof(pci_dev_list[host])); + printf("PCI %d:\n",host); + pciScanDevices(host,pci_dev_list[host],32); + setup_pci_devices(pci_dev_list[host]); + + PCI_MEMORY_ENABLE(host, SELF); } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE(snoopXbaseAddress,data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); - return true; } diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index 7160126..0cf1860 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -51,6 +51,11 @@ memory_map_bank(unsigned int bankNo, unsigned int bankBase, unsigned int bankLength) { +#ifdef MAP_PCI + PCI_HOST host; +#endif + + #ifdef DEBUG if (bankLength > 0) { printf("\nmapping bank %d at %08x - %08x", @@ -60,45 +65,31 @@ memory_map_bank(unsigned int bankNo, } #endif - switch(bankNo) { - case 0: - memoryMapBank0(bankBase, bankLength); -#ifdef MAP_PCI - pci0MapMemoryBank0(bankBase, bankLength); - pci1MapMemoryBank0(bankBase, bankLength); -#endif - return(true); - break; - case 1: - memoryMapBank1(bankBase, bankLength); -#ifdef MAP_PCI - pci0MapMemoryBank1(bankBase, bankLength); - pci1MapMemoryBank1(bankBase, bankLength); -#endif - return(true); - break; - case 2: - memoryMapBank2(bankBase, bankLength); -#ifdef MAP_PCI - pci0MapMemoryBank2(bankBase, bankLength); - pci1MapMemoryBank2(bankBase, bankLength); -#endif - return(true); - break; - case 3: - memoryMapBank3(bankBase, bankLength); + memoryMapBank(bankNo, bankBase, bankLength); + #ifdef MAP_PCI - pci0MapMemoryBank3(bankBase, bankLength); - pci1MapMemoryBank3(bankBase, bankLength); + for (host=PCI_HOST0;host<=PCI_HOST1;host++) { + const int features= + PREFETCH_ENABLE | + DELAYED_READ_ENABLE | + AGGRESSIVE_PREFETCH | + READ_LINE_AGGRESSIVE_PREFETCH | + READ_MULTI_AGGRESSIVE_PREFETCH | + MAX_BURST_4 | + PCI_NO_SWAP; + + pciMapMemoryBank(host, bankNo, bankBase, bankLength); + + pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase, + bankLength); + + pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength); + } #endif - return(true); - break; - default: - return(0); - } + return 0; } -#define GB (1 << 29) +#define GB (1 << 30) /* much of this code is based on (or is) the code in the pip405 port */ /* thanks go to the authors of said port - Josh */ @@ -117,8 +108,7 @@ typedef struct sdram_info { * translate ns.ns/10 coding of SPD timing values * into 10 ps unit values */ - -static unsigned short +static inline unsigned short NS10to10PS(unsigned char spd_byte) { unsigned short ns, ns10; @@ -135,8 +125,7 @@ NS10to10PS(unsigned char spd_byte) * translate ns coding of SPD timing values * into 10 ps unit values */ - -static unsigned short +static inline unsigned short NSto10PS(unsigned char spd_byte) { return(spd_byte*100); @@ -145,8 +134,30 @@ NSto10PS(unsigned char spd_byte) /* This code reads the SPD chip on the sdram and populates * the array which is passed in with the relevant information */ static int -check_dimm(uchar addr, uchar slot, sdram_info_t *info) +check_dimm(uchar slot, sdram_info_t *info) { +#ifdef ZUMA_NTL + /* zero all the values */ + memset(info, 0, sizeof(*info)); + + if (!slot) { + info->slot = 0; + info->banks = 1; + info->registered = 0; + info->drb_size = 16; /* 16 - 256MBit, 32 - 512MBit */ + info->tpar = 3; + info->tras_clocks = 5; + info->burst_len = 4; + +#ifdef CONFIG_ECC + /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ + info->ecc = 2; +#endif + } + return 0; + +#else + uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; uchar rows, cols, sdram_banks, supp_cal, width, cal_val; ulong memclk, tmemclk; @@ -251,6 +262,7 @@ check_dimm(uchar addr, uchar slot, sdram_info_t *info) info->slot = slot; return 0; +#endif } /* sets up the GT properly with information passed in */ @@ -316,8 +328,11 @@ setup_sdram(sdram_info_t *info) tmp = (((info->tpar == 3) ? 2 : 1) | (((info->tpar == 3) ? 2 : 1) << 2) | (((info->tpar == 3) ? 2 : 1) << 4) | - (info->tras_clocks << 8) | - (info->ecc << 13)); + (info->tras_clocks << 8)); + + /* Is this right? RGF */ + if (info->ecc == 2) + tmp |= 1<<13; DP(printf("setting up sdram_timing with: %08lx\n", tmp)); GT_REG_WRITE(SDRAM_TIMING, tmp); @@ -368,36 +383,37 @@ setup_sdram(sdram_info_t *info) static long int dram_size(long int *base, long int maxsize) { - volatile long int *addr; - long int cnt, val; - - for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - *addr = 0xDEADBEEF; - - /* check at base address */ - if ((val = *addr) != 0xDEADBEEF) { - return 0; - } - - for (cnt = 1; ; cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - - if (val != (~cnt)) { - return (cnt * sizeof(long)); - } - } - /* NOTREACHED */ - - return 0; + volatile long int *addr, *b=base; + long int cnt, val, save1, save2; + +#define STARTVAL (1<<20) /* start test at 1M */ + for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1=*addr; /* save contents of addr */ + save2=*b; /* save contents of base */ + + *addr=cnt; /* write cnt to addr */ + *b=0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr=save1; /* restore *addr */ + *b=save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + + *addr=save1; + *b=save2; + + if (val != cnt) { + /* fix boundary condition.. STARTVAL means zero */ + if(cnt==STARTVAL/sizeof(long)) cnt=0; + return (cnt * sizeof(long)); + } + } + return maxsize; } /* ------------------------------------------------------------------------- */ @@ -422,10 +438,10 @@ initdram(int board_type) printf("Skipping SDRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm(DIMM0_I2C_ADDR, 0, &dimm1); + s0 = check_dimm(0, &dimm1); /* DIMM1 */ - s1 = check_dimm(DIMM1_I2C_ADDR, 1, &dimm2); + s1 = check_dimm(1, &dimm2); memory_map_bank(0, 0, 0); memory_map_bank(1, 0, 0); @@ -469,14 +485,10 @@ initdram(int board_type) continue; if ((total + check) > CFG_GT_REGS) - check -= CFG_GT_REGS - (total+check); + check = CFG_GT_REGS - total; memory_map_bank(bank_no, total, check); realsize = dram_size((long int *)total, check); - - if (realsize < 10) - realsize = 0; - memory_map_bank(bank_no, total, realsize); total += realsize; @@ -485,6 +497,5 @@ initdram(int board_type) if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) { puts("[ECC] "); } - return(total); } diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index 593b8e1..e6eec84 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -40,7 +40,9 @@ void serial_init (unsigned long dummy, int baudrate) { +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) int clock_divisor = 230400/baudrate; +#endif mpsc_init(baudrate); @@ -57,9 +59,9 @@ void serial_putc(const char c) { if (c == '\n') - mpsc_putchar_early('\r'); + mpsc_putchar('\r'); - mpsc_putchar_early(c); + mpsc_putchar(c); } int diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c new file mode 100644 index 0000000..c9cc5a2 --- /dev/null +++ b/board/evb64260/zuma_pbb.c @@ -0,0 +1,148 @@ +#include +#include +#include +#include "zuma_pbb.h" + +#undef DEBUG + +#define PAT_LO 0x00010203 +#define PAT_HI 0x04050607 + +static PBB_DMA_REG_MAP *zuma_pbb_reg=NULL; + +static char test_buf1[2048]; +static char test_buf2[2048]; + +int zuma_test_dma(int cmd, int size) +{ + static const char *const test_legend[]={ + "write", "verify", + "copy", "compare", + "write inc", "verify inc"}; + register int i,j; + unsigned int p1=((unsigned int)test_buf1+0xff)&(~0xff); + unsigned int p2=((unsigned int)test_buf2+0xff)&(~0xff); + volatile unsigned int *ps=(unsigned int *)p1; + volatile unsigned int *pd=(unsigned int *)p2; + unsigned int funct, pat_lo=PAT_LO, pat_hi=PAT_HI; + DMA_INT_STATUS stat; + int ret=0; + + if(!zuma_pbb_reg) { + printf("not initted\n"); + return -1; + } + + if(cmd<0||cmd>5) { + printf("inv cmd %d\n", cmd); + return -1; + } + + if(cmd==2 || cmd==3) { + /* not implemented */ + return 0; + } + + if(size<=0 || size>1024) size=1024; + + size&=(~7); /* throw away bottom 3 bits */ + + p1=((unsigned int)test_buf1+0xff)&(~0xff); + p2=((unsigned int)test_buf2+0xff)&(~0xff); + + memset((void *)p1,0,size); + memset((void *)p2,0,size); + + for(i=0;iint_mask.pci_bits.chan0=EOF_RX_FLAG|EOF_TX_FLAG|EOB_TX_FLAG; + + zuma_pbb_reg->debug_57=PAT_LO; /* patl */ + zuma_pbb_reg->debug_58=PAT_HI; /* path */ + + zuma_pbb_reg->debug_54=cpu_to_le32(p1); /* src 0x01b0 */ + zuma_pbb_reg->debug_55=cpu_to_le32(p2); /* dst 0x01b8 */ + zuma_pbb_reg->debug_56=cpu_to_le32(funct); /* func, 0x01c0 */ + + // give DMA time to chew on things.. dont use DRAM or PCI + // if you can avoid it. + do { + for(i=0;i<1000*10;i++); + } while(le32_to_cpu(zuma_pbb_reg->debug_56) & (1<<31)); + + stat.word=zuma_pbb_reg->status.word; + zuma_pbb_reg->int_mask.word=0; + + printf("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0); + + printf("func: %08x\n", le32_to_cpu(zuma_pbb_reg->debug_56)); + printf("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2], ps[3]); + printf("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2], pd[3]); + printf("func: %08x\n", le32_to_cpu(zuma_pbb_reg->debug_56)); + + + if(cmd == 0 || cmd == 4) { + /* this is a write */ + if(!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */ + (memcmp((void *)ps,(void *)pd,size)!=0)) { /* cmp error */ + for(i=0;idebug_63), + zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62); + ret = -1; + } + } + + printf("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size, + (ret==0)?"PASSED":"FAILED"); + return 0; +} + +void zuma_init_pbb(void) +{ + PCI_DEVICE *dev=pciFindDevice(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB); + + if(!dev) { + printf("no zuma pbb\n"); + return; + } + + zuma_pbb_reg=(PBB_DMA_REG_MAP *)dev->bar[0].base; + + if(!zuma_pbb_reg) { + printf("zuma pbb bar none! (hah hah, get it?)\n"); + return; + } + + zuma_pbb_reg->int_mask.word=0; + + printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg, + zuma_pbb_reg->version.pci_bits.rev_major, + zuma_pbb_reg->version.pci_bits.rev_minor, + zuma_pbb_reg->timestamp); + +} diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h new file mode 100644 index 0000000..663e10c --- /dev/null +++ b/board/evb64260/zuma_pbb.h @@ -0,0 +1,346 @@ +#ifndef ZUMA_PBB_H +#define ZUMA_PBB_H + +#define MAX_NUM_BUFFER_PER_RING 32 + +#ifdef __BIG_ENDIAN +#define cpu_bits _be_s_bits /* use with le32_to_cpu only */ +#define pci_bits _be_bits /* may contain swapped bytes, + but dont need le32_to_cpu */ +#endif + +#ifdef __LITTLE_ENDIAN +#define cpu_bits _le_bits +#define pci_bits _le_bits +#endif + +#define VENDOR_ID_ZUMA 0x1172 +#define DEVICE_ID_ZUMA_PBB 0x0004 + +#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */ +#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */ +#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */ +#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */ + +#define PBB_DMA_OWN_BIT 0x80000000 +#define PBB_DMA_LAST_BIT 0x40000000 + +#define EOF_RX_FLAG 1 /* bit 0 */ +#define EOB_RX_FLAG 2 /* bit 1 */ +#define EOF_TX_FLAG 4 /* bit 2 */ +#define EOB_TX_FLAG 8 /* bit 3 */ + +#define TX_MODE(m) (((m)&7) << 16) + +#define RX_DESC(i) (cs->rx_desc[i]) +#define TX_DESC(i) (cs->tx_desc[i]) + +#define RX_CONTROL(i) (RX_DESC(i).control.word) +#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size) +#define TX_CONTROL(i) (TX_DESC(i).control.word) + +#define RX_DATA_P(i) (&RX_DESC(i).ptr) +#define TX_DATA_P(i) (&TX_DESC(i).ptr) + +typedef volatile unsigned char V8; +typedef volatile unsigned short V16; +typedef volatile unsigned int V32; + +/* RAM descriptor layout */ +typedef struct _tag_dma_descriptor { + V32 ptr; + union { + struct { + V32 owner:1; + V32 last:1; + V32 reserved0: 10; + V32 tx_mode: 4; + + V32 reserved1: 5; + V32 size: 11; + } tx; + struct { + V32 owner:1; + V32 last:1; + V32 reserved0: 14; + + V32 reserved1: 5; + V32 size: 11; + } rx; + V32 word; + } control; +} DMA_DESCRIPTOR; + +/* + * NOTE: DO NOT USE structure to write non-word values... all registers + * MUST be written 4 bytes at a time in SI version 0. + * Non-word writes will result in "unaccessed" bytes written as zero. + * + * Byte reads are allowed. + * + * V32 pads are because the registers are spaced every 8 bytes (64 bits) + * + */ + +/* NOTE!!! 4 dwords */ +typedef struct _tag_dma_descriptor_ring { + DMA_DESCRIPTOR *base; + V32 pad1; /* skip high dword */ + volatile DMA_DESCRIPTOR *current; + V32 pad3; /* skip high dword */ +} DMA_DESCRIPTOR_RING; + +/* 1 dword */ +typedef union _tag_dma_generic { + struct { /* byte 3 2 1 0 */ + V32 chan7:4; /* bits 31-28 */ + V32 chan6:4; /* bits 27-24 */ + V32 chan5:4; /* bits 23-20 */ + V32 chan4:4; /* bits 19-16 */ + V32 chan3:4; /* bits 15-12 */ + V32 chan2:4; /* bits 11-8 */ + V32 chan1:4; /* bits 7-4 */ + V32 chan0:4; /* bits 3-0 */ + } _be_s_bits; + struct { /* byte 0 1 2 3 */ + V32 chan1:4; /* bits 7-4 */ + V32 chan0:4; /* bits 3-0 */ + V32 chan3:4; /* bits 15-12 */ + V32 chan2:4; /* bits 11-8 */ + V32 chan5:4; /* bits 23-20 */ + V32 chan4:4; /* bits 19-16 */ + V32 chan7:4; /* bits 31-28 */ + V32 chan6:4; /* bits 27-24 */ + } _be_bits; + struct { /* byte 0 1 2 3 */ + V32 chan0:4; /* bits 0-3 */ + V32 chan1:4; /* bits 4-7 */ + V32 chan2:4; /* bits 8-11 */ + V32 chan3:4; /* bits 12-15 */ + V32 chan4:4; /* bits 16-19 */ + V32 chan5:4; /* bits 20-23 */ + V32 chan6:4; /* bits 24-27 */ + V32 chan7:4; /* bits 28-31 */ + } _le_bits; + V8 byte[4]; + V32 word; +} DMA_RXTX_ENABLE, DMA_RX_DELETE, + DMA_INT_STATUS, DMA_INT_MASK, + DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK; + +/* 1 dword */ +typedef union _tag_dma_rx_timer{ + struct { + V32 res0:8; /* bits 32-24 */ + V32 res1:7; /* bits 23-17 */ + V32 enable:1; /* bit 16 */ + V32 value:16; /* bits 15-0 */ + } _be_s_bits; + struct { + /* crosses byte boundary. must use swap. */ + V32 s_value:16; /* bits 7-0,15-8 */ + V32 enable:1; /* bit 16 */ + V32 res1:7; /* bits 23-17 */ + V32 res0:8; /* bits 32-24 */ + } _be_bits; + struct { + V32 value:16; /* bits 0-15 */ + V32 enable:1; /* bit 16 */ + V32 res1:7; /* bits 17-23 */ + V32 res0:8; /* bits 24-32 */ + } _le_bits; + V8 byte[4]; + V32 word; +} DMA_RX_TIMER; + +/* NOTE!!!: 2 dwords */ +typedef struct _tag_dma_desc_level{ + union { + struct { + V32 res1:8; /* bits 31-24 */ + V32 res0:7; /* bits 23-17 */ + V32 write:1; /* bit 16 */ + V32 thresh:8; /* bits 15-8 */ + V32 level:8; /* bits 7-0 */ + } _be_s_bits; + struct { + V32 level:8; /* bits 7-0 */ + V32 thresh:8; /* bits 15-8 */ + V32 res0:7; /* bits 30-17 */ + V32 write:1; /* bit 16 */ + V32 res1:8; /* bits 31-24 */ + } _be_bits; + struct { + V32 level:8; /* bits 0-7 */ + V32 thresh:8; /* bits 8-15 */ + V32 write:1; /* bit 16 */ + V32 res0:7; /* bit 17-30 */ + V32 res1:8; /* bits 24-31 */ + } _le_bits; + V8 byte[4]; + V32 word; + } desc; + V32 pad1; +} DMA_DESC_LEVEL; + +typedef struct _tag_pbb_dma_reg_map { + /* 0-15 (0x000-0x078) */ + DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */ + + /* 16-31 (0x080-0x0f8) */ + DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */ + + /* 32/33 (0x100/0x108) */ + V32 reserved_32; + V32 pad_32; + V32 reserved_33; + V32 pad_33; + + /* 34 (0x110) */ + DMA_RXTX_ENABLE rxtx_enable; + V32 pad_34; + + /* 35 (0x118) */ + DMA_RX_DELETE rx_delete; + V32 pad_35; + + /* 36-38 (0x120-0x130) */ + DMA_INT_STATUS status; + V32 pad_36; + DMA_INT_STATUS last_status; + V32 pad_37; + DMA_INT_MASK int_mask; + V32 pad_38; + + /* 39/40 (0x138/0x140) */ + union { + /* NOTE!! 4 dwords */ + struct { + V32 channel_3:8; + V32 channel_2:8; + V32 channel_1:8; + V32 channel_0:8; + V32 pad1; + V32 channel_7:8; + V32 channel_6:8; + V32 channel_5:8; + V32 channel_4:8; + V32 pad3; + } _be_s_bits; + struct { + V32 channel_0:8; + V32 channel_1:8; + V32 channel_2:8; + V32 channel_3:8; + V32 pad1; + V32 channel_4:8; + V32 channel_5:8; + V32 channel_6:8; + V32 channel_7:8; + V32 pad3; + } _be_bits, _le_bits; + V8 byte[16]; + V32 word[4]; + } rx_size; + + /* 41/42 (0x148/0x150) */ + V32 reserved_41; + V32 pad_41; + V32 reserved_42; + V32 pad_42; + + /* 43/44 (0x158/0x160) */ + DMA_RX_LEVEL_STATUS rx_level_status; + V32 pad_43; + DMA_RX_LEVEL_INT_MASK rx_level_int_mask; + V32 pad_44; + + /* 45 (0x168) */ + DMA_RX_TIMER rx_timer; + V32 pad_45; + + /* 46 (0x170) */ + V32 reserved_46; + V32 pad_46; + + /* 47 (0x178) */ + V32 mbox_status; + V32 pad_47; + + /* 48/49 (0x180/0x188) */ + V32 mbox_out; + V32 pad_48; + V32 mbox_in; + V32 pad_49; + + /* 50 (0x190) */ + V32 config; + V32 pad_50; + + /* 51/52 (0x198/0x1a0) */ + V32 c2a_ctr; + V32 pad_51; + V32 a2c_ctr; + V32 pad_52; + + /* 53 (0x1a8) */ + union { + struct { + V32 rev_major:8; /* bits 31-24 */ + V32 rev_minor:8; /* bits 23-16 */ + V32 reserved:16; /* bits 15-0 */ + } _be_s_bits; + struct { + V32 s_reserved:16; /* bits 7-0, 15-8 */ + V32 rev_minor:8; /* bits 23-16 */ + V32 rev_major:8; /* bits 31-24 */ + } _be_bits; + struct { + V32 reserved:16; /* bits 0-15 */ + V32 rev_minor:8; /* bits 16-23 */ + V32 rev_major:8; /* bits 24-31 */ + } _le_bits; + V8 byte[4]; + V32 word; + } version; + V32 pad_53; + + /* 54-59 (0x1b0-0x1d8) */ + V32 debug_54; + V32 pad_54; + V32 debug_55; + V32 pad_55; + V32 debug_56; + V32 pad_56; + V32 debug_57; + V32 pad_57; + V32 debug_58; + V32 pad_58; + V32 debug_59; + V32 pad_59; + + /* 60 (0x1e0) */ + V32 timestamp; + V32 pad_60; + + /* 61-63 (0x1e8-0x1f8) */ + V32 debug_61; + V32 pad_61; + V32 debug_62; + V32 pad_62; + V32 debug_63; + V32 pad_63; + + /* 64-71 (0x200 - 0x238) */ + DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */ + + /* 72-98 (0x240 - 0x2f8) */ + /* reserved */ + + /* 96-127 (0x300 - 0x3f8) */ + /* mirrors (0x100 - 0x1f8) */ + +} PBB_DMA_REG_MAP; + + +#endif /* ZUMA_PBB_H */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c new file mode 100644 index 0000000..6e414cc --- /dev/null +++ b/board/evb64260/zuma_pbb_mbox.c @@ -0,0 +1,182 @@ +#include +#include +#include +#include "zuma_pbb.h" +#include "zuma_pbb_mbox.h" + + +struct _zuma_mbox_dev zuma_mbox_dev; + + +static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) +{ + unsigned int status, count = 0, i; + + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + + while((status & OUT_PENDING) && count < 1000) { + count++; + for(i=0;i<1000;i++); + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + } + if(count < 1000) { + /* if SET it means msg pending */ + // printf("mbox real write %08x\n",data); + dev->sip->mbox_out = cpu_to_le32(data); + return 4; + } + + printf("mbox tx timeout\n"); + return 0; +} + +static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) +{ + unsigned int status, count = 0, i; + + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + + while(!(status & IN_VALID) && count < 1000) { + count++; + for(i=0;i<1000;i++); + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + } + if(count < 1000) { + /* if SET it means msg pending */ + *data=le32_to_cpu(dev->sip->mbox_in); + //printf("mbox real read %08x\n", *data); + return 4; + } + printf("mbox rx timeout\n"); + return 0; +} + +static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) +{ + int ret; + ret=zuma_mbox_write(&zuma_mbox_dev,out); + //printf("write 0x%08x (%d bytes)\n", out, ret); + if(ret!=4) return -1; + ret=zuma_mbox_read(&zuma_mbox_dev,in); + //printf("read 0x%08x (%d bytes)\n", *in, ret); + if(ret!=4) return -1; + return 0; +} + + +#define RET_IF_FAILED(x) if ((x) == -1) return -1 + +static int zuma_mbox_do_all_mailbox(void) +{ + unsigned int data_in; + unsigned short sdata_in; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); + memcpy(zuma_acc_mac+2,&data_in,4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); + sdata_in=data_in&0xffff; + memcpy(zuma_acc_mac,&sdata_in,2); + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); + zuma_ip=data_in; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); + zuma_slot_bac=data_in>>3; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); + zuma_console_baud = data_in & 0xffff; + zuma_debug_baud = data_in >> 16; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); + memcpy(zuma_prv_mac+2,&data_in,4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); + sdata_in=data_in&0xffff; + memcpy(zuma_prv_mac,&sdata_in,2); + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); + + return 0; +} + + +static void +zuma_mbox_dump(void) +{ + printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2)); + printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2)); + printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3); + printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud); +} + + +static void +zuma_mbox_setenv(void) +{ + unsigned char *data, buf[32]; + unsigned char save = 0; + + data = getenv("baudrate"); + + if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { + sprintf(buf, "%6d", zuma_console_baud); + setenv("baudrate", buf); + save=1; + printf("baudrate doesn't match from mbox\n"); + } + + ip_to_string(zuma_ip, buf); + setenv("ipaddr", buf); + + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x", + zuma_prv_mac[0], + zuma_prv_mac[1], + zuma_prv_mac[2], + zuma_prv_mac[3], + zuma_prv_mac[4], + zuma_prv_mac[5]); + setenv("ethaddr", buf); + + sprintf(buf,"%02x",zuma_slot_bac); + setenv("bacslot", buf); + + if(save) + saveenv(); +} + +/** + * zuma_mbox_init: + */ + +int zuma_mbox_init(void) +{ + memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); + + zuma_mbox_dev.dev = pciFindDevice(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB); + + if(!zuma_mbox_dev.dev) { + printf("no zuma pbb\n"); + return -1; + } + + zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)zuma_mbox_dev.dev->bar[0].base; + + zuma_mbox_dev.sip->int_mask.word=0; + + printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, + zuma_mbox_dev.sip->version.pci_bits.rev_major, + zuma_mbox_dev.sip->version.pci_bits.rev_minor, + zuma_mbox_dev.sip->timestamp); + + if (zuma_mbox_do_all_mailbox() == -1) { + printf("mailbox failed.. no ACC?\n"); + return -1; + } + + zuma_mbox_dump(); + + zuma_mbox_setenv(); + + return 0; +} diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h new file mode 100644 index 0000000..fc65c04 --- /dev/null +++ b/board/evb64260/zuma_pbb_mbox.h @@ -0,0 +1,43 @@ +#define IN_VALID 1 +#define OUT_PENDING 2 + +enum { + ZUMA_MBOXMSG_DONE, + ZUMA_MBOXMSG_MACL, + ZUMA_MBOXMSG_MACH, + ZUMA_MBOXMSG_IP, + ZUMA_MBOXMSG_SLOT, + ZUMA_MBOXMSG_RESET, + ZUMA_MBOXMSG_BAUD, + ZUMA_MBOXMSG_START, + ZUMA_MBOXMSG_ENG_PRV_MACL, + ZUMA_MBOXMSG_ENG_PRV_MACH, + + MBOXMSG_LAST +}; + +struct zuma_mailbox_info { + unsigned char acc_mac[6]; + unsigned char prv_mac[6]; + unsigned int ip; + unsigned int slot_bac; + unsigned int console_baud; + unsigned int debug_baud; +}; + +struct _zuma_mbox_dev { + PCI_DEVICE *dev; + PBB_DMA_REG_MAP *sip; + struct zuma_mailbox_info mailbox; +}; + +#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac +#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac +#define zuma_ip zuma_mbox_dev.mailbox.ip +#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac +#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud +#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud + + +extern struct _zuma_mbox_dev zuma_mbox_dev; +extern int zuma_mbox_init(void); diff --git a/board/musenki/Makefile b/board/musenki/Makefile index 444bc76..3d890bd 100644 --- a/board/musenki/Makefile +++ b/board/musenki/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o ns16550.o serial.o dc2114x.o -SOBJS = early_init.o +SOBJS = $(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/musenki/early_init.S b/board/musenki/early_init.S deleted file mode 100644 index 18b42be..0000000 --- a/board/musenki/early_init.S +++ /dev/null @@ -1,381 +0,0 @@ -#include -#include - - .globl __pci_config_read_32 -__pci_config_read_32: - lis r4, 0xfec0 - stwbrx r3, r0, r4 - sync - lis r4, 0xfee0 - lwbrx r3, 0, r4 - blr - .globl __pci_config_read_16 -__pci_config_read_16: - lis r4, 0xfec0 - andi. r5, r3, 2 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lhbrx r3, r0, r4 - blr - .globl __pci_config_read_8 -__pci_config_read_8: - lis r4, 0xfec0 - andi. r5, r3, 3 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lbz r3, 0(4) - blr - .globl __pci_config_write_32 -__pci_config_write_32: - lis r5, 0xfec0 - stwbrx r3, r0, r5 - sync - lis r5, 0xfee0 - stwbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_16 -__pci_config_write_16: - lis r5, 0xfec0 - andi. r6, r3, 2 - stwbrx r3, r0, 5 - sync - oris r5, r6, 0xfee0 - sthbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_8 -__pci_config_write_8: - lis r5, 0xfec0 - andi. r6, r3, 3 - stwbrx r3, r0, r5 - sync - oris r5, r6, 0xfee0 - stb r4, 0(r5) - sync - blr - .globl in_8 -in_8: - oris r3, r3, 0xfe00 - lbz r3,0(r3) - blr - .globl in_16 -in_16: - oris r3, r3, 0xfe00 - lhbrx r3, 0, r3 - blr - .globl in_16_ne -in_16_ne: - oris r3, r3, 0xfe00 - lhzx r3, 0, r3 - blr - .globl in_32 -in_32: - oris r3, r3, 0xfe00 - lwbrx r3, 0, r3 - blr - .globl out_8 -out_8: - oris r3, r3, 0xfe00 - stb r4, 0(r3) - eieio - blr - .globl out_16 -out_16: - oris r3, r3, 0xfe00 - sthbrx r4, 0, r3 - eieio - blr - .globl out_16_ne -out_16_ne: - oris r3, r3, 0xfe00 - sth r4, 0(r3) - eieio - blr - .globl out_32 -out_32: - oris r3, r3, 0xfe00 - stwbrx r4, 0, r3 - eieio - blr - .globl read_8 -read_8: - lbz r3,0(r3) - blr - .globl read_16 -read_16: - lhbrx r3, 0, r3 - blr - .globl read_32 -read_32: - lwbrx r3, 0, r3 - blr - .globl read_32_ne -read_32_ne: - lwz r3, 0(r3) - blr - .globl write_8 -write_8: - stb r4, 0(r3) - eieio - blr - .globl write_16 -write_16: - sthbrx r4, 0, r3 - eieio - blr - .globl write_32 -write_32: - stwbrx r4, 0, r3 - eieio - blr - .globl write_32_ne -write_32_ne: - stw r4, 0(r3) - eieio - blr - - -.globl early_init_f - -early_init_f: - mflr r11 - lis r10, 0x8000 - - /* PCI Latency Timer */ - li r4, 0x0d - ori r3, r10, PLTR@l - bl __pci_config_write_8 - - /* Cache Line Size */ - li r4, 0x08 - ori r3, r10, PCLSR@l - bl __pci_config_write_8 - - /* PCI Cmd */ - li r4, 6 - ori r3, r10, PCICR@l - bl __pci_config_write_16 - -#if 1 - /* PCI Stat */ - ori r3, r10, PCISR@l - bl __pci_config_read_16 - ori r4, r4, 0xffff - ori r3, r10, PCISR@l - bl __pci_config_write_16 -#endif - - /* PICR1 */ - lis r4, 0xff14 - ori r4, r4, 0x1b98 - ori r3, r10, PICR1@l - bl __pci_config_write_32 - - - /* PICR2 */ - lis r4, 0x0404 - ori r4, r4, 0x0004 - ori r3, r10, PICR2@l - bl __pci_config_write_32 - - /* MIOCR1 */ - li r4, 0x00 - ori r3, r10, MIOCR1@l - bl __pci_config_write_8 - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - li r4, 0x10 - ori r3, r10, MIOCR2@l - bl __pci_config_write_8 - - /* EUMBBAR */ - lis r4, 0xfc00 - ori r3, r10, EUMBBAR@l - bl __pci_config_write_32 - - /* AMBOR */ - - /* Even if Address Map B is not being used (though it should), - * the memory DLL needs to be cleared/set/cleared before using memory. - */ - - ori r3, r10, AMBOR@l - bl __pci_config_read_8 /* get Current bits */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - ori r4, r4, 0x0020 - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Set DLL_RESET */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - /* Preserve memgo bit */ - /* MCCR1 */ - - lis r4, 0x75a8 // Safe Local ROM = 11+3 clocks -// lis r4, 0x73a0 // Fast Local ROM = 7+3 clocks -// oris r4, r4, 0x0010 // Burst ROM/Flash enable -// oris r4, r4, 0x0004 // Self-refresh enable - -// ori r4,r4,0xFFFF // 16Mbit 2bank SDRAM -// ori r4,r4,0xAAAA // 256Mbit 4bank SDRAM (8245 only) -// ori r4,r4,0x5555 // 64Mbit 2bank SDRAM - ori r4,r4,0x0000 // 64Mbit 4bank SDRAM - - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* MCCR2 */ - - lis r4,0x0000 -/* oris r4,r4,0x4000 // TS_WAIT_TIMER = 3 clocks */ -/* oris r4,r4,0x0400 // ASRISE = 2 clocks */ -/* oris r4,r4,0x0040 // ASFALL = 2 clocks */ -/* oris r4,r4,0x0010 // SDRAM Parity (else ECC) */ -/* oris r4,r4,0x0008 // Write parity check */ -/* oris r4,r4,0x0004 // SDRAM inline reads */ - - -/* Select a refresh rate; it needs to match the bus speed; if too */ -/* slow, data may be lost; if too fast, performance is lost. We */ -/* use the fastest value so we run at all speeds. */ -/* Refresh = (15600ns/busclk) - (213 (see UM)). */ - -/* ori r4,r4,0x1d2c // 133 MHz mem bus = 1867 */ - ori r4,r4,0x150c /* 100 MHz mem bus = 1347 */ -/* ori r4,r4,0x10fc // 83 MHz mem bus = 1087 */ -/* ori r4,r4,0x0cc4 // 66 MHz mem bus = 817 */ -/* ori r4,r4,0x04cc // 33 MHz mem bus (SAFE) = 307 */ - -/* ori r4,r4,0x0002 // Reserve a page */ -/* ori r4,r4,0x0001 // RWM parity */ - - ori r3, r10, MCCR2@l - bl __pci_config_write_32 - - - /* MCCR3 */ - lis r4,0x7000 // BSTOPRE_M = 7 (see A/N) - oris r4,r4,0x0800 // REFREC = 8 clocks - ori r3, r10, MCCR3@l - bl __pci_config_write_32 - - /* MCCR4 */ - lis r4, 0x3000 // PRETOACT = 3 clocks - oris r4,r4,0x0500 // ACTOPRE = 5 clocks - oris r4,r4,0x0080 // Enable 8-beat burst (32-bit bus) -// oris r4,r4,0x0040 // Enable Inline ECC/Parity - oris r4,r4,0x0020 // EXTROM enabled - oris r4,r4,0x0010 // Registered buffers -// oris r4,r4,0x0000 // BSTOPRE_U = 0 (see A/N) - oris r4,r4,0x0002 // DBUS_SIZ[2] (8 bit on RCS1) - -// ori r4,r4,0x8000 // Registered DIMMs - ori r4,r4,0x3000 // CAS Latency (CL=3) (see RDLAT) -// ori r4,r4,0x2000 // CAS Latency (CL=2) (see RDLAT) -// ori r4,r4,0x0300 // Sequential wrap/8-beat burst - ori r4,r4,0x0030 // ACTORW = 3 clocks - ori r4,r4,0x0009 // BSTOPRE_L = 9 (see A/N) - - ori r3, r10, MCCR4@l - bl __pci_config_write_32 - - /* MSAR1 */ - lis r4, 0xffffff00 - ori r3, r10, MSAR1@l - bl __pci_config_write_32 - - /* MSAR2 */ - lis r4, 0xffffffff - ori r3, r10, MSAR2@l - bl __pci_config_write_32 - - /* MESAR1 */ - lis r4, 0x03030300@h - li r4, 0x03030300@l - ori r3, r10, EMSAR1@l - bl __pci_config_write_32 - - /* MESAR2 */ - lis r4, 0x03030303@h - li r4, 0x03030303@l - ori r3, r10, EMSAR2@l - bl __pci_config_write_32 - - /* MEAR1 */ - lis r4, 0xffffff7f@h - li r4, 0xffffff7f@l - ori r3, r10, MEAR1@l - bl __pci_config_write_32 - - /* MEAR2 */ - lis r4, 0xffffffff@h - li r4, 0xffffffff@l - ori r3, r10, MEAR2@l - bl __pci_config_write_32 - - /* MEEAR1 */ - lis r4, 0x03030300@h - li r4, 0x03030300@l - ori r3, r10, EMEAR1@l - bl __pci_config_write_32 - - /* MEEAR2 */ - lis r4, 0x03030303@h - li r4, 0x03030303@l - ori r3, r10, EMEAR2@l - bl __pci_config_write_32 - - /* ODCR */ - li r4, 0x1c - ori r3, r10, ODCR@l - bl __pci_config_write_8 - - /* MBER */ - li r4, 0x01 - ori r3, r10, MBER@l - bl __pci_config_write_8 - - /* Page CTR aka PGMAX */ - li r4, 0x32 - ori r3, r10, 0xa3 - bl __pci_config_write_8 - -#if 0 - /* CLK Drive */ - ori r4, r10, 0xfc01 /* Top bit will be ignored */ - ori r3, r10, 0x74 - bl __pci_config_write_16 -#endif - - /* delay */ - lis r7, 1 - mtctr r7 -label1: bdnz label1 - - /* Set memgo bit */ - /* MCCR1 */ - ori r3, r10, MCCR1@l - bl __pci_config_read_32 - lis r7, 0x0008 - or r4, r3, r7 - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* delay again */ - lis r7, 1 - mtctr r7 -label2: bdnz label2 - - mtlr r11 - blr - diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c index fc51e42..5ffaa74 100644 --- a/board/musenki/musenki.c +++ b/board/musenki/musenki.c @@ -100,3 +100,10 @@ Done: return (32 * 1024 * 1024); #endif } + +/* + * Initialize PCI Devices + */ +void pci_init (bd_t *dummy) +{ +} diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 9b2beef..35875f8 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "pci.h" @@ -156,7 +157,7 @@ void pcippc2_wdt_reset (void) out8 (FPGA (WDT, REFRESH), 0x56); } -watchdog_reset (void) +void watchdog_reset (void) { int re_enable = disable_interrupts (); diff --git a/board/sandpoint/eepro100.c b/board/sandpoint/eepro100.c index 09450fa..5db82e9 100644 --- a/board/sandpoint/eepro100.c +++ b/board/sandpoint/eepro100.c @@ -6,30 +6,30 @@ /* Ethernet chip registers. */ -#define SCBStatus 0 /* Rx/Command Unit Status *Word* */ -#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ -#define SCBCmd 2 /* Rx/Command Unit Command *Word* */ -#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ -#define SCBPointer 4 /* General purpose pointer. */ -#define SCBPort 8 /* Misc. commands and operands. */ -#define SCBflash 12 /* Flash memory control. */ -#define SCBeeprom 14 /* EEPROM memory control. */ -#define SCBCtrlMDI 16 /* MDI interface control. */ -#define SCBEarlyRx 20 /* Early receive byte count. */ -#define SCBGenControl 28 /* 82559 General Control Register */ -#define SCBGenStatus 29 /* 82559 General Status register */ +#define SCBStatus 0 /* Rx/Command Unit Status *Word* */ +#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ +#define SCBCmd 2 /* Rx/Command Unit Command *Word* */ +#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ +#define SCBPointer 4 /* General purpose pointer. */ +#define SCBPort 8 /* Misc. commands and operands. */ +#define SCBflash 12 /* Flash memory control. */ +#define SCBeeprom 14 /* EEPROM memory control. */ +#define SCBCtrlMDI 16 /* MDI interface control. */ +#define SCBEarlyRx 20 /* Early receive byte count. */ +#define SCBGenControl 28 /* 82559 General Control Register */ +#define SCBGenStatus 29 /* 82559 General Status register */ /* 82559 SCB status word defnitions */ -#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ -#define SCB_STATUS_FR 0x4000 /* frame received */ -#define SCB_STATUS_CNA 0x2000 /* CU left active state */ -#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ -#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ -#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ -#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ +#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ +#define SCB_STATUS_FR 0x4000 /* frame received */ +#define SCB_STATUS_CNA 0x2000 /* CU left active state */ +#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ +#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ +#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ +#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ -#define SCB_INTACK_MASK 0xFD00 /* all the above */ +#define SCB_INTACK_MASK 0xFD00 /* all the above */ #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) @@ -40,24 +40,24 @@ #define CU_NOP 0x0000 #define CU_START 0x0010 #define CU_RESUME 0x0020 -#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ -#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ -#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ -#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ +#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ +#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ +#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ +#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ /* RUC Commands */ #define RUC_NOP 0x0000 #define RUC_START 0x0001 #define RUC_RESUME 0x0002 #define RUC_ABORT 0x0004 -#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ +#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ #define RUC_RESUMENR 0x0007 #define CU_CMD_MASK 0x00f0 #define RU_CMD_MASK 0x0007 -#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ -#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ +#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ +#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ #define CU_STATUS_MASK 0x00C0 #define RU_STATUS_MASK 0x003C @@ -72,23 +72,23 @@ /* 82559 Port interface commands. */ -#define I82559_RESET 0x00000000 /* Software reset */ -#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ +#define I82559_RESET 0x00000000 /* Software reset */ +#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ #define I82559_SELECTIVE_RESET 0x00000002 #define I82559_DUMP 0x00000003 #define I82559_DUMP_WAKEUP 0x00000007 /* 82559 Eeprom interface. */ -#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ -#define EE_CS 0x02 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ #define EE_WRITE_0 0x01 #define EE_WRITE_1 0x05 -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ #define EE_ENB (0x4800 | EE_CS) - /* The EEPROM commands include the alway-set leading bit. + /* The EEPROM commands include the alway-set leading bit. */ #define EE_WRITE_CMD (5 << addr_len) #define EE_READ_CMD (6 << addr_len) @@ -99,67 +99,66 @@ struct RxFD { volatile u16 status; volatile u16 control; - volatile u32 link; /* struct RxFD * */ - volatile u32 rx_buf_addr; /* void * */ + volatile u32 link; /* struct RxFD * */ + volatile u32 rx_buf_addr; /* void * */ volatile u32 count; - volatile u8 data[PKTSIZE_ALIGN]; }; -#define RFD_STATUS_C 0x8000 /* completion of received frame */ -#define RFD_STATUS_OK 0x2000 /* frame received with no errors */ +#define RFD_STATUS_C 0x8000 /* completion of received frame */ +#define RFD_STATUS_OK 0x2000 /* frame received with no errors */ -#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ -#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ -#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ -#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ +#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ +#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ +#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ +#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ #define RFD_COUNT_MASK 0x3fff #define RFD_COUNT_F 0x4000 #define RFD_COUNT_EOF 0x8000 -#define RFD_RX_CRC 0x0800 /* crc error */ -#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ -#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ -#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ -#define RFD_RX_SHORT 0x0080 /* short frame error */ +#define RFD_RX_CRC 0x0800 /* crc error */ +#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ +#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ +#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ +#define RFD_RX_SHORT 0x0080 /* short frame error */ #define RFD_RX_LENGTH 0x0020 -#define RFD_RX_ERROR 0x0010 /* receive error */ -#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ -#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ -#define RFD_RX_TCO 0x0001 /* TCO indication */ +#define RFD_RX_ERROR 0x0010 /* receive error */ +#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ +#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ +#define RFD_RX_TCO 0x0001 /* TCO indication */ /* Transmit frame descriptors */ -struct TxFD { /* Transmit frame descriptor set. */ +struct TxFD { /* Transmit frame descriptor set. */ volatile u16 status; volatile u16 command; - volatile u32 link; /* void * */ - volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ + volatile u32 link; /* void * */ + volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ volatile s32 count; - volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ - volatile s32 tx_buf_size0; /* Length of Tx frame. */ - volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ - volatile s32 tx_buf_size1; /* Length of Tx frame. */ + volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size0; /* Length of Tx frame. */ + volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size1; /* Length of Tx frame. */ }; -#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ -#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ -#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ -#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ -#define TxCB_CMD_S 0x4000 /* suspend on completion */ -#define TxCB_CMD_EL 0x8000 /* last command block in CBL */ +#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ +#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ +#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ +#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ +#define TxCB_CMD_S 0x4000 /* suspend on completion */ +#define TxCB_CMD_EL 0x8000 /* last command block in CBL */ #define TxCB_COUNT_MASK 0x3fff #define TxCB_COUNT_EOF 0x8000 - /* The Speedo3 Rx and Tx frame/buffer descriptors. + /* The Speedo3 Rx and Tx frame/buffer descriptors. */ -struct descriptor { /* A generic descriptor. */ +struct descriptor { /* A generic descriptor. */ volatile u16 status; volatile u16 command; - volatile u32 link; /* struct descriptor * */ + volatile u32 link; /* struct descriptor * */ unsigned char params[0]; }; @@ -167,8 +166,8 @@ struct descriptor { /* A generic descriptor. */ #define CFG_CMD_EL 0x8000 #define CFG_CMD_SUSPEND 0x4000 #define CFG_CMD_INT 0x2000 -#define CFG_CMD_IAS 0x0001 /* individual address setup */ -#define CFG_CMD_CONFIGURE 0x0002 /* configure */ +#define CFG_CMD_IAS 0x0001 /* individual address setup */ +#define CFG_CMD_CONFIGURE 0x0002 /* configure */ #define CFG_STATUS_C 0x8000 #define CFG_STATUS_OK 0x2000 @@ -176,65 +175,63 @@ struct descriptor { /* A generic descriptor. */ /* Misc. */ #define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 1 /* Number of TX descriptors */ +#define NUM_TX_DESC 1 /* Number of TX descriptors */ #define TOUT_LOOP 1000000 #define ETH_ALEN 6 -static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ -static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ -static int rx_next; /* RX descriptor ring pointer */ -static int tx_next; /* TX descriptor ring pointer */ +static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ +static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ +static int rx_next; /* RX descriptor ring pointer */ +static int tx_next; /* TX descriptor ring pointer */ static int tx_threshold; static u_long iobase = 0; -static void init_rx_ring(void); -static void purge_tx_ring(void); +static void init_rx_ring (void); +static void purge_tx_ring (void); -static void check_hw_addr(bd_t * bis); +static void check_hw_addr (bd_t * bis); -static inline int INL(u_long addr) +static inline int INL (u_long addr) { - return le32_to_cpu(*(volatile u32 *)(addr + iobase)); + return le32_to_cpu (*(volatile u32 *) (addr + iobase)); } -static inline int INW(u_long addr) +static inline int INW (u_long addr) { - return le16_to_cpu(*(volatile u16 *)(addr + iobase)); + return le16_to_cpu (*(volatile u16 *) (addr + iobase)); } -static inline int INB(u_long addr) +static inline int INB (u_long addr) { - return *(volatile u8 *)(addr + iobase); + return *(volatile u8 *) (addr + iobase); } -static inline void OUTB(int command, u_long addr) +static inline void OUTB (int command, u_long addr) { - *(volatile u8 *)(addr + iobase) = command; + *(volatile u8 *) (addr + iobase) = command; } -static inline void OUTW(int command, u_long addr) +static inline void OUTW (int command, u_long addr) { - *(volatile u16 *)(addr + iobase) = cpu_to_le16(command); + *(volatile u16 *) (addr + iobase) = cpu_to_le16 (command); } -static inline void OUTL(int command, u_long addr) +static inline void OUTL (int command, u_long addr) { - *(volatile u32 *)(addr + iobase) = cpu_to_le32(command); + *(volatile u32 *) (addr + iobase) = cpu_to_le32 (command); } /* Wait for the chip get the command. */ -static int wait_for_eepro100(void) +static int wait_for_eepro100 (void) { int i; - for(i = 0; INW(SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) - { - if (i >= TOUT_LOOP) - { + for (i = 0; INW (SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { + if (i >= TOUT_LOOP) { return 0; } } @@ -242,242 +239,226 @@ static int wait_for_eepro100(void) return 1; } -int eth_init(bd_t *bis) +int eth_init (bd_t * bis) { int i, status = 0; int bus, devno, func; int tx_cur; struct descriptor *ias_cmd; - /* Find PCI device + /* Find PCI device */ - if (pci_dev_find(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82557, - 0, &bus, &devno, &func) != TRUE) - { - printf("Error: Can not find an ethernet card on the PCI bus\n"); - goto Done; + if ((pci_dev_find (PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82557, + 0, &bus, &devno, &func) != TRUE) && + (pci_dev_find (PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82559, + 0, &bus, &devno, &func) != TRUE)) { + puts ("Error: Can not find an ethernet card on the PCI bus\n"); + return (status); } pci_config_inl (bus, devno, func, - PCI_CFG_BASE_ADDRESS_0, (uint32 *)&iobase); + PCI_CFG_BASE_ADDRESS_0, (uint32 *) & iobase); iobase &= PCI_MEMBASE_MASK; - printf("eth: Intel i82559 PCI EtherExpressPro @0x%lX" - "(bus=%d, device=%d, func=%d)\n", - iobase, bus, devno, func); - - pci_config_outl (bus, devno, func, - PCI_CFG_COMMAND, - PCI_CMD_MEM_ENABLE | - PCI_CMD_MASTER_ENABLE); - - /* Check if I/O accesses and Bus Mastering are enabled. - */ - pci_config_inl (bus, devno, func, - PCI_CFG_COMMAND, &status); + printf ("eth: Intel i82559 PCI EtherExpressPro @0x%lX" + "(bus=%d, device=%d, func=%d)\n", + iobase, bus, devno, func); + + pci_config_outl (bus, devno, func, + PCI_CFG_COMMAND, + PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE); - if (!(status & PCI_CMD_MEM_ENABLE)) - { - printf("Error: Can not enable MEM access.\n"); - goto Done; + /* Check if I/O accesses and Bus Mastering are enabled. + */ + pci_config_inl (bus, devno, func, PCI_CFG_COMMAND, &status); + + if (!(status & PCI_CMD_MEM_ENABLE)) { + puts ("Error: Can not enable MEM access\n"); + return (status); } - if (!(status & PCI_CMD_MASTER_ENABLE)) - { - printf("Error: Can not enable Bus Mastering.\n"); - goto Done; + if (!(status & PCI_CMD_MASTER_ENABLE)) { + puts ("Error: Can not enable Bus Mastering\n"); + return (status); } - /* Set the latency timer for value. - */ - pci_config_outb(bus, devno, func, - PCI_CFG_LATENCY_TIMER, - PCI_LATENCY_TIMER); + /* Set the latency timer for value. + */ + pci_config_outb (bus, devno, func, + PCI_CFG_LATENCY_TIMER, PCI_LATENCY_TIMER); - udelay(10 * 1000); + udelay (10 * 1000); - check_hw_addr(bis); + check_hw_addr (bis); /* Reset the ethernet controller */ - OUTL(I82559_SELECTIVE_RESET, SCBPort); - udelay(20); + OUTL (I82559_SELECTIVE_RESET, SCBPort); + udelay (20); - OUTL(I82559_RESET, SCBPort); - udelay(20); + OUTL (I82559_RESET, SCBPort); + udelay (20); - if (!wait_for_eepro100()) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; + if (!wait_for_eepro100 ()) { + puts ("Error: Can not reset ethernet controller\n"); + return (status); } - OUTL(0, SCBPointer); - OUTW(SCB_M | RUC_ADDR_LOAD, SCBCmd); + OUTL (0, SCBPointer); + OUTW (SCB_M | RUC_ADDR_LOAD, SCBCmd); - if (!wait_for_eepro100()) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; + if (!wait_for_eepro100 ()) { + puts ("Error: Can not reset ethernet controller\n"); + return (status); } - OUTL(0, SCBPointer); - OUTW(SCB_M | CU_ADDR_LOAD, SCBCmd); + OUTL (0, SCBPointer); + OUTW (SCB_M | CU_ADDR_LOAD, SCBCmd); - /* Initialize Rx and Tx rings. - */ - init_rx_ring(); - purge_tx_ring(); + /* Initialize Rx and Tx rings. + */ + init_rx_ring (); + purge_tx_ring (); - /* Tell the adapter where the RX ring is located. - */ - if (!wait_for_eepro100()) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; + /* Tell the adapter where the RX ring is located. + */ + if (!wait_for_eepro100 ()) { + puts ("Error: Can not reset ethernet controller\n"); + return (status); } - OUTL((u32) &rx_ring[rx_next], SCBPointer); - OUTW(SCB_M | RUC_START, SCBCmd); + OUTL ((u32) & rx_ring[rx_next], SCBPointer); + OUTW (SCB_M | RUC_START, SCBCmd); - /* Send the Individual Address Setup frame - */ - tx_cur = tx_next; - tx_next = ((tx_next+1) % NUM_TX_DESC); + /* Send the Individual Address Setup frame + */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); - ias_cmd = (struct descriptor *)&tx_ring[tx_cur]; - ias_cmd->command = cpu_to_le16((CFG_CMD_SUSPEND | CFG_CMD_IAS)); - ias_cmd->status = 0; - ias_cmd->link = cpu_to_le32((u32) &tx_ring[tx_next]); + ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; + ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); + ias_cmd->status = 0; + ias_cmd->link = cpu_to_le32 ((u32) & tx_ring[tx_next]); - memcpy(ias_cmd->params, bis->bi_enetaddr, 6); + memcpy (ias_cmd->params, bis->bi_enetaddr, 6); - /* Tell the adapter where the TX ring is located. - */ - if (!wait_for_eepro100()) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; + /* Tell the adapter where the TX ring is located. + */ + if (!wait_for_eepro100 ()) { + puts ("Error: Can not reset ethernet controller\n"); + return (status); } - OUTL((u32) &tx_ring[tx_cur], SCBPointer); - OUTW(SCB_M | CU_START, SCBCmd); + OUTL ((u32) & tx_ring[tx_cur], SCBPointer); + OUTW (SCB_M | CU_START, SCBCmd); - for (i=0; !(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_C); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: Tx error buffer not ready\n"); - goto Done; + for (i = 0; + !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + puts ("eth: Tx error buffer not ready\n"); + return (status); } } - if (!(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_OK)) - { - printf("TX error status = 0x%08X\n", - le16_to_cpu(tx_ring[tx_cur].status)); + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); status++; } -Done: - return status; + return (status); } -int eth_send(volatile void *packet, int length) +int eth_send (volatile void *packet, int length) { int i, status = 0; int tx_cur; - if (length <= 0) - { - printf("eth: bad packet size: %d\n", length); - goto Done; + if (length <= 0) { + printf ("eth: bad packet size: %d\n", length); + return (status); } - tx_cur = tx_next; - tx_next = (tx_next+1) % NUM_TX_DESC; - - tx_ring[tx_cur].command = cpu_to_le16(TxCB_CMD_TRANSMIT | TxCB_CMD_SF | \ - TxCB_CMD_S | TxCB_CMD_EL); - tx_ring[tx_cur].status = 0; - tx_ring[tx_cur].count = cpu_to_le32(tx_threshold); - tx_ring[tx_cur].link = cpu_to_le32((u32) &tx_ring[tx_next]); - tx_ring[tx_cur].tx_desc_addr = cpu_to_le32((u32) &tx_ring[tx_cur].tx_buf_addr0); - tx_ring[tx_cur].tx_buf_addr0 = cpu_to_le32((u_long)packet); - tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32(length); - - if (!wait_for_eepro100()) - { - printf("eth: Tx error ethernet controller not ready.\n"); - goto Done; + tx_cur = tx_next; + tx_next = (tx_next + 1) % NUM_TX_DESC; + + tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | + TxCB_CMD_SF | + TxCB_CMD_S | + TxCB_CMD_EL); + tx_ring[tx_cur].status = 0; + tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); + tx_ring[tx_cur].link = cpu_to_le32 ((u32) & tx_ring[tx_next]); + tx_ring[tx_cur].tx_desc_addr = cpu_to_le32 ((u32) & tx_ring[tx_cur].tx_buf_addr0); + tx_ring[tx_cur].tx_buf_addr0 = cpu_to_le32 ((u_long) packet); + tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); + + if (!wait_for_eepro100 ()) { + puts ("eth: Tx error ethernet controller not ready\n"); + return (status); } /* Send the packet. */ - OUTL((u32) &tx_ring[tx_cur], SCBPointer); - OUTW(SCB_M | CU_START, SCBCmd); - - for(i = 0; !(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_C); i++) - { - if (i >= TOUT_LOOP) - { - printf("eth: Tx error buffer not ready\n"); - goto Done; + OUTL ((u32) & tx_ring[tx_cur], SCBPointer); + OUTW (SCB_M | CU_START, SCBCmd); + + for (i = 0; + !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + puts ("eth: Tx error buffer not ready\n"); + return (status); } } - if (!(le16_to_cpu(tx_ring[tx_cur].status) & CFG_STATUS_OK)) - { - printf("TX error status = 0x%08X\n", - le16_to_cpu(tx_ring[tx_cur].status)); + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); status++; } - Done: - return status; + return (status); } -int eth_rx(void) +int eth_rx (void) { u16 status, stat; int rx_prev, length = 0; - stat = INW(SCBStatus); - OUTW(stat & SCB_STATUS_RNR, SCBStatus); + stat = INW (SCBStatus); + OUTW (stat & SCB_STATUS_RNR, SCBStatus); - for ( ; ; ) - { - status = le16_to_cpu(rx_ring[rx_next].status); + for (;;) { + status = le16_to_cpu (rx_ring[rx_next].status); - if (!(status & RFD_STATUS_C)) - { + if (!(status & RFD_STATUS_C)) { break; } - /* Valid frame status. + /* Valid frame status. + */ + if ((status & RFD_STATUS_OK)) { + /* A valid frame received. */ - if ((status & RFD_STATUS_OK)) - { - /* A valid frame received. - */ - length = le32_to_cpu(rx_ring[rx_next].count) & 0x3fff; - - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(rx_ring[rx_next].data, length); - } - else - { - /* There was an error. - */ - printf("RX error status = 0x%08X\n", status); + length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive (rx_ring[rx_next].data, length); + } else { + /* There was an error. + */ + printf ("RX error status = 0x%08X\n", status); } - rx_ring[rx_next].control = cpu_to_le16(RFD_CONTROL_S); - rx_ring[rx_next].status = 0; - rx_ring[rx_next].count = cpu_to_le32(PKTSIZE_ALIGN << 16); + rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); + rx_ring[rx_next].status = 0; + rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); - rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; + rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; rx_ring[rx_prev].control = 0; /* Update entry information. @@ -485,131 +466,122 @@ int eth_rx(void) rx_next = (rx_next + 1) % NUM_RX_DESC; } - if (stat & SCB_STATUS_RNR) - { + if (stat & SCB_STATUS_RNR) { - printf("eth: Receiver is not ready, restart it !\n"); + puts ("eth: Receiver is not ready, restart it\n"); /* Reinitialize Rx ring. */ - init_rx_ring(); + init_rx_ring (); - if (!wait_for_eepro100()) - { - printf("Error: Can not restart ethernet controller.\n"); - goto Done; + if (!wait_for_eepro100 ()) { + puts ("Error: Can not restart ethernet controller\n"); + return (length); } - OUTL((u32) &rx_ring[rx_next], SCBPointer); - OUTW(SCB_M | RUC_START, SCBCmd); + OUTL ((u32) & rx_ring[rx_next], SCBPointer); + OUTW (SCB_M | RUC_START, SCBCmd); } - Done: - return length; + return (length); } -void eth_halt(void) +void eth_halt (void) { - if (!iobase) - { - goto Done; + if (!iobase) { + return; } /* Reset the ethernet controller */ - OUTL(I82559_SELECTIVE_RESET, SCBPort); - udelay(20); + OUTL (I82559_SELECTIVE_RESET, SCBPort); + udelay (20); - OUTL(I82559_RESET, SCBPort); - udelay(20); + OUTL (I82559_RESET, SCBPort); + udelay (20); - if (!wait_for_eepro100()) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; + if (!wait_for_eepro100 ()) { + puts ("Error: Can not reset ethernet controller\n"); + return; } - OUTL(0, SCBPointer); - OUTW(SCB_M | RUC_ADDR_LOAD, SCBCmd); + OUTL (0, SCBPointer); + OUTW (SCB_M | RUC_ADDR_LOAD, SCBCmd); - if (!wait_for_eepro100()) - { - printf("Error: Can not reset ethernet controller.\n"); - goto Done; + if (!wait_for_eepro100 ()) { + puts ("Error: Can not reset ethernet controller\n"); + return; } - OUTL(0, SCBPointer); - OUTW(SCB_M | CU_ADDR_LOAD, SCBCmd); + OUTL (0, SCBPointer); + OUTW (SCB_M | CU_ADDR_LOAD, SCBCmd); - Done: return; } /* SROM Read. */ -static int read_eeprom(long iobase, int location, int addr_len) +static int read_eeprom (long iobase, int location, int addr_len) { unsigned short retval = 0; int read_cmd = location | EE_READ_CMD; int i; - OUTW(EE_ENB & ~EE_CS, SCBeeprom); - OUTW(EE_ENB, SCBeeprom); + OUTW (EE_ENB & ~EE_CS, SCBeeprom); + OUTW (EE_ENB, SCBeeprom); /* Shift the read command bits out. */ - for (i = 12; i >= 0; i--) - { + for (i = 12; i >= 0; i--) { short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; - OUTW(EE_ENB | dataval, SCBeeprom); - udelay(1); - OUTW(EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); - udelay(1); + + OUTW (EE_ENB | dataval, SCBeeprom); + udelay (1); + OUTW (EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay (1); } - OUTW(EE_ENB, SCBeeprom); - - for (i = 15; i >= 0; i--) - { - OUTW(EE_ENB | EE_SHIFT_CLK, SCBeeprom); - udelay(1); - retval = (retval << 1) | - ((INW(SCBeeprom) & EE_DATA_READ) ? 1 : 0); - OUTW(EE_ENB, SCBeeprom); - udelay(1); + OUTW (EE_ENB, SCBeeprom); + + for (i = 15; i >= 0; i--) { + OUTW (EE_ENB | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + retval = (retval << 1) | + ((INW (SCBeeprom) & EE_DATA_READ) ? 1 : 0); + OUTW (EE_ENB, SCBeeprom); + udelay (1); } /* Terminate the EEPROM access. */ - OUTW(EE_ENB & ~EE_CS, SCBeeprom); + OUTW (EE_ENB & ~EE_CS, SCBeeprom); return retval; } -static void init_rx_ring(void) +static void init_rx_ring (void) { int i; - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].status = 0; - rx_ring[i].control = (i == NUM_RX_DESC-1) ? cpu_to_le16(RFD_CONTROL_S) : 0; - rx_ring[i].link = cpu_to_le32((u32) &rx_ring[(i+1) % NUM_RX_DESC]); + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = 0; + rx_ring[i].control = (i == NUM_RX_DESC - 1) ? + cpu_to_le16 (RFD_CONTROL_S) : 0; + rx_ring[i].link = cpu_to_le32 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]); rx_ring[i].rx_buf_addr = 0xffffffff; - rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16); + rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); } rx_next = 0; } -static void purge_tx_ring(void) +static void purge_tx_ring (void) { int i; - tx_next = 0; + tx_next = 0; tx_threshold = 0x01208000; - for (i = 0; i < NUM_TX_DESC; i++) - { - tx_ring[i].status = 0; - tx_ring[i].command = 0; - tx_ring[i].link = 0; + for (i = 0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].command = 0; + tx_ring[i].link = 0; tx_ring[i].tx_desc_addr = 0; - tx_ring[i].count = 0; + tx_ring[i].count = 0; tx_ring[i].tx_buf_addr0 = 0; tx_ring[i].tx_buf_size0 = 0; @@ -618,49 +590,46 @@ static void purge_tx_ring(void) } } -static void check_hw_addr(bd_t *bis) +static void check_hw_addr (bd_t * bis) { u16 eeprom[0x40]; u16 sum = 0; u8 hw_addr[ETH_ALEN]; int i, j; - int addr_len = read_eeprom(iobase, 0, 6) == 0xffff ? 8 : 6; + int addr_len = read_eeprom (iobase, 0, 6) == 0xffff ? 8 : 6; + + for (j = 0, i = 0; i < 0x40; i++) { + u16 value = read_eeprom (iobase, i, addr_len); - for (j = 0, i = 0; i < 0x40; i++) - { - u16 value = read_eeprom(iobase, i, addr_len); eeprom[i] = value; sum += value; - if (i < 3) - { + if (i < 3) { hw_addr[j++] = value; hw_addr[j++] = value >> 8; } } - if (sum != 0xBABA) - printf("eth: Invalid EEPROM checksum %#4.4x, " - "check settings before activating this device!\n", - sum); - - for (i=0;ibi_enetaddr[i]) - { - printf("Warning: HW address don't match:\n"); - printf("Address in SROM is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - printf("Address used by ppcboot is " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - bis->bi_enetaddr[0], bis->bi_enetaddr[1], - bis->bi_enetaddr[2], bis->bi_enetaddr[3], - bis->bi_enetaddr[4], bis->bi_enetaddr[5]); - goto Done; + if (sum != 0xBABA) { + printf ("eth: Invalid EEPROM checksum %#4.4x, " + "check settings before activating this device!\n", + sum); + } + + for (i = 0; i < ETH_ALEN; i++) { + if (hw_addr[i] != bis->bi_enetaddr[i]) { + printf ("Warning: HW address don't match:\n"); + printf ("Address in SROM is " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + hw_addr[0], hw_addr[1], hw_addr[2], + hw_addr[3], hw_addr[4], hw_addr[5]); + printf ("Address used by ppcboot is " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + bis->bi_enetaddr[0], bis->bi_enetaddr[1], + bis->bi_enetaddr[2], bis->bi_enetaddr[3], + bis->bi_enetaddr[4], bis->bi_enetaddr[5]); + return; } } -Done: return; } diff --git a/board/sandpoint/pci.h b/board/sandpoint/pci.h index 31f4cb4..daf9f8d 100644 --- a/board/sandpoint/pci.h +++ b/board/sandpoint/pci.h @@ -251,6 +251,7 @@ typedef int INT32; #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_82559ER 0x1209 #define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82559 0x1030 /* Cache Line Size - 32 32-bit value = 128 bytes */ #ifndef PCI_CACHE_LINE_SIZE diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index e365d13..d58baba 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -26,12 +26,20 @@ int checkboard (void) { - printf ("Sandpoint "); /*TODO: Check processor type */ - printf ("8240 Unity ##Test not implemented yet##\n"); + + puts ( "Sandpoint " +#ifdef CONFIG_MPC8240 + "8240" +#endif +#ifdef CONFIG_MPC8245 + "8245" +#endif + " Unity ##Test not implemented yet##\n"); return 0; } +#if 0 /* NOT USED */ int checkflash (void) { /* TODO: XXX XXX XXX */ @@ -39,6 +47,7 @@ int checkflash (void) return (0); } +#endif long int initdram (int board_type) { diff --git a/common/Makefile b/common/Makefile index ae5706e..9d10ea3 100644 --- a/common/Makefile +++ b/common/Makefile @@ -28,18 +28,16 @@ LIB = libcommon.a AOBJS = COBJS = board.o main.o command.o environment.o bedbug.o \ cmd_autoscript.o cmd_bedbug.o cmd_boot.o \ - cmd_bootm.o cmd_cache.o cmd_console.o \ - cmd_date.o cmd_dcr.o cmd_eeprom.o cmd_elf.o \ - cmd_fdc.o cmd_flash.o cmd_i2c.o \ - cmd_ide.o cmd_immap.o cmd_mem.o \ - cmd_mii.o cmd_misc.o cmd_net.o \ - cmd_nvedit.o cmd_pcmcia.o \ - cmd_reginfo.o cmd_scsi.o cmd_doc.o \ - console.o devices.o dlmalloc.o \ - usb.o usb_storage.o usb_kbd.o cmd_usb.o \ - flash.o hush.o kgdb.o \ - lists.o miiphybb.o miiphyutil.o \ - s_record.o docecc.o + cmd_bootm.o cmd_cache.o cmd_console.o cmd_date.o \ + cmd_dcr.o cmd_doc.o cmd_eeprom.o cmd_elf.o \ + cmd_fdc.o cmd_flash.o cmd_i2c.o cmd_ide.o \ + cmd_immap.o cmd_jffs2.o cmd_mem.o cmd_mii.o \ + cmd_misc.o cmd_net.o cmd_nvedit.o cmd_pcmcia.o \ + cmd_reginfo.o cmd_scsi.o cmd_usb.o \ + console.o devices.o dlmalloc.o docecc.o \ + flash.o hush.o kgdb.o lists.o \ + miiphybb.o miiphyutil.o s_record.o \ + usb.o usb_kbd.o usb_storage.o OBJS = $(AOBJS) $(COBJS) @@ -47,8 +45,8 @@ CPPFLAGS += -I.. all: $(LIB) $(AOBJS) -$(LIB): .depend $(COBJS) - $(AR) crv $@ $(COBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) environment.o: environment.c ../tools/envcrc $(CC) $(AFLAGS) -Wa,--no-warn \ diff --git a/common/board.c b/common/board.c index d9985a0..9da899f 100644 --- a/common/board.c +++ b/common/board.c @@ -405,7 +405,7 @@ board_init_f (ulong bootflag) i = getenv_r ("ethaddr", tmp, sizeof(tmp)); s = (i > 0) ? tmp : NULL; -#ifdef CONFIG_MBX +#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) if (s == NULL) board_get_enetaddr(bd->bi_enetaddr); else diff --git a/common/cmd_doc.c b/common/cmd_doc.c index f743d6d..acb3925 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -232,7 +232,7 @@ int do_docboot (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) cnt = (hdr->ih_size + sizeof(image_header_t)); cnt -= SECTORSIZE; } else { - printf("\n** Bad Magic Number **\n"); + puts ("\n** Bad Magic Number **\n"); SHOW_BOOT_PROGRESS (-1); return 1; } @@ -322,7 +322,7 @@ void doc_print(struct DiskOnChip *this) { flash_size > (1 << 20) ? flash_size >> 20 : flash_size >> 10, flash_size > (1 << 20) ? "MB" : "kB", bin_size); } else { - printf("\t No NFTL boot record found.\n"); + puts ("\t No NFTL boot record found.\n"); } } @@ -355,7 +355,7 @@ static int _DoC_WaitReady(struct DiskOnChip *doc) unsigned long start = get_timer(0); #ifdef PSYCHO_DEBUG - printf("_DoC_WaitReady called for out-of-line wait\n"); + puts ("_DoC_WaitReady called for out-of-line wait\n"); #endif /* Out-of-line routine to wait for chip response */ @@ -369,7 +369,7 @@ static int _DoC_WaitReady(struct DiskOnChip *doc) } #else if (get_timer(start) > 10 * 1000) { - printf("_DoC_WaitReady timed out.\n"); + puts ("_DoC_WaitReady timed out.\n"); return DOC_ETIMEOUT; } #endif @@ -717,14 +717,14 @@ static void DoC_ScanChips(struct DiskOnChip *this) /* If there are none at all that we recognise, bail */ if (!this->numchips) { - printf("No flash chips recognised.\n"); + puts ("No flash chips recognised.\n"); return; } /* Allocate an array to hold the information for each chip */ this->chips = malloc(sizeof(struct Nand) * this->numchips); if (!this->chips) { - printf("No memory for allocating chip info structures\n"); + puts ("No memory for allocating chip info structures\n"); return; } @@ -782,7 +782,7 @@ static int find_boot_record(struct NFTLrecord *nftl) if (warncount) { printf("Block read at 0x%x failed\n", block * nftl->EraseSize); if (!--warncount) - printf("Further failures for this block will not be printed\n"); + puts ("Further failures for this block will not be printed\n"); } continue; } @@ -834,24 +834,26 @@ static int find_boot_record(struct NFTLrecord *nftl) /* Do some sanity checks on it */ if (mh->UnitSizeFactor != 0xff) { - printf("Sorry, we don't support UnitSizeFactor " - "of != 1 yet.\n"); + puts ("Sorry, we don't support UnitSizeFactor " + "of != 1 yet.\n"); return -1; } nftl->nb_boot_blocks = le16_to_cpu(mh->FirstPhysicalEUN); if ((nftl->nb_boot_blocks + 2) >= nftl->nb_blocks) { - printf("NFTL Media Header sanity check failed:\n"); - printf("nb_boot_blocks (%d) + 2 > nb_blocks (%d)\n", - nftl->nb_boot_blocks, nftl->nb_blocks); + printf ("NFTL Media Header sanity check failed:\n" + "nb_boot_blocks (%d) + 2 > nb_blocks (%d)\n", + nftl->nb_boot_blocks, nftl->nb_blocks); return -1; } nftl->numvunits = le32_to_cpu(mh->FormattedSize) / nftl->EraseSize; if (nftl->numvunits > (nftl->nb_blocks - nftl->nb_boot_blocks - 2)) { - printf("NFTL Media Header sanity check failed:\n"); - printf("numvunits (%d) > nb_blocks (%d) - nb_boot_blocks(%d) - 2\n", - nftl->numvunits, nftl->nb_blocks, nftl->nb_boot_blocks); + printf ("NFTL Media Header sanity check failed:\n" + "numvunits (%d) > nb_blocks (%d) - nb_boot_blocks(%d) - 2\n", + nftl->numvunits, + nftl->nb_blocks, + nftl->nb_boot_blocks); return -1; } @@ -868,7 +870,7 @@ static int find_boot_record(struct NFTLrecord *nftl) if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize + i + SECTORSIZE, SECTORSIZE, &retlen, buf, (char *)&oob)) < 0) { - printf("Read of bad sector table failed\n"); + puts ("Read of bad sector table failed\n"); return -1; } } @@ -949,7 +951,7 @@ int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len, /* Don't allow read past end of device */ if (from >= this->totlen) { - printf("Out of flash\n"); + puts ("Out of flash\n"); return DOC_EINVAL; } @@ -1089,7 +1091,7 @@ int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len, /* Don't allow write past end of device */ if (to >= this->totlen) { - printf("Out of flash\n"); + puts ("Out of flash\n"); return DOC_EINVAL; } @@ -1151,7 +1153,7 @@ int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len, DoC_Delay(this, 2); if (ReadDOC_(docptr, this->ioreg) & 1) { - printf("Error programming flash\n"); + puts ("Error programming flash\n"); /* Error in programming */ *retlen = 0; return DOC_EIO; @@ -1203,7 +1205,7 @@ int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len, DoC_Delay(this, 2); if (ReadDOC_(docptr, this->ioreg) & 1) { - printf("Error programming flash\n"); + puts ("Error programming flash\n"); /* Error in programming */ *retlen = 0; return DOC_EIO; @@ -1349,7 +1351,7 @@ int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len, DoC_Delay(this, 2); if (ReadDOC_(docptr, this->ioreg) & 1) { - printf("Error programming oob data\n"); + puts ("Error programming oob data\n"); /* There was an error */ *retlen = 0; return DOC_EIO; @@ -1368,7 +1370,7 @@ int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len, DoC_Delay(this, 2); if (ReadDOC_(docptr, this->ioreg) & 1) { - printf("Error programming oob data\n"); + puts ("Error programming oob data\n"); /* There was an error */ *retlen = 0; return DOC_EIO; @@ -1386,7 +1388,7 @@ int doc_erase(struct DiskOnChip* this, loff_t ofs, size_t len) struct Nand *mychip; if (ofs & (this->erasesize-1) || len & (this->erasesize-1)) { - printf("Offset and size must be sector aligned\n"); + puts ("Offset and size must be sector aligned\n"); return DOC_EINVAL; } @@ -1487,8 +1489,14 @@ static inline int doccheck(unsigned long potential, unsigned long physadr) default: #ifndef CFG_DOCPROBE_55AA +/* + * if the ID isn't the DoC2000 or DoCMillenium ID, so we can assume + * the DOC is missing + */ +# if 0 printf("Possible DiskOnChip with unknown ChipID %2.2X found at 0x%lx\n", ChipID, physadr); +# endif #endif #ifndef DOC_PASSIVE_PROBE /* Put back the contents of the DOCControl register, in case it's not @@ -1499,14 +1507,14 @@ static inline int doccheck(unsigned long potential, unsigned long physadr) return 0; } - printf("DiskOnChip failed TOGGLE test, dropping.\n"); + puts ("DiskOnChip failed TOGGLE test, dropping.\n"); #ifndef DOC_PASSIVE_PROBE /* Put back the contents of the DOCControl register: it's not a DiskOnChip */ WriteDOC(tmp2, window, DOCControl); #endif return 0; -} +} void doc_probe(unsigned long physadr) { @@ -1523,7 +1531,7 @@ void doc_probe(unsigned long physadr) } if (!this) { - printf("Cannot allocate memory for data structures.\n"); + puts ("Cannot allocate memory for data structures.\n"); return; } @@ -1537,6 +1545,8 @@ void doc_probe(unsigned long physadr) this->ChipID = ChipID; DoC2k_init(this); + } else { + puts ("No DiskOnChip found\n"); } } diff --git a/common/cmd_elf.c b/common/cmd_elf.c index ea22e3a..9c91179 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -147,7 +147,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) if ((bootline = getenv ("bootargs")) != NULL) { memcpy ((void *) bootaddr, bootline, MAX(strlen(bootline), 255)); - flush_cache ((void *)bootaddr, MAX(strlen(bootline), 255)); + flush_cache (bootaddr, MAX(strlen(bootline), 255)); } else { #if defined(CONFIG_4xx) sprintf (build_buf, "ibmEmac(0,0)"); @@ -165,7 +165,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) "e=%s ", tmp); } memcpy ((void *)bootaddr, build_buf, MAX(strlen(build_buf), 255)); - flush_cache ((void *)bootaddr, MAX(strlen(build_buf), 255)); + flush_cache (bootaddr, MAX(strlen(build_buf), 255)); #elif defined(CONFIG_IOP480) sprintf (build_buf, "dc(0,0)"); @@ -182,7 +182,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) "e=%s ", tmp); } memcpy ((void *) bootaddr, build_buf, MAX(strlen(build_buf), 255)); - flush_cache ((void *)bootaddr, MAX(strlen(build_buf), 255)); + flush_cache (bootaddr, MAX(strlen(build_buf), 255)); #else /* @@ -282,22 +282,28 @@ unsigned long load_elf_image (unsigned long addr) (i * sizeof (Elf32_Shdr))); if (!(shdr->sh_flags & SHF_ALLOC) - || shdr->sh_type == SHT_NOBITS || shdr->sh_addr == 0 || shdr->sh_size == 0) { continue; } if (strtab) { - printf ("Loading %s @ 0x%08lx (%ld bytes)\n", + printf ("%sing %s @ 0x%08lx (%ld bytes)\n", + (shdr->sh_type == SHT_NOBITS) ? + "Clear" : "Load", &strtab[shdr->sh_name], (unsigned long) shdr->sh_addr, (long) shdr->sh_size); } - - image = (unsigned char *) addr + shdr->sh_offset; - memcpy ((void *) shdr->sh_addr, (const void *) image, + + if (shdr->sh_type == SHT_NOBITS) { + memset ((void *)shdr->sh_addr, 0, shdr->sh_size); + } else { + image = (unsigned char *) addr + shdr->sh_offset; + memcpy ((void *) shdr->sh_addr, + (const void *) image, shdr->sh_size); - flush_cache ((void *)shdr->sh_addr, shdr->sh_size); + } + flush_cache (shdr->sh_addr, shdr->sh_size); } return ehdr->e_entry; diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c new file mode 100644 index 0000000..7dba497 --- /dev/null +++ b/common/cmd_jffs2.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + +static void +get_part_info(struct part_info *part) +{ + extern flash_info_t flash_info[]; /* info for FLASH chips */ + int i; + + memset(part, 0, sizeof(*part)); + part->offset = (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[0]; + + /* Figure out flash partition size */ + for (i = CFG_JFFS2_FIRST_BANK; i < CFG_JFFS2_NUM_BANKS+CFG_JFFS2_FIRST_BANK; i++) + part->size += flash_info[i].size; + + /* unused in current jffs2 loader */ + part->erasesize = 0; +} + +int +do_jffs2_fsload(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + struct part_info part; + char *filename = "vmlinuz"; + ulong offset = CFG_LOAD_ADDR; + int size; + + if (argc >= 2) { + offset = simple_strtoul(argv[1], NULL, 16); + } + if (argc == 3) { + filename = argv[2]; + } + + get_part_info(&part); + + printf("### JFFS2 loading '%s' to 0x%lx\n", filename, offset); + size = jffs2_1pass_load((char *)offset, &part, filename); + + if (size > 0) { + printf("### JFFS2 load compleate: %d bytes loaded to 0x%lx\n", + size, offset); + } else { + printf("### JFFS2 LOAD ERROR<%x> for %s!\n", size, filename); + } + return !(size > 0); +} + +int +do_jffs2_ls(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + struct part_info part; + char *filename = "/"; + int ret; + + if (argc == 2) + filename = argv[1]; + + get_part_info(&part); + ret = jffs2_1pass_ls(&part, filename); + + return (ret == 1); +} + +int +do_jffs2_fsinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + struct part_info part; + int ret; + + get_part_info(&part); + ret = jffs2_1pass_info(&part); + + return (ret == 1); +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 9b2047e..a387ad4 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -152,6 +152,8 @@ static uchar *flash_addr = (uchar *)CFG_ENV_ADDR; # endif /* ENV, FLASH */ # endif /* ENV_IS_EMBEDDED */ +#else +# error Define one of CFG_ENV_IS_IN_NVRAM, CFG_ENV_IS_IN_EEPROM, CFG_ENV_IS_IN_FLASH #endif /* CFG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------*/ diff --git a/common/command.c b/common/command.c index 9bb0ad7..946d519 100644 --- a/common/command.c +++ b/common/command.c @@ -48,18 +48,19 @@ #include #include +#include #include /* Floppy support */ #include /* USB support */ #include #include #include /* 4xx DCR register access */ #include +#include #include /* board special functions */ #include -#include /* * HELP command @@ -254,6 +255,7 @@ cmd_tbl_t cmd_tbl[] = { CMD_TBL_IMINFO CMD_TBL_IOPINFO CMD_TBL_IRQINFO + CMD_TBL_JFFS2 CMD_TBL_KGDB CMD_TBL_LOADB CMD_TBL_LOADS diff --git a/config.mk b/config.mk index 3bdcdf6..29b8b48 100644 --- a/config.mk +++ b/config.mk @@ -102,7 +102,8 @@ else CFLAGS := $(CPPFLAGS) -Wall -Wno-uninitialized -Wstrict-prototypes endif -AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) +AFLAGS_DEBUG := -Wa,--gstabs +AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) # $(AFLAGS_DEBUG) LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) diff --git a/cpu/74xx_7xx/Makefile b/cpu/74xx_7xx/Makefile index fc29c33..f913c6d 100644 --- a/cpu/74xx_7xx/Makefile +++ b/cpu/74xx_7xx/Makefile @@ -25,18 +25,19 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a -START = start.o kgdb.o io.o +START = start.o +ASOBJS = kgdb.o io.o OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o -all: .depend $(START) $(LIB) +all: .depend $(START) $(ASOBJS) $(LIB) $(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) kgdb.o io.o + $(AR) crv $@ $(ASOBJS) $(OBJS) ######################################################################### .depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ sinclude .depend diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index 11000bc..7df519e 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -88,37 +88,44 @@ checkcpu(long clock) { uint type = get_cpu_type(); uint pvr = get_pvr(); + char buf[32]; + char *str; switch (type) { + case CPU_750CX: + printf ("750CX(e) v2.%d", pvr & 0xf); + goto PR_CLK; + case CPU_750: - printf ("750 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); - return (0); + str = "750"; + break; case CPU_755: - printf ("755 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); - return (0); - - case CPU_750CX: - printf ("750CX(e) v2.%d\n", pvr & 0xf); - return (0); + str = "755"; + break; case CPU_7400: - printf ("MPC7400 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); - return (0); + str = "MPC7400"; + break; case CPU_7410: - printf ("MPC7410 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); - return (0); + str = "MPC7410"; + break; case CPU_7450: - printf ("MPC7450 v%d.%d\n", (pvr >> 8) & 0xFF, pvr & 0xFF); - return (0); + str = "MPC7450"; + break; default: printf("Unknown CPU -- PVR: 0x%08x\n", pvr); return -1; } + printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF); +PR_CLK: + printf (" @ %s MHz\n", strmhz(buf, get_gclk_freq())); + + return (0); } /* these two functions are unimplemented currently [josh] */ diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c index 8ac5721..96f0cf0 100644 --- a/cpu/74xx_7xx/cpu_init.c +++ b/cpu/74xx_7xx/cpu_init.c @@ -30,21 +30,6 @@ #include #include <74xx_7xx.h> -__inline__ unsigned long -get_hid0(void) -{ - unsigned long msr; - - asm volatile("mfspr %0, 1008" : "=r" (msr) :); - return msr; -} - -__inline__ void -set_hid0(unsigned long msr) -{ - asm volatile("mtspr 1008, %0" : : "r" (msr)); -} - /* * Breath some life into the CPU... * diff --git a/cpu/74xx_7xx/interrupts.c b/cpu/74xx_7xx/interrupts.c index 723b44f..ed4dd94 100644 --- a/cpu/74xx_7xx/interrupts.c +++ b/cpu/74xx_7xx/interrupts.c @@ -149,6 +149,8 @@ timer_interrupt(struct pt_regs *regs) #if defined(CONFIG_WATCHDOG) if ((timestamp % (CFG_HZ / 2)) == 0) { #if defined(CONFIG_PCIPPC2) + extern void pcippc2_wdt_reset (void); + pcippc2_wdt_reset(); #endif } diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index 03bdca5..94e5215 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -25,22 +25,6 @@ #include <74xx_7xx.h> #include -/* Access functions for the Machine State Register */ -static __inline__ unsigned long -get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void -set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - /* ------------------------------------------------------------------------- */ /* diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index ccf5b34..f648910 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -34,13 +34,16 @@ void cpu_init_f (void) { -/* MOUSSE and MUSENKI and boards initialized in asm */ -#if (!defined(CONFIG_MOUSSE) && \ - !defined(CONFIG_MUSENKI)) +/* MOUSSE board is initialized in asm */ +#if !defined(CONFIG_MOUSSE) register unsigned long val; CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ +#if defined(CONFIG_MUSENKI) + CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); /* enable on-chip PCI arbitration */ +#endif + CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ /* @@ -122,14 +125,18 @@ cpu_init_f (void) (CFG_SDMODE_BURSTLEN)) <> 6) <> 6) <im_cpm.cp_rccr = CFG_RCCR; diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index b71431e..62ec328 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -288,6 +288,7 @@ i2c_newio(i2c_state_t *state) state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase]; state->tx_space = MAX_TX_SPACE; state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); + state->err_cb = NULL; PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 0fa72e3..f46e030 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -454,6 +454,11 @@ int eth_init(bd_t *bis) immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; #endif /* AMX860 */ +#ifdef CONFIG_RPXCLASSIC + *((uchar *)BCSR0) &= ~BCSR0_ETHLPBK; + *((uchar *)BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); +#endif + #ifdef CONFIG_RPXLITE *((uchar *)BCSR0) |= BCSR0_ETHEN ; #endif @@ -473,7 +478,7 @@ int eth_init(bd_t *bis) */ #if defined (CONFIG_FADS) udelay(10000); /* wait 10 ms */ -#elif defined (CONFIG_AMX860) +#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) udelay(100000); /* wait 100 ms */ #endif diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 19971c4..6580166 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -145,7 +145,7 @@ serial_init (ulong cpu_clock, int baudrate) #endif #endif /* CONFIG_FADS */ -#if defined(CONFIG_RPXLITE) +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) /* Enable Monitor Port Transceiver */ *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; #endif /* CONFIG_RPXLITE */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index aa2b38f..c3b042a 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -59,16 +59,9 @@ void i2c_init(void) get_sys_info (&sysInfo); freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; /* set divisor according to freqOPB */ - if (freqOPB <= 20000000) - divisor = 0x1; - else if (freqOPB <= 30000000) - divisor = 0x2; - else if (freqOPB <= 40000000) - divisor = 0x3; - else if (freqOPB <= 50000000) - divisor = 0x4; - else - divisor = 0x5; + divisor = freqOPB / 10000000; + if (divisor == 0) + divisor = 1; out8(IIC_CLKDIV,divisor); __asm__ volatile("eieio"); @@ -274,7 +267,7 @@ int i2c_send(unsigned char address, int i2c_read (uchar *addr, int alen, uchar *buffer, int len) { int rcode = 0; - + if ((alen < 1) || (alen > 3)) { printf ("I2C read: addr len %d not supported\n", alen); return 1; @@ -337,7 +330,7 @@ int i2c_write (uchar *addr, int alen, uchar *buffer, int len) if (alen == 2) { /* fill in address first */ - wbuffer[0] = addr[1]; + wbuffer[0] = addr[1]; for (i=1; i < len+1; i++) { wbuffer[i] = *buffer++; /* copy data */ } @@ -349,8 +342,8 @@ int i2c_write (uchar *addr, int alen, uchar *buffer, int len) } if (alen == 3) { /* fill in the address first */ - wbuffer[0] = addr[1]; - wbuffer[1] = addr[2]; + wbuffer[0] = addr[1]; + wbuffer[1] = addr[2]; for (i=2; i < len+2; i++) { wbuffer[i] = *buffer++; /* copy data */ } diff --git a/doc/README.RPXClassic b/doc/README.RPXClassic new file mode 100644 index 0000000..d650037 --- /dev/null +++ b/doc/README.RPXClassic @@ -0,0 +1,21 @@ +# Porting PPCboot onto RPXClassic LF_BW31 board +# Written by Pierre AUBERT +# E-Mail p.aubert@staubli.com +# Stäubli Faverges - +# +# Sept. 20 2001 +# +# Cross compile: Montavista Hardhat ported on HP-UX 10.20 +# + +Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 +DRAM : 16 Mb from 0 +NVRAM : 512 kb from 0xfa000000 + + +- environment is stored in NVRAM +- Mac address is read from EEPROM +- ethernet on SCC1 or fast ethernet on FEC are running (depending on the + configuration flag CONFIG_FEC_ENET) + + diff --git a/fs/Makefile b/fs/Makefile new file mode 100644 index 0000000..3e53c96 --- /dev/null +++ b/fs/Makefile @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# + +SUBDIRS := jffs2 + +.depend all: + @for dir in $(SUBDIRS) ; do \ + $(MAKE) -C $$dir $@ ; done + diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile new file mode 100644 index 0000000..51189e8 --- /dev/null +++ b/fs/jffs2/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libjffs2.a + +AOBJS = +COBJS = jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o +OBJS = $(AOBJS) $(COBJS) + +#CPPFLAGS += + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/jffs2/compr_rtime.c b/fs/jffs2/compr_rtime.c new file mode 100644 index 0000000..3e68312 --- /dev/null +++ b/fs/jffs2/compr_rtime.c @@ -0,0 +1,91 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by Arjan van de Ven + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: compr_rtime.c,v 1.2 2002/01/24 22:58:42 rfeany Exp $ + * + * + * Very simple lz77-ish encoder. + * + * Theory of operation: Both encoder and decoder have a list of "last + * occurances" for every possible source-value; after sending the + * first source-byte, the second byte indicated the "run" length of + * matches + * + * The algorithm is intended to only send "whole bytes", no bit-messing. + * + */ + +#include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include + +void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen) +{ + int positions[256]; + int outpos; + int pos; + int i; + + outpos = pos = 0; + + for (i = 0; i < 256; positions[i++] = 0); + + while (outpos= outpos) { + while(repeat) { + cpage_out[outpos++] = cpage_out[backoffs++]; + repeat--; + } + } else { + for (i = 0; i < repeat; i++) + *(cpage_out + outpos + i) = *(cpage_out + backoffs + i); + outpos+=repeat; + } + } + } +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/compr_rubin.c b/fs/jffs2/compr_rubin.c new file mode 100644 index 0000000..4d9842c --- /dev/null +++ b/fs/jffs2/compr_rubin.c @@ -0,0 +1,124 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by Arjan van de Ven + * + * Heavily modified by Russ Dill in an attempt at + * a little more speed. + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: compr_rubin.c,v 1.2 2002/01/24 22:58:42 rfeany Exp $ + * + */ + +#include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + + +void rubin_do_decompress(unsigned char *bits, unsigned char *in, + unsigned char *page_out, __u32 destlen) +{ + register char *curr = page_out; + char *end = page_out + destlen; + register unsigned long temp; + register unsigned long result; + register unsigned long p; + register unsigned long q; + register unsigned long rec_q; + register unsigned long bit; + register long i0; + unsigned long i; + + /* init_pushpull */ + temp = *(u32 *) in; + bit = 16; + + /* init_rubin */ + q = 0; + p = (long) (2 * UPPER_BIT_RUBIN); + + /* init_decode */ + rec_q = (in[0] << 8) | in[1]; + + while (curr < end) { + /* in byte */ + + result = 0; + for (i = 0; i < 8; i++) { + /* decode */ + + while ((q & UPPER_BIT_RUBIN) || ((p + q) <= UPPER_BIT_RUBIN)) { + q &= ~UPPER_BIT_RUBIN; + q <<= 1; + p <<= 1; + rec_q &= ~UPPER_BIT_RUBIN; + rec_q <<= 1; + rec_q |= (temp >> (bit++ ^ 7)) & 1; + if (bit > 31) { + bit = 0; + temp = *(++((u32 *) in)); + } + } + i0 = (bits[i] * p) >> 8; + + if (i0 <= 0) i0 = 1; + /* if it fails, it fails, we have our crc + if (i0 >= p) i0 = p - 1; */ + + result >>= 1; + if (rec_q < q + i0) { + /* result |= 0x00; */ + p = i0; + } else { + result |= 0x80; + p -= i0; + q += i0; + } + } + *(curr++) = result; + } +} + +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen) +{ + unsigned char bits[8]; + int c; + + for (c=0; c<8; c++) + bits[c] = (256 - data_in[c]); + + rubin_do_decompress(bits, data_in+8, cpage_out, dstlen); +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c new file mode 100644 index 0000000..7e4dfa4 --- /dev/null +++ b/fs/jffs2/compr_zlib.c @@ -0,0 +1,52 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: compr_zlib.c,v 1.2 2002/01/24 22:58:42 rfeany Exp $ + * + */ + +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + +long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, + __u32 srclen, __u32 destlen) +{ + return (decompress_block(cpage_out, data_in + 2, ldr_memcpy)); + +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c new file mode 100644 index 0000000..ebdea89 --- /dev/null +++ b/fs/jffs2/jffs2_1pass.c @@ -0,0 +1,979 @@ +/* +------------------------------------------------------------------------- + * Filename: jffs2.c + * Version: $Id: jffs2_1pass.c,v 1.7 2002/01/25 01:56:47 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Module to load kernel from jffs2 + *-----------------------------------------------------------------------*/ +/* + * some portions of this code are taken from jffs2, and as such, the + * following copyright notice is included. + * + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: jffs2_1pass.c,v 1.7 2002/01/25 01:56:47 nyet Exp $ + * + */ + +/* Ok, so anyone who knows the jffs2 code will probably want to get a papar + * bag to throw up into before reading this code. I looked through the jffs2 + * code, the caching scheme is very elegant. I tried to keep the version + * for a bootloader as small and simple as possible. Instead of worring about + * unneccesary data copies, node scans, etc, I just optimized for the known + * common case, a kernel, which looks like: + * (1) most pages are 4096 bytes + * (2) version numbers are somewhat sorted in acsending order + * (3) multiple compressed blocks making up one page is uncommon + * + * So I create a linked list of decending version numbers (insertions at the + * head), and then for each page, walk down the list, until a matching page + * with 4096 bytes is found, and then decompress the watching pages in + * reverse order. + * + */ + +/* + * Adapted by Nye Liu and + * Rex Feany + * on Jan/2002 for ppcboot. + * + * Clipped out all the non-1pass functions, cleaned up warnings, + * wrappers, etc. No major changes to the code. + * Please, he really means it when he said have a paper bag + * handy. We needed it ;). + * + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + +#include "jffs2_private.h" + +/* Compression names */ +static char *compr_names[] = { + "NONE", + "ZERO", + "RTIME", + "RUBINMIPS", + "COPY", + "DYNRUBIN", + "ZLIB" }; + +static char spinner[] = { '|', '\\', '-', '/' }; + +static struct b_lists g_1PassList; + +#define DEBUG(x...) +#define MALLOC_CHUNK (10*1024) + + +static struct b_node * +add_node(struct b_node *tail, u32 * count, u32 * memBase) +{ + u32 index; + u32 memLimit; + struct b_node *b; + + index = (*count) * sizeof(struct b_node) % MALLOC_CHUNK; + memLimit = MALLOC_CHUNK; + +#if 0 + putLabeledWord("add_node: index = ", index); + putLabeledWord("add_node: memLimit = ", memLimit); + putLabeledWord("add_node: memBase = ", *memBase); +#endif + + // we need not keep a list of bases since we'll never free the + // memory, just jump the the kernel + if ((index == 0) || (index > memLimit)) { // we need mode space before we continue + if ((*memBase = (u32) mmalloc(MALLOC_CHUNK)) == (u32) NULL) { + putstr("add_node: malloc failed\n"); + return NULL; + } +#if 0 + putLabeledWord("add_node: alloced a new membase at ", *memBase); +#endif + + } + // now we have room to add it. + b = (struct b_node *) (*memBase + index); + + // null on first call + if (tail) + tail->next = b; + +#if 0 + putLabeledWord("add_node: tail = ", (u32) tail); + if (tail) + putLabeledWord("add_node: tail->next = ", (u32) tail->next); + +#endif + +#if 0 + putLabeledWord("add_node: mb+i = ", (u32) (*memBase + index)); + putLabeledWord("add_node: b = ", (u32) b); +#endif + (*count)++; + b->next = (struct b_node *) NULL; + return b; + +} + +// we know we have empties at the start offset so we will hop +// t points that would be non F if there were a node here to speed this up. +struct jffs2_empty_node { + u32 first; + u32 second; +}; + +static u32 +jffs2_scan_empty(u32 start_offset, struct part_info *part) +{ + u32 max = part->size - sizeof(struct jffs2_raw_inode); + + // this would be either dir node_crc or frag isize + u32 offset = start_offset + 32; + struct jffs2_empty_node *node; + + start_offset += 4; + while (offset < max) { + node = (struct jffs2_empty_node *) (part->offset + offset); + if ((node->first == 0xFFFFFFFF) && (node->second == 0xFFFFFFFF)) { + // we presume that there were no nodes in between and advance in a hop + // putLabeledWord("\t\tjffs2_scan_empty: empty at offset=",offset); + start_offset = offset + 4; + offset = start_offset + 32; // orig 32 + 4 bytes for the second==0xfffff + } else { + return start_offset; + } + } + return start_offset; +} + +static u32 +jffs_init_1pass_list(void) +{ + g_1PassList.dirListHead = g_1PassList.dirListTail = NULL; + g_1PassList.fragListHead = g_1PassList.fragListTail = NULL; + g_1PassList.dirListCount = 0; + g_1PassList.dirListMemBase = 0; + g_1PassList.fragListCount = 0; + g_1PassList.fragListMemBase = 0; + g_1PassList.partOffset = 0x0; + + return 0; +} + +// find the inode from the slashless name given a parent +static long +jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest) +{ + struct b_node *b; + struct jffs2_raw_inode *jNode; + u32 totalSize = 1; + u32 oldTotalSize = 0; + u32 size = 0; + char *lDest = (char *) dest; + char *src; + long ret; + int i; + u32 counter = 0; + char totalSizeSet = 0; + +#if 0 + b = pL->fragListHead; + while (b) { + jNode = (struct jffs2_raw_inode *) (b->offset); + if ((inode == jNode->ino)) { + putLabeledWord("\r\n\r\nread_inode: totlen = ", jNode->totlen); + putLabeledWord("read_inode: inode = ", jNode->ino); + putLabeledWord("read_inode: version = ", jNode->version); + putLabeledWord("read_inode: isize = ", jNode->isize); + putLabeledWord("read_inode: offset = ", jNode->offset); + putLabeledWord("read_inode: csize = ", jNode->csize); + putLabeledWord("read_inode: dsize = ", jNode->dsize); + putLabeledWord("read_inode: compr = ", jNode->compr); + putLabeledWord("read_inode: usercompr = ", jNode->usercompr); + putLabeledWord("read_inode: flags = ", jNode->flags); + } + + b = b->next; + } + +#endif + +#if 1 + b = pL->fragListHead; + while (b && (size < totalSize)) { + jNode = (struct jffs2_raw_inode *) (b->offset); + if ((inode == jNode->ino)) { + if ((jNode->isize == oldTotalSize) && (jNode->isize > totalSize)) { + // 2 consecutive isizes indicate file length + totalSize = jNode->isize; + totalSizeSet = 1; + } else if (!totalSizeSet) { + totalSize = size + jNode->dsize + 1; + } + oldTotalSize = jNode->isize; + + if(dest) { + src = ((char *) jNode) + sizeof(struct jffs2_raw_inode); + // lDest = (char *) (dest + (jNode->offset & ~3)); + lDest = (char *) (dest + jNode->offset); +#if 0 + putLabeledWord("\r\n\r\nread_inode: src = ", src); + putLabeledWord("read_inode: dest = ", lDest); + putLabeledWord("read_inode: dsize = ", jNode->dsize); + putLabeledWord("read_inode: csize = ", jNode->csize); + putLabeledWord("read_inode: version = ", jNode->version); + putLabeledWord("read_inode: isize = ", jNode->isize); + putLabeledWord("read_inode: offset = ", jNode->offset); + putLabeledWord("read_inode: compr = ", jNode->compr); + putLabeledWord("read_inode: flags = ", jNode->flags); +#endif + switch (jNode->compr) { + case JFFS2_COMPR_NONE: +#if 0 + { + int i; + + if ((dest > 0xc0092ff0) && (dest < 0xc0093000)) + for (i = 0; i < first->length; i++) { + putLabeledWord("\tCOMPR_NONE: src =", src + i); + putLabeledWord("\tCOMPR_NONE: length =", first->length); + putLabeledWord("\tCOMPR_NONE: dest =", dest + i); + putLabeledWord("\tCOMPR_NONE: data =", (unsigned char) *(src + i)); + } + } +#endif + + ret = (unsigned long) ldr_memcpy(lDest, src, jNode->dsize); + break; + case JFFS2_COMPR_ZERO: + ret = 0; + for (i = 0; i < jNode->dsize; i++) + *(lDest++) = 0; + break; + case JFFS2_COMPR_RTIME: + ret = 0; + rtime_decompress(src, lDest, jNode->csize, jNode->dsize); + break; + case JFFS2_COMPR_DYNRUBIN: + // this is slow but it works + ret = 0; + dynrubin_decompress(src, lDest, jNode->csize, jNode->dsize); + break; + case JFFS2_COMPR_ZLIB: + ret = zlib_decompress(src, lDest, jNode->csize, jNode->dsize); + break; + default: + /* unknown */ + putLabeledWord("UNKOWN COMPRESSION METHOD = ", jNode->compr); + return -1; + break; + } + } + + size += jNode->dsize; +#if 0 + putLabeledWord("read_inode: size = ", size); + putLabeledWord("read_inode: totalSize = ", totalSize); + putLabeledWord("read_inode: compr ret = ", ret); +#endif + } + b = b->next; + counter++; + } +#endif + +#if 0 + putLabeledWord("read_inode: returning = ", size); +#endif + return size; +} + +// find the inode from the slashless name given a parent +static u32 +jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + int len; + u32 counter; + u32 version = 0; + u32 inode = 0; + + // name is assumed slash free + len = strlen(name); + + counter = 0; + // we need to search all and return the inode with the highest version + for(b = pL->dirListHead;b;b=b->next,counter++) { + jDir = (struct jffs2_raw_dirent *) (b->offset); + if ((pino == jDir->pino) && (len == jDir->nsize) && (jDir->ino) && // 0 for unlink + (!strncmp(jDir->name, name, len))) { // a match + if (jDir->version < version) continue; + + if(jDir->version==0) { + /* Is this legal? */ + putstr(" ** WARNING ** "); + putnstr(jDir->name, jDir->nsize); + putstr(" is version 0 (in find, ignoring)\r\n"); + } else if(jDir->version==version) { + /* Im pretty sure this isn't ... */ + putstr(" ** ERROR ** "); + putnstr(jDir->name, jDir->nsize); + putLabeledWord(" has dup version =", version); + } + inode = jDir->ino; + version = jDir->version; + } +#if 0 + putstr("\r\nfind_inode:p&l ->"); + putnstr(jDir->name, jDir->nsize); + putstr("\r\n"); + putLabeledWord("pino = ", jDir->pino); + putLabeledWord("nsize = ", jDir->nsize); + putLabeledWord("b = ", (u32) b); + putLabeledWord("counter = ", counter); +#endif + } + return inode; +} + +static char *mkmodestr(unsigned long mode, char *str) +{ + static const char *l="xwr"; + int mask=1, i; + char c; + + switch (mode & __S_IFMT) { + case __S_IFDIR: str[0]=(mode & __S_ISVTX)?'t':'d'; break; + case __S_IFBLK: str[0]='b'; break; + case __S_IFCHR: str[0]='c'; break; + case __S_IFIFO: str[0]='f'; break; + case __S_IFLNK: str[0]='l'; break; + case __S_IFSOCK: str[0]='s'; break; + case __S_IFREG: str[0]='-'; break; + default: str[0]='?'; + } + + for(i=0;i<9;i++) { + c=l[i%3]; + str[9-i]=(mode & mask)?c:'-'; + mask=mask<<1; + } + + if((mode & __S_ISUID) && (mode & __S_IXUSR)) str[3]='s'; + if((mode & __S_ISGID) && (mode & __S_IXGRP)) str[6]='s'; + str[10]='\0'; + return str; +} + +static inline void dump_stat(struct stat *st, const char *name) +{ + char str[20]; + char s[64], *p; + + if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */ + st->st_mtime = 1; + + ctime_r(&st->st_mtime, s/*, 64*/); /* newlib ctime doesn't have buflen */ + + if((p=strchr(s,'\n'))!=NULL) *p='\0'; + if((p=strchr(s,'\r'))!=NULL) *p='\0'; + +/* + printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str), + st->st_size, s, name); +*/ + + printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name); +} + +static inline u32 dump_inode(struct b_lists * pL, struct jffs2_raw_dirent *d, struct jffs2_raw_inode *i) +{ + char fname[256]; + struct stat st; + + if(!d || !i) return -1; + + strncpy(fname, d->name, d->nsize); + fname[d->nsize]='\0'; + + memset(&st,0,sizeof(st)); + + st.st_mtime=i->mtime; + st.st_mode=i->mode; + st.st_ino=i->ino; + + /* neither dsize nor isize help us.. do it the long way */ + st.st_size=jffs2_1pass_read_inode(pL, i->ino, NULL); + + dump_stat(&st, fname); + + if (d->type == DT_LNK) { + unsigned char *src = (unsigned char *) (&i[1]); + putstr(" -> "); + putnstr(src, (int)i->dsize); + } + + putstr("\r\n"); + + return 0; +} + +// list inodes with the given pino +static u32 +jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + + for(b = pL->dirListHead;b;b=b->next) { + jDir = (struct jffs2_raw_dirent *) (b->offset); + if ((pino == jDir->pino) && (jDir->ino)) { // 0 inode for unlink + u32 i_version=0; + struct jffs2_raw_inode *jNode, *i=NULL; + struct b_node *b2 = pL->fragListHead; + + while (b2) { + jNode = (struct jffs2_raw_inode *) (b2->offset); + if (jNode->ino == jDir->ino + && jNode->version>=i_version) + i=jNode; + b2 = b2->next; + } + + dump_inode(pL, jDir, i); + } + } + return pino; +} + +static u32 +jffs2_1pass_search_inode(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + // discard any leading slash + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + + while ((c = (char *) strchr(tmp, '/'))) // we are still dired searching + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; +#if 0 + putstr("search_inode: tmp = "); + putstr(tmp); + putstr("\r\n"); + putstr("search_inode: wtmp = "); + putstr(working_tmp); + putstr("\r\n"); + putstr("search_inode: c = "); + putstr(c); + putstr("\r\n"); +#endif + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; +#if 0 + putstr("search_inode: post tmp = "); + putstr(tmp); + putstr("\r\n"); +#endif + + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino))) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + // this is for the bare filename, directories have already been mapped + if (!(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +static u32 +jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino) +{ + struct b_node *b; + struct b_node *b2; + struct jffs2_raw_dirent *jDir; + struct jffs2_raw_inode *jNode; + struct jffs2_raw_dirent *jDirFound; + char tmp[256]; + u32 version = 0; + u32 pino; + unsigned char *src; + + // we need to search all and return the inode with the highest version + for(b = pL->dirListHead; b; b=b->next) { + jDir = (struct jffs2_raw_dirent *) (b->offset); + if (ino == jDir->ino) { + if(jDir->version < version) continue; + + if(jDir->version == 0) { + /* Is this legal? */ + putstr(" ** WARNING ** "); + putnstr(jDir->name, jDir->nsize); + putstr(" is version 0 (in resolve, ignoring)\r\n"); + } else if(jDir->version == version) { + /* Im pretty sure this isn't ... */ + putstr(" ** ERROR ** "); + putnstr(jDir->name, jDir->nsize); + putLabeledWord(" has dup version (resolve) = ", + version); + } + + jDirFound = jDir; + version = jDir->version; + } + } + // now we found the right entry again. (shoulda returned inode*) + if (jDirFound->type != DT_LNK) + return jDirFound->ino; + // so its a soft link so we follow it again. + b2 = pL->fragListHead; + while (b2) { + jNode = (struct jffs2_raw_inode *) (b2->offset); + if (jNode->ino == jDirFound->ino) { + src = (unsigned char *) (b2->offset + sizeof(struct jffs2_raw_inode)); + +#if 0 + putLabeledWord("\t\t dsize = ", jNode->dsize); + putstr("\t\t target = "); + putnstr(src, jNode->dsize); + putstr("\r\n"); +#endif + strncpy(tmp, src, jNode->dsize); + tmp[jNode->dsize] = '\0'; + break; + } + b2 = b2->next; + } + // ok so the name of the new file to find is in tmp + // if it starts with a slash it is root based else shared dirs + if (tmp[0] == '/') + pino = 1; + else + pino = jDirFound->pino; + + return jffs2_1pass_search_inode(pL, tmp, pino); +} + +static u32 +jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + // discard any leading slash + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + working_tmp[0] = '\0'; + while ((c = (char *) strchr(tmp, '/'))) // we are still dired searching + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; + // only a failure if we arent looking at top level + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) && (working_tmp[0])) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + + if (tmp[0] && !(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + // this is for the bare filename, directories have already been mapped + if (!(pino = jffs2_1pass_list_inodes(pL, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +unsigned char +jffs2_1pass_rescan_needed(struct part_info *part, struct b_lists *pL) +{ + unsigned char ret = 0; + struct b_node *b; + struct jffs2_unknown_node *node; + + // if we have no list, we need to rescan + if (pL->fragListCount == 0) { + DEBUG("rescan: fraglist zero\n"); + return 1; + } + // or if we are scanninga new partition + if (pL->partOffset != part->offset) { + DEBUG("rescan: different partition\n"); + return 1; + } + // but suppose someone reflashed the root partition at the same offset... + b = pL->dirListHead; + while (b) { + node = (struct jffs2_unknown_node *) (b->offset); + if (node->nodetype != JFFS2_NODETYPE_DIRENT) { + DEBUG("rescan: fs changed beneath me? (%lx)\n", (unsigned long) b->offset); + return 1; + } + b = b->next; + } + return ret; +} + +static u32 +jffs2_1pass_build_lists(struct part_info * part, struct b_lists * pL) +{ + struct jffs2_unknown_node *node; + u32 offset; + u32 max = part->size - sizeof(struct jffs2_raw_inode); + u32 counter = 0; + u32 counter4 = 0; + u32 counterF = 0; + + // turn off the lcd. Refreshing the lcd adds 50% overhead to the + // jffs2 list building enterprise nope. in newer versions the overhead is + // only about 5 %. not enough to inconvenience people for. + // lcd_off(); + + // if we are building a list we need to refresh the cache. + // note that since we don't free our memory, eventually this will be bad. + // but we're a bootldr so what the hell. + jffs_init_1pass_list(); + pL->partOffset = part->offset; + offset = 0; + printf("Scanning JFFS2 FS: "); + + /* start at the beginning of the partition */ + while (offset < max) { + if (! (++counter%10000)) + printf("\b\b%c ", spinner[(counter / 10000) % 4]); + + node = (struct jffs2_unknown_node *) (part->offset + offset); + if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) { + // if its a fragment add it + if (node->nodetype == JFFS2_NODETYPE_INODE && inode_crc((struct jffs2_raw_inode *) node)) { + if (!(pL->fragListTail = add_node(pL->fragListTail, &(pL->fragListCount), + &(pL->fragListMemBase)))) { + putstr("add_node failed!\r\n"); + return 0; + } + pL->fragListTail->offset = (u32) (part->offset + offset); + if (!pL->fragListHead) + pL->fragListHead = pL->fragListTail; + } else if (node->nodetype == JFFS2_NODETYPE_DIRENT && + dirent_crc((struct jffs2_raw_dirent *) node) && + dirent_name_crc((struct jffs2_raw_dirent *) node)) { + printf("\b\b. "); +#if 0 + printf("Found DIRENT @ 0x%lx\n", offset); + putstr("\r\nbuild_lists:p&l ->"); + putnstr(((struct jffs2_raw_dirent *) node)->name, ((struct jffs2_raw_dirent *) node)->nsize); + putstr("\r\n"); + putLabeledWord("\tpino = ", ((struct jffs2_raw_dirent *) node)->pino); + putLabeledWord("\tnsize = ", ((struct jffs2_raw_dirent *) node)->nsize); +#endif + + if (!(pL->dirListTail = add_node(pL->dirListTail, &(pL->dirListCount), &(pL->dirListMemBase)))) { + putstr("add_node failed!\r\n"); + return 0; + } + pL->dirListTail->offset = (u32) (part->offset + offset); +#if 0 + putLabeledWord("\ttail = ", (u32) pL->dirListTail); + putstr("\ttailName ->"); + putnstr(((struct jffs2_raw_dirent *) (pL->dirListTail->offset))->name, + ((struct jffs2_raw_dirent *) (pL->dirListTail->offset))->nsize); + putstr("\r\n"); +#endif + if (!pL->dirListHead) + pL->dirListHead = pL->dirListTail; + } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { + if (node->totlen != sizeof(struct jffs2_unknown_node)) + printf("OOPS Cleanmarker has bad size %d != %d\n", node->totlen, sizeof(struct jffs2_unknown_node)); + } else { + printf("Unknown node type: %x len %d offset 0x%x\n", node->nodetype, node->totlen, offset); + } + offset += ((node->totlen + 3) & ~3); + counterF++; + } else if (node->magic == JFFS2_EMPTY_BITMASK && node->nodetype == JFFS2_EMPTY_BITMASK) { + offset = jffs2_scan_empty(offset, part); + } else { // if we know nothing of the filesystem, we just step and look. + offset += 4; + counter4++; + } +// printf("unknown node magic %4.4x %4.4x @ %lx\n", node->magic, node->nodetype, (unsigned long)node); + + } + + putstr("\b\b done.\r\n"); // close off the dots + // turn the lcd back on. + // splash(); + +#if 0 + putLabeledWord("dir entries = ", pL->dirListCount); + putLabeledWord("frag entries = ", pL->fragListCount); + putLabeledWord("+4 increments = ", counter4); + putLabeledWord("+file_offset increments = ", counterF); + +#endif + +#undef SHOW_ALL +#undef SHOW_ALL_FRAGMENTS + +#ifdef SHOW_ALL + { + struct b_node *b; + struct b_node *b2; + struct jffs2_raw_dirent *jDir; + struct jffs2_raw_inode *jNode; + + putstr("\r\n\r\n******The directory Entries******\r\n"); + b = pL->dirListHead; + while (b) { + jDir = (struct jffs2_raw_dirent *) (b->offset); + putstr("\r\n"); + putnstr(jDir->name, jDir->nsize); + putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic); + putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype); + putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc); + putLabeledWord("\tbuild_list: pino = ", jDir->pino); + putLabeledWord("\tbuild_list: version = ", jDir->version); + putLabeledWord("\tbuild_list: ino = ", jDir->ino); + putLabeledWord("\tbuild_list: mctime = ", jDir->mctime); + putLabeledWord("\tbuild_list: nsize = ", jDir->nsize); + putLabeledWord("\tbuild_list: type = ", jDir->type); + putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc); + putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc); + b = b->next; + } + +#ifdef SHOW_ALL_FRAGMENTS + putstr("\r\n\r\n******The fragment Entries******\r\n"); + b = pL->fragListHead; + while (b) { + jNode = (struct jffs2_raw_inode *) (b->offset); + putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset); + putLabeledWord("\tbuild_list: totlen = ", jNode->totlen); + putLabeledWord("\tbuild_list: inode = ", jNode->ino); + putLabeledWord("\tbuild_list: version = ", jNode->version); + putLabeledWord("\tbuild_list: isize = ", jNode->isize); + putLabeledWord("\tbuild_list: atime = ", jNode->atime); + putLabeledWord("\tbuild_list: offset = ", jNode->offset); + putLabeledWord("\tbuild_list: csize = ", jNode->csize); + putLabeledWord("\tbuild_list: dsize = ", jNode->dsize); + putLabeledWord("\tbuild_list: compr = ", jNode->compr); + putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr); + putLabeledWord("\tbuild_list: flags = ", jNode->flags); + b = b->next; + } +#endif /* SHOW_ALL_FRAGMENTS */ + } + +#endif /* SHOW_ALL */ + // give visual feedback that we are done scanning the flash + led_blink(0x0, 0x0, 0x1, 0x1); // off, forever, on 100ms, off 100ms + return 1; +} + + + + + +static u32 +jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL) +{ + struct b_node *b; + struct jffs2_raw_inode *jNode; + int i; + + b = pL->fragListHead; + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + piL->compr_info[i].num_frags = 0; + piL->compr_info[i].compr_sum = 0; + piL->compr_info[i].decompr_sum = 0; + } + + while (b) { + jNode = (struct jffs2_raw_inode *) (b->offset); + if (jNode->compr < JFFS2_NUM_COMPR) { + piL->compr_info[jNode->compr].num_frags++; + piL->compr_info[jNode->compr].compr_sum += jNode->csize; + piL->compr_info[jNode->compr].decompr_sum += jNode->dsize; + } + b = b->next; + } + return 0; +} + + + +static struct b_lists * +jffs2_get_list(struct part_info * part, const char *who) +{ + struct b_lists *pl = &g_1PassList; + + if (jffs2_1pass_rescan_needed(part, pl)) { + if (!jffs2_1pass_build_lists(part, pl)) { + printf("%s: Failed to scan JFFSv2 file structure\n", who); + return NULL; + } + } + return pl; +} + + +/* Print directory / file contents */ +u32 +jffs2_1pass_ls(struct part_info * part, const char *fname) +{ + struct b_lists *pl; + long ret = 0; + u32 inode; + + if (! (pl = jffs2_get_list(part, "ls"))) + return 0; + + if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) { + putstr("ls: Failed to scan jffs2 file structure\r\n"); + return 0; + } + + +#if 0 + putLabeledWord("found file at inode = ", inode); + putLabeledWord("read_inode returns = ", ret); +#endif + + return ret; +} + + + + + +/* Load a file from flash into memory. fname can be a full path */ +u32 +jffs2_1pass_load(char *dest, struct part_info * part, const char *fname) +{ + + struct b_lists *pl; + long ret = 0; + u32 inode; + + if (! (pl = jffs2_get_list(part, "load"))) + return 0; + + if (! (inode = jffs2_1pass_search_inode(pl, fname, 1))) { + putstr("load: Failed to find inode\r\n"); + return 0; + } + + /* Resolve symlinks */ + if (! (inode = jffs2_1pass_resolve_inode(pl, inode))) { + putstr("load: Failed to resolve inode structure\r\n"); + return 0; + } + + if ((ret = jffs2_1pass_read_inode(pl, inode, dest)) < 0) { + putstr("load: Failed to read inode\r\n"); + return 0; + } + + DEBUG(printf("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname, + (unsigned long) dest, ret)); + return ret; +} + +/* Return information about the fs on this partition */ +u32 +jffs2_1pass_info(struct part_info * part) +{ + struct b_jffs2_info info; + struct b_lists *pl = &g_1PassList; + int i; + + if (! (pl = jffs2_get_list(part, "info"))) + return 0; + + jffs2_1pass_fill_info(pl, &info); + for (i=0; i < JFFS2_NUM_COMPR; i++) { + printf("Compression: %s\n", compr_names[i]); + printf("\tfrag count: %d\n", info.compr_info[i].num_frags); + printf("\tcompressed sum: %d\n", info.compr_info[i].compr_sum); + printf("\tuncompressed sum: %d\n", info.compr_info[i].decompr_sum); + } + return 1; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h new file mode 100644 index 0000000..a9ce96d --- /dev/null +++ b/fs/jffs2/jffs2_private.h @@ -0,0 +1,78 @@ +#ifndef jffs2_private_h +#define jffs2_private_h + +#include + +struct b_node { + u32 offset; + struct b_node *next; +}; + +struct b_lists { + char *partOffset; + struct b_node *dirListTail; + struct b_node *dirListHead; + u32 dirListCount; + u32 dirListMemBase; + struct b_node *fragListTail; + struct b_node *fragListHead; + u32 fragListCount; + u32 fragListMemBase; + +}; +struct b_compr_info { + u32 num_frags; + u32 compr_sum; + u32 decompr_sum; +}; + +struct b_jffs2_info { + struct b_compr_info compr_info[JFFS2_NUM_COMPR]; +}; + +static inline int +hdr_crc(struct jffs2_unknown_node *node) +{ + u32 crc = crc32_no_comp(0, node, sizeof(struct jffs2_unknown_node) - 4); + u32 crc_blah = crc32_no_comp(~0, node, sizeof(struct jffs2_unknown_node) - 4); + + crc_blah ^= ~0; + + if (node->hdr_crc != crc) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_crc(struct jffs2_raw_dirent *node) +{ + if (node->node_crc != crc32_no_comp(0, node, sizeof(struct jffs2_raw_dirent) - 8)) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_name_crc(struct jffs2_raw_dirent *node) +{ + if (node->name_crc != crc32_no_comp(0, &(node->name), node->nsize)) { + return 0; + } else { + return 1; + } +} + +static inline int +inode_crc(struct jffs2_raw_inode *node) +{ + if (node->node_crc != crc32_no_comp(0, node, sizeof(struct jffs2_raw_inode) - 8)) { + return 0; + } else { + return 1; + } +} + +#endif /* jffs2_private.h */ diff --git a/fs/jffs2/mini_inflate.c b/fs/jffs2/mini_inflate.c new file mode 100644 index 0000000..09f5967 --- /dev/null +++ b/fs/jffs2/mini_inflate.c @@ -0,0 +1,393 @@ +/*------------------------------------------------------------------------- + * Filename: mini_inflate.c + * Version: $Id: mini_inflate.c,v 1.3 2002/01/24 22:58:42 rfeany Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Mini inflate implementation (RFC 1951) + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include + +/* The order that the code lengths in section 3.2.7 are in */ +static unsigned char huffman_order[] = {16, 17, 18, 0, 8, 7, 9, 6, 10, 5, + 11, 4, 12, 3, 13, 2, 14, 1, 15}; + +inline void cramfs_memset(int *s, const int c, size n) +{ + n--; + for (;n > 0; n--) s[n] = c; + s[0] = c; +} + +/* associate a stream with a block of data and reset the stream */ +static void init_stream(struct bitstream *stream, unsigned char *data, + void *(*inflate_memcpy)(void *, const void *, size)) +{ + stream->error = NO_ERROR; + stream->memcpy = inflate_memcpy; + stream->decoded = 0; + stream->data = data; + stream->bit = 0; /* The first bit of the stream is the lsb of the + * first byte */ + + /* really sorry about all this initialization, think of a better way, + * let me know and it will get cleaned up */ + stream->codes.bits = 8; + stream->codes.num_symbols = 19; + stream->codes.lengths = stream->code_lengths; + stream->codes.symbols = stream->code_symbols; + stream->codes.count = stream->code_count; + stream->codes.first = stream->code_first; + stream->codes.pos = stream->code_pos; + + stream->lengths.bits = 16; + stream->lengths.num_symbols = 288; + stream->lengths.lengths = stream->length_lengths; + stream->lengths.symbols = stream->length_symbols; + stream->lengths.count = stream->length_count; + stream->lengths.first = stream->length_first; + stream->lengths.pos = stream->length_pos; + + stream->distance.bits = 16; + stream->distance.num_symbols = 32; + stream->distance.lengths = stream->distance_lengths; + stream->distance.symbols = stream->distance_symbols; + stream->distance.count = stream->distance_count; + stream->distance.first = stream->distance_first; + stream->distance.pos = stream->distance_pos; + +} + +/* pull 'bits' bits out of the stream. The last bit pulled it returned as the + * msb. (section 3.1.1) + */ +inline unsigned long pull_bits(struct bitstream *stream, + const unsigned int bits) +{ + unsigned long ret; + int i; + + ret = 0; + for (i = 0; i < bits; i++) { + ret += ((*(stream->data) >> stream->bit) & 1) << i; + + /* if, before incrementing, we are on bit 7, + * go to the lsb of the next byte */ + if (stream->bit++ == 7) { + stream->bit = 0; + stream->data++; + } + } + return ret; +} + +inline int pull_bit(struct bitstream *stream) +{ + int ret = ((*(stream->data) >> stream->bit) & 1); + if (stream->bit++ == 7) { + stream->bit = 0; + stream->data++; + } + return ret; +} + +/* discard bits up to the next whole byte */ +static void discard_bits(struct bitstream *stream) +{ + if (stream->bit != 0) { + stream->bit = 0; + stream->data++; + } +} + +/* No decompression, the data is all literals (section 3.2.4) */ +static void decompress_none(struct bitstream *stream, unsigned char *dest) +{ + unsigned int length; + + discard_bits(stream); + length = *(stream->data++); + length += *(stream->data++) << 8; + pull_bits(stream, 16); /* throw away the inverse of the size */ + + stream->decoded += length; + stream->memcpy(dest, stream->data, length); + stream->data += length; +} + +/* Read in a symbol from the stream (section 3.2.2) */ +static int read_symbol(struct bitstream *stream, struct huffman_set *set) +{ + int bits = 0; + int code = 0; + while (!(set->count[bits] && code < set->first[bits] + + set->count[bits])) { + code = (code << 1) + pull_bit(stream); + if (++bits > set->bits) { + /* error decoding (corrupted data?) */ + stream->error = CODE_NOT_FOUND; + return -1; + } + } + return set->symbols[set->pos[bits] + code - set->first[bits]]; +} + +/* decompress a stream of data encoded with the passed length and distance + * huffman codes */ +static void decompress_huffman(struct bitstream *stream, unsigned char *dest) +{ + struct huffman_set *lengths = &(stream->lengths); + struct huffman_set *distance = &(stream->distance); + + int symbol, length, dist, i; + + do { + if ((symbol = read_symbol(stream, lengths)) < 0) return; + if (symbol < 256) { + *(dest++) = symbol; /* symbol is a literal */ + stream->decoded++; + } else if (symbol > 256) { + /* Determine the length of the repitition + * (section 3.2.5) */ + if (symbol < 265) length = symbol - 254; + else if (symbol == 285) length = 258; + else { + length = pull_bits(stream, (symbol - 261) >> 2); + length += (4 << ((symbol - 261) >> 2)) + 3; + length += ((symbol - 1) % 4) << + ((symbol - 261) >> 2); + } + + /* Determine how far back to go */ + if ((symbol = read_symbol(stream, distance)) < 0) + return; + if (symbol < 4) dist = symbol + 1; + else { + dist = pull_bits(stream, (symbol - 2) >> 1); + dist += (2 << ((symbol - 2) >> 1)) + 1; + dist += (symbol % 2) << ((symbol - 2) >> 1); + } + stream->decoded += length; + for (i = 0; i < length; i++) *(dest++) = dest[-dist]; + } + } while (symbol != 256); /* 256 is the end of the data block */ +} + +/* Fill the lookup tables (section 3.2.2) */ +static void fill_code_tables(struct huffman_set *set) +{ + int code = 0, i, length; + + /* fill in the first code of each bit length, and the pos pointer */ + set->pos[0] = 0; + for (i = 1; i < set->bits; i++) { + code = (code + set->count[i - 1]) << 1; + set->first[i] = code; + set->pos[i] = set->pos[i - 1] + set->count[i - 1]; + } + + /* Fill in the table of symbols in order of their huffman code */ + for (i = 0; i < set->num_symbols; i++) { + if ((length = set->lengths[i])) + set->symbols[set->pos[length]++] = i; + } + + /* reset the pos pointer */ + for (i = 1; i < set->bits; i++) set->pos[i] -= set->count[i]; +} + +static void init_code_tables(struct huffman_set *set) +{ + cramfs_memset(set->lengths, 0, set->num_symbols); + cramfs_memset(set->count, 0, set->bits); + cramfs_memset(set->first, 0, set->bits); +} + +/* read in the huffman codes for dynamic decoding (section 3.2.7) */ +static void decompress_dynamic(struct bitstream *stream, unsigned char *dest) +{ + /* I tried my best to minimize the memory footprint here, while still + * keeping up performance. I really dislike the _lengths[] tables, but + * I see no way of eliminating them without a sizable performance + * impact. The first struct table keeps track of stats on each bit + * length. The _length table keeps a record of the bit length of each + * symbol. The _symbols table is for looking up symbols by the huffman + * code (the pos element points to the first place in the symbol table + * where that bit length occurs). I also hate the initization of these + * structs, if someone knows how to compact these, lemme know. */ + + struct huffman_set *codes = &(stream->codes); + struct huffman_set *lengths = &(stream->lengths); + struct huffman_set *distance = &(stream->distance); + + int hlit = pull_bits(stream, 5) + 257; + int hdist = pull_bits(stream, 5) + 1; + int hclen = pull_bits(stream, 4) + 4; + int length, curr_code, symbol, i, last_code; + + last_code = 0; + + init_code_tables(codes); + init_code_tables(lengths); + init_code_tables(distance); + + /* fill in the count of each bit length' as well as the lengths + * table */ + for (i = 0; i < hclen; i++) { + length = pull_bits(stream, 3); + codes->lengths[huffman_order[i]] = length; + if (length) codes->count[length]++; + + } + fill_code_tables(codes); + + /* Do the same for the length codes, being carefull of wrap through + * to the distance table */ + curr_code = 0; + while (curr_code < hlit) { + if ((symbol = read_symbol(stream, codes)) < 0) return; + if (symbol == 0) { + curr_code++; + last_code = 0; + } else if (symbol < 16) { /* Literal length */ + lengths->lengths[curr_code] = last_code = symbol; + lengths->count[symbol]++; + curr_code++; + } else if (symbol == 16) { /* repeat the last symbol 3 - 6 + * times */ + length = 3 + pull_bits(stream, 2); + for (;length; length--, curr_code++) + if (curr_code < hlit) { + lengths->lengths[curr_code] = + last_code; + lengths->count[last_code]++; + } else { /* wrap to the distance table */ + distance->lengths[curr_code - hlit] = + last_code; + distance->count[last_code]++; + } + } else if (symbol == 17) { /* repeat a bit length 0 */ + curr_code += 3 + pull_bits(stream, 3); + last_code = 0; + } else { /* same, but more times */ + curr_code += 11 + pull_bits(stream, 7); + last_code = 0; + } + } + fill_code_tables(lengths); + + /* Fill the distance table, don't need to worry about wrapthrough + * here */ + curr_code -= hlit; + while (curr_code < hdist) { + if ((symbol = read_symbol(stream, codes)) < 0) return; + if (symbol == 0) { + curr_code++; + last_code = 0; + } else if (symbol < 16) { + distance->lengths[curr_code] = last_code = symbol; + distance->count[symbol]++; + curr_code++; + } else if (symbol == 16) { + length = 3 + pull_bits(stream, 2); + for (;length; length--, curr_code++) { + distance->lengths[curr_code] = + last_code; + distance->count[last_code]++; + } + } else if (symbol == 17) { + curr_code += 3 + pull_bits(stream, 3); + last_code = 0; + } else { + curr_code += 11 + pull_bits(stream, 7); + last_code = 0; + } + } + fill_code_tables(distance); + + decompress_huffman(stream, dest); +} + +/* fill in the length and distance huffman codes for fixed encoding + * (section 3.2.6) */ +static void decompress_fixed(struct bitstream *stream, unsigned char *dest) +{ + /* let gcc fill in the initial values */ + struct huffman_set *lengths = &(stream->lengths); + struct huffman_set *distance = &(stream->distance); + + cramfs_memset(lengths->count, 0, 16); + cramfs_memset(lengths->first, 0, 16); + cramfs_memset(lengths->lengths, 8, 144); + cramfs_memset(lengths->lengths + 144, 9, 112); + cramfs_memset(lengths->lengths + 256, 7, 24); + cramfs_memset(lengths->lengths + 280, 8, 8); + lengths->count[7] = 24; + lengths->count[8] = 152; + lengths->count[9] = 112; + + cramfs_memset(distance->count, 0, 16); + cramfs_memset(distance->first, 0, 16); + cramfs_memset(distance->lengths, 5, 32); + distance->count[5] = 32; + + + fill_code_tables(lengths); + fill_code_tables(distance); + + + decompress_huffman(stream, dest); +} + +/* returns the number of bytes decoded, < 0 if there was an error. Note that + * this function assumes that the block starts on a byte boundry + * (non-compliant, but I don't see where this would happen). section 3.2.3 */ +long decompress_block(unsigned char *dest, unsigned char *source, + void *(*inflate_memcpy)(void *, const void *, size)) +{ + int bfinal, btype; + struct bitstream stream; + + init_stream(&stream, source, inflate_memcpy); + do { + bfinal = pull_bit(&stream); + btype = pull_bits(&stream, 2); + if (btype == NO_COMP) decompress_none(&stream, dest + stream.decoded); + else if (btype == DYNAMIC_COMP) + decompress_dynamic(&stream, dest + stream.decoded); + else if (btype == FIXED_COMP) decompress_fixed(&stream, dest + stream.decoded); + else stream.error = COMP_UNKNOWN; + } while (!bfinal && !stream.error); + +#if 0 + putstr("decompress_block start\r\n"); + putLabeledWord("stream.error = ",stream.error); + putLabeledWord("stream.decoded = ",stream.decoded); + putLabeledWord("dest = ",dest); + putstr("decompress_block end\r\n"); +#endif + return stream.error ? -stream.error : stream.decoded; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index a50d03a..7d555b5 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -90,6 +90,7 @@ #define BATL_CACHEINHIBIT 0x00000020 #define BATL_MEMCOHERENCE 0x00000010 #define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 #define BATL_PP_MSK 0x00000003 #define BATL_PP_00 0x00000000 /* No access */ @@ -97,6 +98,10 @@ #define BATL_PP_10 0x00000002 /* Read-write */ #define BATL_PP_11 0x00000003 +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + #ifndef __ASSEMBLY__ /* cpu ids we detect */ typedef enum __cpu_t { @@ -111,8 +116,42 @@ typedef enum __cpu_t { extern cpu_t get_cpu_type(void); -extern unsigned long get_hid0(void); -extern void set_hid0(unsigned long); -#endif +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + +#endif /* __ASSEMBLY__ */ #endif /* __MPC74XX_H__ */ diff --git a/include/asm/processor.h b/include/asm/processor.h index d1ab4ba..b950cfd 100644 --- a/include/asm/processor.h +++ b/include/asm/processor.h @@ -173,10 +173,12 @@ #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ #define HID0_DLOCK (1<<12) /* Data Cache Lock */ #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ -#define HID0_DCI (1<<10) /* Data Cache Invalidate */ +#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ +#define HID0_DCI HID0_DCFI #define HID0_SPD (1<<9) /* Speculative disable */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ -#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ +#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ #define HID0_ABE (1<<3) /* Address Broadcast Enable */ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h index bbbb5c1..2856907 100644 --- a/include/cmd_bsp.h +++ b/include/cmd_bsp.h @@ -168,6 +168,42 @@ int do_crayL1 (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); #endif /* CONFIG_CRAY405 */ /* ----------------------------------------------------------------------------*/ +#if defined (CONFIG_EVB64260) +/* ----- EVB64260 -------------------------------------------------------------*/ +#ifdef ZUMA_NTL +#define CMD_TBL_BSP ZUMA_TBL_ENTRY + +#define ZUMA_TBL_ENTRY MK_CMD_TBL_ENTRY( \ + "zinit", 5, 1, 0, do_zuma_init_pbb, \ + "zinit - init zuma pbb\n", \ + "\n" \ + " - init zuma pbb\n" \ +), MK_CMD_TBL_ENTRY( \ + "zdtest", 6, 3, 1, do_zuma_test_dma, \ + "zdtest - run dma test\n", \ + "[cmd [count]]\n" \ + " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n" \ +), MK_CMD_TBL_ENTRY( \ + "zminit", 5, 1, 0, do_zuma_init_mbox, \ + "zminit - init zuma mbox\n", \ + "\n" \ + " - init zuma mbox\n" \ +), + +int do_zuma_init_pbb (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); +int do_zuma_test_dma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); +int do_zuma_init_mbox (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); + +void zuma_init_pbb(void); +int zuma_mbox_init(void); +int zuma_test_dma(int cmd, int size); +#else +#define CMD_TBL_BSP +#endif /* ZUMA_NTL */ + +#endif /* CONFIG_EVB64260 */ +/* ----------------------------------------------------------------------------*/ + #else #define CMD_TBL_BSP #endif /* CFG_CMD_BSP */ diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 09825d6..65e9e86 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -68,6 +68,7 @@ #define CFG_CMD_MISC 0x0000000200000000 /* Misc functions like sleep etc*/ #define CFG_CMD_USB 0x0000000400000000 /* USB Support */ #define CFG_CMD_DOC 0x0000000800000000 /* Disk-On-Chip Support */ +#define CFG_CMD_JFFS2 0x0000001000000000 /* JFFS2 Support */ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFF /* ALL commands */ @@ -88,6 +89,7 @@ CFG_CMD_IDE | \ CFG_CMD_IMMAP | \ CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ CFG_CMD_MII | \ CFG_CMD_PCI | \ diff --git a/include/cmd_jffs2.h b/include/cmd_jffs2.h new file mode 100644 index 0000000..5ebc23d --- /dev/null +++ b/include/cmd_jffs2.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * JFFS2 support + */ +#ifndef _CMD_JFFS2_H +#define _CMD_JFFS2_H + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CMD_TBL_JFFS2 MK_CMD_TBL_ENTRY( \ + "fsload", 5, 3, 0, do_jffs2_fsload, \ + "fsload - load binary file from a filesystem image\n", \ + "[ off ] [ filename ]\n" \ + " - load binary file from flash bank\n" \ + " with offset 'off'\n" \ +), \ + MK_CMD_TBL_ENTRY( \ + "fsinfo", 5, 1, 1, do_jffs2_fsinfo, \ + "fsinfo - print information about filesystems\n", \ + "\n" \ + " - print information about filesystems\n" \ +), \ + MK_CMD_TBL_ENTRY( \ + "ls", 2, 2, 1, do_jffs2_ls, \ + "ls - list files in a directory (default /)\n", \ + "[ directory ]\n" \ + " - list files in a directory.\n" \ +), + +int do_jffs2_fsload (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); +int do_jffs2_fsinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); +int do_jffs2_ls (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); + +#else +#define CMD_TBL_JFFS2 +#endif /* CFG_CMD_JFFS2 */ + +#endif /* _CMD_JFFS2_H */ diff --git a/include/commproc.h b/include/commproc.h index 62c8970..d23a636 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1002,6 +1002,14 @@ typedef struct scc_enet { /*** RPXCLASSIC *****************************************************/ #ifdef CONFIG_RPXCLASSIC + +#ifdef CONFIG_FEC_ENET + +# define FEC_ENET /* use FEC for EThernet */ +# undef SCC_ENET + +#else /* ! CONFIG_FEC_ENET */ + /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC1 use. */ @@ -1021,6 +1029,9 @@ typedef struct scc_enet { */ #define SICR_ENET_MASK ((uint)0x000000ff) #define SICR_ENET_CLKRT ((uint)0x0000003d) + +#endif /* CONFIG_FEC_ENET */ + #endif /* CONFIG_RPXCLASSIC */ /*** RPXLITE ********************************************************/ diff --git a/include/config_EVB64260.h b/include/config_EVB64260.h index 8c509d0..2491f9f 100644 --- a/include/config_EVB64260.h +++ b/include/config_EVB64260.h @@ -34,23 +34,13 @@ #include #endif +/* XXX #include "local.h" XXX */ + /* * High Level Configuration Options * (easy to change) */ -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:11:22:33:44:55 - -/* next two ethernet hwaddrs */ -#define CONFIG_ETH1ADDR 00:11:22:33:44:66 -#define CONFIG_ETH2ADDR 00:11:22:33:44:77 - -#define CONFIG_ENV_OVERWRITE - #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ #define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ @@ -61,6 +51,8 @@ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT +#define CFG_BOARD_NAME "EVB64260" + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " @@ -76,12 +68,14 @@ * to use the MPSC, #define CONFIG_MPSC. If you have wired up another * mpsc channel, change CONFIG_MPSC_PORT to the desired value. */ -#undef CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 +#define CONFIG_MPSC +#define CONFIG_MPSC_PORT 0 /* to change the default ethernet port, use this define (options: 0, 1, 2) */ #define CONFIG_ETHER_PORT 0 +#undef CONFIG_ETHER_PORT_MII /* use RMII */ + #if 1 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else @@ -91,7 +85,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp 1000000 && " \ + "bootp && " \ "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:" \ "$netmask:$hostname:eth0:none; && " \ @@ -107,7 +101,7 @@ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -116,7 +110,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -129,12 +123,13 @@ #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x300000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_BUS_HZ 100000000 /* 100 MHz */ +#define CFG_BUS_CLK CFG_BUS_HZ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* * Low Level Configuration Settings @@ -149,6 +144,8 @@ #define CFG_INIT_RAM_END 0x1000 #define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for init data */ #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_RAM_LOCK + /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -157,90 +154,172 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfff00000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc */ /* areas to map different things with the GT in physical space */ #define CFG_DRAM_BANKS 4 -#define CFG_DFL_GT_REGS 0x14000000 -#define CFG_GT_REGS 0xf0000000 -#define CFG_DEV0_SPACE (CFG_GT_REGS + _8M) -#define CFG_DEV1_SPACE (CFG_GT_REGS + (2 * _8M)) -#define CFG_DEV2_SPACE (CFG_GT_REGS + (3 * _8M)) -#define CFG_DEV3_SPACE (CFG_GT_REGS + (4 * _8M)) - -#define CFG_DEV0_SIZE _8M -#define CFG_DEV1_SIZE _8M -#define CFG_DEV2_SIZE _8M -#define CFG_DEV3_SIZE _16M - -#define CFG_DEV0_PAR 0x20205093 -#define CFG_DEV1_PAR 0xcfcfffff -#define CFG_DEV2_PAR 0xc0059bd4 -#define CFG_8BIT_BOOT_PAR 0xc00b5e7c -#define CFG_32BIT_BOOT_PAR 0xc4a8241c - -#define CFG_MPP_CONTROL_0 0x53541717 -#define CFG_MPP_CONTROL_1 0x44009911 -#define CFG_MPP_CONTROL_2 0x40091818 -#define CFG_MPP_CONTROL_3 0x00090066 - -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ +#define CFG_GT_REGS 0xf8000000 +#define CFG_DEV_BASE 0xfc000000 + +#define CFG_DEV0_SPACE CFG_DEV_BASE +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) + +#define CFG_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */ +#define CFG_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */ +#define CFG_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */ +#define CFG_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */ + +#define CFG_DEV0_PAR 0x20205093 +#define CFG_DEV1_PAR 0xcfcfffff +#define CFG_DEV2_PAR 0xc0059bd4 +#define CFG_8BIT_BOOT_PAR 0xc00b5e7c +#define CFG_32BIT_BOOT_PAR 0xc4a8241c + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ + +#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ + /* DMAAck[1:0] GNT0[1:0] */ +#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ + /* DMAReq[4] DMAAck[4] WDNMI WDE */ +#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ + /* DMAAck[1:0] GNT1[1:0] */ + +#if 0 /* Wrong?? NTL */ +# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ + /* GPP[27:26] Int[1:0] */ +#else +# define CFG_MPP_CONTROL_3 0x00090000 /* GPP[31:29] BClkOut0 */ + /* GPP[27:26] */ + /* GPP[25:24] (pci int[1:0]) */ +#endif + +# define CFG_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ + +#if 0 /* Wrong?? - NTL */ +# define CFG_GPP_LEVEL_CONTROL 0x000002c6 +#else +# define CFG_GPP_LEVEL_CONTROL 0xc3400000 /* 0110 0011 0100 0000 */ + /* gpp[30]:gpp[29] */ + /* gpp[25:24] (pci int[1:0]) */ + /* gpp[22] */ + +# define CFG_SDRAM_CONFIG 0xd8e10200 /* 0x448 */ + /* idmas use buffer 1,1 + comm use buffer 0 + pci use buffer 1,1 + cpu use buffer 0 + normal load (see also ifdef HVL) + standard SDRAM (see also ifdef REG) + non staggered refresh */ + /* 31:26 25 23 20 19 18 16 */ + /* 110110 00 111 0 0 00 1 */ + /* refresh_count=0x200 + phisical interleaving enable + virtual interleaving enable */ + /* 15 14 13:0 */ + /* 0 0 0x200 */ +#endif + +#define CFG_DUART_IO CFG_DEV2_SPACE +#define CFG_DUART_CHAN 1 /* channel to use for console */ #define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 +#define CFG_INIT_CHAN2 -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ +#define SRAM_BASE CFG_DEV0_SPACE +#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ -#define CFG_CPU_CLK 300000000 -#define CFG_BUS_CLK 125000000 -/*---------------------------------------------------------------------- - * Initial BAT mappings +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- */ -/* SDRAM */ -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + -/* galileo regs [poweron location] */ -#define CFG_IBAT2L (CFG_DFL_GT_REGS | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (CFG_DFL_GT_REGS | BATU_BL_16M | BATU_VS | BATU_VP) -/* flash, moved GT regs, etc */ -#define CFG_DBAT3L (CFG_GT_REGS | BATL_PP_10 | BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (CFG_GT_REGS | BATU_BL_256M | BATU_VS | BATU_VP) +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M -/* the GUARDEDSTORAGE bit should not be set in IBATs */ -#define CFG_IBAT3L (CFG_GT_REGS | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (CFG_GT_REGS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CFG_DBAT1L CFG_IBAT1L #define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U /* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization @@ -248,12 +327,16 @@ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ +#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ + #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) /*----------------------------------------------------------------------- * Cache Configuration @@ -267,9 +350,17 @@ * L2CR setup -- make sure this is right for your board! * look in include/mpc74xx.h for the defines used here */ -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) + +#define CFG_L2 + +#ifdef CONFIG_750CX +#define L2_INIT 0 +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) /* * Internal Definitions @@ -279,4 +370,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_BOARD_ASM_INIT 1 + + #endif /* __CONFIG_H */ diff --git a/include/config_LANTEC.h b/include/config_LANTEC.h index 922487e..42edd7e 100644 --- a/include/config_LANTEC.h +++ b/include/config_LANTEC.h @@ -92,6 +92,7 @@ & ~CFG_CMD_I2C \ & ~CFG_CMD_IDE \ & ~CFG_CMD_IRQ \ + & ~CFG_CMD_JFFS2 \ & ~CFG_CMD_KGDB \ & ~CFG_CMD_MII \ & ~CFG_CMD_PCI \ diff --git a/include/config_MPC8260ADS.h b/include/config_MPC8260ADS.h index 6427de7..8484fea 100644 --- a/include/config_MPC8260ADS.h +++ b/include/config_MPC8260ADS.h @@ -107,6 +107,7 @@ CFG_CMD_ELF | \ CFG_CMD_FDC | \ CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ CFG_CMD_MII | \ CFG_CMD_PCI | \ diff --git a/include/config_MUSENKI.h b/include/config_MUSENKI.h index e52dba6..b04a464 100644 --- a/include/config_MUSENKI.h +++ b/include/config_MUSENKI.h @@ -23,7 +23,7 @@ /* * - * Configuration settings for the CU824 board. + * Configuration settings for the MUSENKI board. * */ @@ -41,7 +41,7 @@ * (easy to change) */ -#define CONFIG_MPC824x 1 +#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_MUSENKI 1 @@ -55,28 +55,36 @@ #define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ #define CONFIG_BOOTDELAY 5 -#define CONFIG_COMMANDS CONFIG_CMD_DFL +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ #include /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP 1 /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - #define CFG_MAXARGS 8 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 /* Default load address */ +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#define PCI_ENET_IOADDR 0x80000000 +#define PCI_ENET_MEMADDR 0x80000000 + + /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -97,8 +105,9 @@ #define CFG_EUMB_ADDR 0xFC000000 #define CFG_MONITOR_BASE TEXT_BASE - +#if 0 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#endif #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_MEMTEST_START 0x00004000 /* memtest works on */ @@ -127,7 +136,7 @@ #define CFG_INIT_RAM_END 0x1000000 /* 16MB */ #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET -#else + #define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ #define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data */ @@ -135,6 +144,16 @@ #define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET #endif + +#define CFG_MONITOR_LEN 0x00030000 +/* #define CFG_MONITOR_BASE TEXT_BASE */ +/*#define CFG_INIT_DATA_SIZE 256*/ +#define CFG_INIT_DATA_SIZE 128 +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) + + /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -143,6 +162,7 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +#define CFG_SERIAL_CLOCK 100000000 #define CFG_HZ 1000 #define CFG_ETH_DEV_FN 0x7800 @@ -150,8 +170,8 @@ /* Bit-field values for MCCR1. */ -#define CFG_ROMNAL 0xf -#define CFG_ROMFAL 0x1f +#define CFG_ROMNAL 7 +#define CFG_ROMFAL 11 #define CFG_DBUS_SIZE 0x3 /* Bit-field values for MCCR2. @@ -165,19 +185,23 @@ /* Bit-field values for MCCR3. */ -#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ /* Bit-field values for MCCR4. */ -#define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ +#define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ #define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ +#define CFG_ACTORW 3 /* FIXME was 2 */ #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ -#define CFG_ACTORW 0xa /* FIXME was 2 */ +#if 0 +#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length OBSOLETE */ +#endif #define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 -#define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ @@ -218,7 +242,7 @@ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#if 0 +#if 1 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) @@ -286,4 +310,5 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ + #endif /* __CONFIG_H */ diff --git a/include/config_RPXClassic.h b/include/config_RPXClassic.h new file mode 100644 index 0000000..74c18d9 --- /dev/null +++ b/include/config_RPXClassic.h @@ -0,0 +1,414 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * PPCboot port on RPXlite board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define RPXClassic_50MHz + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 +#define CONFIG_RPXCLASSIC 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ + + +/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */ +#undef CONFIG_FEC_ENET +#ifdef CONFIG_FEC_ENET +#define CFG_DISCOVER_PHY 1 +#endif /* CONFIG_FEC_ENET */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + + +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NONSTD | CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_RESET_ADDRESS 0x80000000 +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFA200000 + +/*----------------------------------------------------------------------------- + * I2C Configuration + *----------------------------------------------------------------------------- + */ +#define CONFIG_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0x34 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 + +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE 0xFF000000 +/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if 0 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_ADDR 0xfa000100 +#define CFG_ENV_SIZE 0x1000 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/* #define CFG_DER 0x2002000F */ +/* #define CFG_DER 0 */ +#define CFG_DER 0x0082000F + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ +#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ + +/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000E00 + +#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* RPXLITE mem setting */ +#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ +#define CFG_OR3_PRELIM 0xff7f8970 +#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ +#define CFG_OR4_PRELIM 0xFFF80970 + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 58 + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV8 + +/* + * MAMR settings for SDRAM + */ + +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ + MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ +/* Configuration variable added by yooth. */ +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ + +/* + * BCSRx + * + * Board Status and Control Registers + * + */ + +#define BCSR0 0xFA400000 +#define BCSR1 0xFA400001 +#define BCSR2 0xFA400002 +#define BCSR3 0xFA400003 + +#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ +#define BCSR0_COLTEST 0x20 +#define BCSR0_ETHLPBK 0x40 +#define BCSR0_ETHEN 0x80 + +#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ +#define BCSR1_PCVCTL6 0x02 +#define BCSR1_PCVCTL5 0x04 +#define BCSR1_PCVCTL4 0x08 +#define BCSR1_IPB5SEL 0x10 + +#define BCSR2_MIIRST 0x80 +#define BCSR2_MIIPWRDWN 0x40 +#define BCSR2_MIICTL 0x08 + +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 + + +/* + * Environment setting + */ + +/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ +/* #define CONFIG_IPADDR 10.10.106.1 */ +/* #define CONFIG_SERVERIP 10.10.104.11 */ + +#endif /* __CONFIG_H */ diff --git a/include/config_Sandpoint8240.h b/include/config_Sandpoint8240.h index 48a0690..235cb18 100644 --- a/include/config_Sandpoint8240.h +++ b/include/config_Sandpoint8240.h @@ -169,7 +169,7 @@ #define CFG_RDLAT 4 /* data latency from read command */ #define CFG_PRETOACT 3 /* Precharge to activate interval */ #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTTORW 3 /* Activate to R/W */ +#define CFG_ACTORW 3 /* Activate to R/W */ #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ #define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ diff --git a/include/config_Sandpoint8245.h b/include/config_Sandpoint8245.h new file mode 100644 index 0000000..1259a61 --- /dev/null +++ b/include/config_Sandpoint8245.h @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_SANDPOINT 1 + +#if 0 +#define USE_DINK32 1 +#else +#undef USE_DINK32 +#endif + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ + +#define PCI_ENET_IOADDR 0x80000000 +#define PCI_ENET_MEMADDR 0x80000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_INIT_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +/*#define CFG_INIT_DATA_SIZE 256*/ +#define CFG_INIT_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0xFFF00000 +#if 0 +#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ +#else +#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ +#endif +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_ISA_MEM 0xFD000000 +#define CFG_ISA_IO 0xFE000000 + +#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x01000000 +#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + + +#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ +#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ +#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ +#define CFG_NS87308_BADDR_10 1 + + +#define CFG_NS_PC87308UL 1 /* Nat Semi super-io controller on ISA bus */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CFG_ROMNAL 7 /*rom/flash next access time */ +#define CFG_ROMFAL 11 /*rom/flash access time */ + +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#if 0 +#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ +#endif + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#undef NR_8259_INTS +#define NR_8259_INTS 1 + + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +#endif /* __CONFIG_H */ diff --git a/include/config_WALNUT405.h b/include/config_WALNUT405.h index 47f65e8..5a754e2 100644 --- a/include/config_WALNUT405.h +++ b/include/config_WALNUT405.h @@ -63,7 +63,11 @@ * Set to 0 to use polling instead of interrupts. * Setting to 0 will also disable RTS/CTS handshaking. */ +#if 0 #define CONFIG_SERIAL_SOFTWARE_FIFO 4000 +#else +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#endif #if 0 #define CONFIG_BOOTARGS "root=/dev/nfs " \ @@ -220,7 +224,7 @@ * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM 0xFFF80000 /* FLASH bank #0 */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ diff --git a/include/config_ZUMA.h b/include/config_ZUMA.h new file mode 100644 index 0000000..feb3bae --- /dev/null +++ b/include/config_ZUMA.h @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#ifndef __ASSEMBLY__ +#include +#endif + +/* XXX #include "local.h" XXX */ + +#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ +#define ZUMA_NTL 1 /* temporary, will rename to something nicer */ + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ + +#define CONFIG_ECC /* enable ECC support */ + +#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_PRE_INIT + +#define CFG_BOARD_NAME "Zuma APv2" + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ +#define CONFIG_MPSC + +#define CONFIG_MPSC_PORT 0 + +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#define CONFIG_ETHER_PORT 0 + +#define CONFIG_ETHER_PORT_MII /* use MII */ + +#if 1 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS + +#define CONFIG_BOOTCOMMAND \ + "tftpboot && " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:" \ + "$netmask:$hostname:eth0:none panic=5 && bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 1 +#define CFG_JFFS2_NUM_BANKS 2 + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x300000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ + +#define CFG_BUS_HZ 133000000 /* 133 MHz */ + +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_RAM_LOCK + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfff00000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 4 +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ +#define CFG_GT_REGS 0xf8000000 /* later mapped GT_REGS */ +#define CFG_DEV_BASE 0xf0000000 +#define CFG_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ +#define CFG_DEV1_SIZE _8M /* unused */ +#define CFG_DEV2_SIZE _8M /* unused */ +#define CFG_DEV3_SIZE _8M /* unused */ + +#define CFG_DEV0_PAR 0xc498241c + /* c 4 9 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 01|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 3 | 4 */ + +#define CFG_8BIT_BOOT_PAR 0xc00b5e7c + +#define CFG_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ +#define CFG_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ +#define CFG_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ +#define CFG_MPP_CONTROL_3 0x00009900 /* GPP[31:28] (pci int[3:0]) */ + /* WDE WDNMI GPP[25:24] */ + +#define CFG_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ +#define CFG_GPP_LEVEL_CONTROL 0xf000c000 /* GPP[31:28] ints GPP[15:14] led */ + +#define CFG_SDRAM_CONFIG 0xf4e18200 /* 0x448 */ + /* idmas use buffer 1,1 + comm use buffer 1 + pci use buffer 1,0 + cpu use buffer 1 (R*18) + normal load (see also ifdef HVL) + standard SDRAM (see also ifdef REG) + non staggered refresh */ + /* 31:26 25 23 20 19 18 16 */ + /* 111101 00 111 0 0 00 1 */ + + /* refresh count=0x200 + phy interleave disable (only one bank) + virt interleave enable */ + /* 15 14 13:0 */ + /* 1 0 0x200 */ + +#define CFG_DEV0_SPACE CFG_DEV_BASE +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) + +/*----------------------------------------------------------------------- + * PCI stuff + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 + + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ + +#define CFG_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ +#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +#define CFG_ENV_ADDR (0xfff80000 - CFG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ + +#define CFG_L2 + +#ifdef CONFIG_750CX +#define L2_INIT 0 +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/*------------------------------------------------------------------------ + * Real time clock + */ +#define CONFIG_RTC_DS1302 + + +/*------------------------------------------------------------------------ + * Galileo I2C driver + */ +#define CONFIG_GT_I2C + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_BOARD_ASM_INIT 1 + +#endif /* __CONFIG_H */ diff --git a/include/config_hymod.h b/include/config_hymod.h index 93abbb6..c15e144 100644 --- a/include/config_hymod.h +++ b/include/config_hymod.h @@ -140,6 +140,7 @@ CFG_CMD_ELF | \ CFG_CMD_FDC | \ CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ CFG_CMD_PCMCIA | \ CFG_CMD_PCI | \ diff --git a/include/galileo/core.h b/include/galileo/core.h index b110fba..f8deba3 100644 --- a/include/galileo/core.h +++ b/include/galileo/core.h @@ -83,6 +83,15 @@ extern unsigned int INTERNAL_REG_BASE_ADDR; #define _15M 0x00f00000 #define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + typedef enum _bool{false,true} bool; /* Little to Big endian conversion macros */ @@ -119,6 +128,11 @@ typedef enum _bool{false,true} bool; #define NONE_CACHEABLE 0x00000000 #define CACHEABLE 0x00000000 +/* 750 cache line */ +#define CACHE_LINE_SIZE 32 +#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) +#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) + /* Read/Write to/from GT`s internal registers */ #define GT_REG_READ(offset, pData) \ *pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h index 12b3a8b..1ea5f1c 100644 --- a/include/galileo/gt64260R.h +++ b/include/galileo/gt64260R.h @@ -103,22 +103,22 @@ /* CPU Access Protect */ /****************************************/ -#define CPU_LOW_PROTECT_ADDRESS_0 0X180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0X188 -#define CPU_LOW_PROTECT_ADDRESS_1 0X190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0X198 -#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8 -#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8 +#define CPU_LOW_PROTECT_ADDRESS_0 0x180 +#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 +#define CPU_LOW_PROTECT_ADDRESS_1 0x190 +#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 +#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 +#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 +#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 +#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 +#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 +#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 +#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 +#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 +#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 +#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 +#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 +#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 /****************************************/ @@ -156,7 +156,7 @@ #define X_1_COMMAND_ID 0x378 #define WRITE_DATA_LOW 0x3c0 #define WRITE_DATA_HIGH 0x3c8 -#define WRITE_BYTE_ENABLE 0X3e0 +#define WRITE_BYTE_ENABLE 0x3e0 #define READ_DATA_LOW 0x3d0 #define READ_DATA_HIGH 0x3d8 #define READ_ID 0x3e8 @@ -168,31 +168,32 @@ /****************************************/ -/* SDRAM Configuration */ +/* SDRAM Configuration */ /****************************************/ -#define SDRAM_CONFIGURATION 0x448 -#define SDRAM_OPERATION_MODE 0x474 -#define SDRAM_ADDRESS_DECODE 0x47C -#define SDRAM_UMA_CONTROL 0x4a4 -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac -#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 -#define SDRAM_TIMING 0x4b4 + +#define SDRAM_CONFIGURATION 0x448 +#define SDRAM_OPERATION_MODE 0x474 +#define SDRAM_ADDRESS_DECODE 0x47c +#define SDRAM_UMA_CONTROL 0x4a4 +#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 +#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac +#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 +#define SDRAM_TIMING 0x4b4 /****************************************/ -/* SDRAM Parameters */ +/* SDRAM Parameters */ /****************************************/ -#define SDRAM_BANK0PARAMETERS 0x44C -#define SDRAM_BANK1PARAMETERS 0x450 -#define SDRAM_BANK2PARAMETERS 0x454 -#define SDRAM_BANK3PARAMETERS 0x458 +#define SDRAM_BANK0PARAMETERS 0x44C +#define SDRAM_BANK1PARAMETERS 0x450 +#define SDRAM_BANK2PARAMETERS 0x454 +#define SDRAM_BANK3PARAMETERS 0x458 /****************************************/ -/* SDRAM Error Report */ +/* SDRAM Error Report */ /****************************************/ #define SDRAM_ERROR_DATA_LOW 0x484 @@ -205,7 +206,7 @@ /****************************************/ -/* SDunit Debug (for internal use) */ +/* SDunit Debug (for internal use) */ /****************************************/ #define X0_ADDRESS 0x500 @@ -258,7 +259,7 @@ /* DMA Record */ /****************************************/ -#define CHANNEL0_DMA_BYTE_COUNT 0x800 +#define CHANNEL0_DMA_BYTE_COUNT 0x800 #define CHANNEL1_DMA_BYTE_COUNT 0x804 #define CHANNEL2_DMA_BYTE_COUNT 0x808 #define CHANNEL3_DMA_BYTE_COUNT 0x80C @@ -556,25 +557,25 @@ #define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 #define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 #define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10 +#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 #define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 #define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20 +#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 #define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 #define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30 +#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 #define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 #define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40 +#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 #define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 #define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50 +#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 #define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 #define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60 +#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 #define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 #define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70 +#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 #define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 #define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 #define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 @@ -587,25 +588,25 @@ #define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 #define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 #define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90 +#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 #define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 #define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0 +#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 #define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 #define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0 +#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 #define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 #define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0 +#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 #define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 #define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0 +#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 #define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 #define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0 +#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 #define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 #define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0 +#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 #define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 #define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 @@ -687,7 +688,100 @@ #define L_SLAVE_READ_ID 0x1d64 /****************************************/ -/* Interrupts */ +/* PCI Configuration Function 0 */ +/****************************************/ + +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C +#define PCI_SCS_0_BASE_ADDRESS 0x010 +#define PCI_SCS_1_BASE_ADDRESS 0x014 +#define PCI_SCS_2_BASE_ADDRESS 0x018 +#define PCI_SCS_3_BASE_ADDRESS 0x01C +#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 +#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 +#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C +#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define PCI_VPD_ADDRESS 0x048 +#define PCI_VPD_DATA 0x04c +#define PCI_MSI_MESSAGE_CONTROL 0x050 +#define PCI_MSI_MESSAGE_ADDRESS 0x054 +#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 +#define PCI_MSI_MESSAGE_DATA 0x05c +#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 + +/****************************************/ +/* PCI Configuration Function 1 */ +/****************************************/ + +#define PCI_CS_0_BASE_ADDRESS 0x110 +#define PCI_CS_1_BASE_ADDRESS 0x114 +#define PCI_CS_2_BASE_ADDRESS 0x118 +#define PCI_CS_3_BASE_ADDRESS 0x11c +#define PCI_BOOTCS_BASE_ADDRESS 0x120 + +/****************************************/ +/* PCI Configuration Function 2 */ +/****************************************/ + +#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 +#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 +#define PCI_P2P_I_O_BASE_ADDRESS 0x218 +#define PCI_CPU_BASE_ADDRESS 0x21c + +/****************************************/ +/* PCI Configuration Function 4 */ +/****************************************/ + +#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 +#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 +#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 +#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 + + +/****************************************/ +/* PCI Configuration Function 5 */ +/****************************************/ + +#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 +#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 +#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 +#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 + + +/****************************************/ +/* PCI Configuration Function 6 */ +/****************************************/ + +#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 +#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 +#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 +#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c +#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 +#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 + +/****************************************/ +/* PCI Configuration Function 7 */ +/****************************************/ + +#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 +#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c +#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 +#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 + +/****************************************/ +/* Interrupts */ /****************************************/ #define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 @@ -733,34 +827,34 @@ #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0X1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0X1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0X1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0X1C1C -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0X1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0X1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0X1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0X1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0X1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0X1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0X1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0X1C44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0X1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0X1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C7C +#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 +#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 +#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 +#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C +#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 +#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 +#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C /****************************************/ /* Communication Unit Registers */ /****************************************/ -#define ETHERNET_0_ADDRESS_CONTROL_LOW +#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 #define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 #define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 #define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c @@ -787,18 +881,12 @@ #define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c #define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 #define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4 -#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 +#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 +#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 +#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 +#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc +#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 +#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 #define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 #define SERIAL_INIT_LAST_DATA 0xf324 #define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 diff --git a/include/galileo/memory.h b/include/galileo/memory.h index 4aef2e1..d12dfcb 100644 --- a/include/galileo/memory.h +++ b/include/galileo/memory.h @@ -59,17 +59,8 @@ unsigned int memoryGetDeviceSize(DEVICE device); unsigned int memoryGetDeviceWidth(DEVICE device); /* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ -bool memoryMapBank0(unsigned int bank0Base,unsigned int bank0Length); -bool memoryMapBank1(unsigned int bank1Base,unsigned int bank1Length); -bool memoryMapBank2(unsigned int bank2Base,unsigned int bank2Length); -bool memoryMapBank3(unsigned int bank3Base,unsigned int bank3Length); -/* when given base Address and size Set new BAR for CS_X. (X = 0,1,2,3 or BOOT*/ -bool memoryMapDevice0Space(unsigned int device0Base,unsigned int device0Length); -bool memoryMapDevice1Space(unsigned int device1Base,unsigned int device1Length); -bool memoryMapDevice2Space(unsigned int device2Base,unsigned int device2Length); -bool memoryMapDevice3Space(unsigned int device3Base,unsigned int device3Length); -bool memoryMapDeviceBootSpace(unsigned int bootDeviceBase, - unsigned int bootDeviceLength); +bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); +bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); /* Change the Internal Register Base Address to a new given Address. */ bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); diff --git a/include/galileo/pci.h b/include/galileo/pci.h index 92f7e9e..2fa67d6 100644 --- a/include/galileo/pci.h +++ b/include/galileo/pci.h @@ -8,6 +8,11 @@ /* includes */ #include"core.h" +#include"memory.h" + +/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ +#define PCI_MAX_DEVICES 22 + /* Macros */ @@ -15,58 +20,36 @@ the PCI to become: MASTER, response to MEMORY transactions , response to IO transactions or TWO both MEMORY_IO transactions. Those configuration are for both PCI0 and PCI1. */ -#define PCI0_MASTER_ENABLE(deviceNumber) pci0WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ - pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI0_MASTER_DISABLE(deviceNumber) pci0WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ - pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI1_MASTER_ENABLE(deviceNumber) pci1WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ - pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI1_MASTER_DISABLE(deviceNumber) pci1WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ - pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) -#define PCI0_MEMORY_ENABLE(deviceNumber) pci0WriteConfigReg( \ +#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \ - pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) -#define PCI1_MEMORY_ENABLE(deviceNumber) pci1WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \ - pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI0_IO_ENABLE(deviceNumber) pci0WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \ - pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI1_IO_ENABLE(deviceNumber) pci1WriteConfigReg( \ +#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \ - pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) -#define PCI0_SLAVE_ENABLE(deviceNumber) pci0WriteConfigReg( \ +#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \ - pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) -#define PCI1_SLAVE_ENABLE(deviceNumber) pci1WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \ - pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI0_DISABLE(deviceNumber) pci0WriteConfigReg( \ +#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \ PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \ - pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber)) + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber)) -#define PCI1_DISABLE(deviceNumber) pci1WriteConfigReg( \ - PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \ - pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber)) +#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ + pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) + +#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ + pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) #define MASTER_ENABLE BIT2 #define MEMORY_ENABLE BIT1 #define I_O_ENABLE BIT0 #define SELF 32 + /* Agent on the PCI bus may have up to 6 BARS. */ #define BAR0 0x10 #define BAR1 0x14 @@ -74,14 +57,22 @@ #define BAR3 0x1c #define BAR4 0x20 #define BAR5 0x24 +#define BAR_SEL_MEM_IO BIT0 +#define BAR_MEM_TYPE_32_BIT NO_BIT +#define BAR_MEM_TYPE_BELOW_1M BIT1 +#define BAR_MEM_TYPE_64_BIT BIT2 +#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2) +#define BAR_MEM_TYPE_MASK (BIT1 | BIT2) +#define BAR_PREFETCHABLE BIT3 +#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3) /* Defines for the access regions. */ #define PREFETCH_ENABLE BIT12 #define PREFETCH_DISABLE NO_BIT #define DELAYED_READ_ENABLE BIT13 -#define CACHING_ENABLE BIT14 -/* aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define AGGRESIVE_PREFETCH BIT16 +// #define CACHING_ENABLE BIT14 +/* aggressive prefetch: PCI slave prefetch two burst in advance*/ +#define AGGRESSIVE_PREFETCH BIT16 /* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ #define READ_LINE_AGGRESSIVE_PREFETCH BIT17 /* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ @@ -92,7 +83,7 @@ #define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ #define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ #define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ -#define PCI_WORD_SWAP BIT24 | BIT25 /* Bits[25:24] = 11 */ +#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ #define PCI_ACCESS_PROTECT BIT28 #define PCI_WRITE_PROTECT BIT29 @@ -110,34 +101,29 @@ typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} PCI_SNOOP_REGION; -typedef struct pciDevice -{ - char type[20]; +typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; +typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, + PCI_REGION2,PCI_REGION3, + PCI_IO} + PCI_REGION; + +typedef struct pciBar { + unsigned int detectBase; + unsigned int base; + unsigned int size; + unsigned int type; +} PCI_BAR; + +typedef struct pciDevice { + PCI_HOST host; + char type[40]; unsigned int deviceNum; unsigned int venID; - unsigned int deviceID; - unsigned int bar0Base; - unsigned int bar0Size; - unsigned int bar0Type; - unsigned int bar1Base; - unsigned int bar1Size; - unsigned int bar1Type; - unsigned int bar2Base; - unsigned int bar2Size; - unsigned int bar2Type; - unsigned int bar3Base; - unsigned int bar3Size; - unsigned int bar3Type; - unsigned int bar4Base; - unsigned int bar4Size; - unsigned int bar4Type; - unsigned int bar5Base; - unsigned int bar5Size; - unsigned int bar5Type; + unsigned int deviceID; + PCI_BAR bar[6]; } PCI_DEVICE; -typedef struct pciSelfBars -{ +typedef struct pciSelfBars { unsigned int SCS0Base; unsigned int SCS0Size; unsigned int SCS1Base; @@ -167,100 +153,47 @@ typedef struct pciSelfBars unsigned int CPUBase; unsigned int CPUSize; } PCI_SELF_BARS; + /* read/write configuration registers on local PCI bus. */ -void pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum, - unsigned int data); -void pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum, - unsigned int data); -unsigned int pci0ReadConfigReg (unsigned int regOffset, - unsigned int pciDevNum); -unsigned int pci1ReadConfigReg (unsigned int regOffset, - unsigned int pciDevNum); +void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data); +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum); + /* read/write configuration registers on another PCI bus. */ -void pci0OverBridgeWriteConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -void pci1OverBridgeWriteConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -unsigned int pci0OverBridgeReadConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); -unsigned int pci1OverBridgeReadConfigReg(unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); +void pciOverBridgeWriteConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum,unsigned int data); +unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum); + /* Performs full scane on both PCI and returns all detail possible on the agents which exist on the bus. */ -void pci0ScanDevices(PCI_DEVICE *pci0Detect,unsigned int numberOfElment); -void pci1ScanDevices(PCI_DEVICE *pci1Detect,unsigned int numberOfElment); +void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect, + unsigned int numberOfElment); /* Master`s memory space */ - -void pci0MapIOspace(unsigned int pci0IoBase,unsigned int pci0IoLength); -void pci1MapIOspace(unsigned int pci1IoBase,unsigned int pci1IoLength); -void pci0MapMemory0space(unsigned int pci0Mem0Base, - unsigned int pci0Mem0Length); -void pci1MapMemory0space(unsigned int pci1Mem0Base, - unsigned int pci1Mem0Length); -void pci0MapMemory1space(unsigned int pci0Mem1Base, - unsigned int pci0Mem1Length); -void pci1MapMemory1space(unsigned int pci1Mem1Base, - unsigned int pci1Mem1Length); -void pci0MapMemory2space(unsigned int pci0Mem2Base, - unsigned int pci0Mem2Length); -void pci1MapMemory2space(unsigned int pci1Mem2Base, - unsigned int pci1Mem2Length); -void pci0MapMemory3space(unsigned int pci0Mem3Base, - unsigned int pci0Mem3Length); -void pci1MapMemory3space(unsigned int pci1Mem3Base, - unsigned int pci1Mem3Length); - -unsigned int pci0GetIOspaceBase(void); -unsigned int pci0GetIOspaceSize(void); -unsigned int pci0GetMemory0Base(void); -unsigned int pci0GetMemory0Size(void); -unsigned int pci0GetMemory1Base(void); -unsigned int pci0GetMemory1Size(void); -unsigned int pci0GetMemory2Base(void); -unsigned int pci0GetMemory2Size(void); -unsigned int pci0GetMemory3Base(void); -unsigned int pci0GetMemory3Size(void); - -unsigned int pci1GetIOspaceBase(void); -unsigned int pci1GetIOspaceSize(void); -unsigned int pci1GetMemory0Base(void); -unsigned int pci1GetMemory0Size(void); -unsigned int pci1GetMemory1Base(void); -unsigned int pci1GetMemory1Size(void); -unsigned int pci1GetMemory2Base(void); -unsigned int pci1GetMemory2Size(void); -unsigned int pci1GetMemory3Base(void); -unsigned int pci1GetMemory3Size(void); +bool pciMapSpace(PCI_HOST host, PCI_REGION region, + unsigned int remapBase, + unsigned int deviceBase, + unsigned int deviceLength); +unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); +unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); /* Slave`s memory space */ +void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, + unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); +#if 0 // GARBAGE routines - dont use till they get cleaned up void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars); void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars); void pci0MapInternalRegSpace(unsigned int pci0InternalBase); void pci1MapInternalRegSpace(unsigned int pci1InternalBase); void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase); void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase); -void pci0MapMemoryBank0(unsigned int pci0Dram0Base, - unsigned int pci0Dram0Size); -void pci1MapMemoryBank0(unsigned int pci1Dram0Base, - unsigned int pci1Dram0Size); -void pci0MapMemoryBank1(unsigned int pci0Dram1Base, - unsigned int pci0Dram1Size); -void pci1MapMemoryBank1(unsigned int pci1Dram1Base, - unsigned int pci1Dram1Size); -void pci0MapMemoryBank2(unsigned int pci0Dram2Base, - unsigned int pci0Dram2Size); -void pci1MapMemoryBank2(unsigned int pci1Dram2Base, - unsigned int pci1Dram2Size); -void pci0MapMemoryBank3(unsigned int pci0Dram3Base, - unsigned int pci0Dram3Size); -void pci1MapMemoryBank3(unsigned int pci1Dram3Base, - unsigned int pci1Dram3Size); void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, unsigned int pci0Dev0Length); void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, @@ -296,160 +229,56 @@ void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs); void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs); +#endif + +/* PCI region options */ -bool pci0SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, - unsigned int baseAddress,unsigned int regionLength); +bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength); -bool pci1SetRegionFeatures(PCI_ACCESS_REGIONS region,unsigned int features, - unsigned int baseAddress,unsigned int regionLength); -void pci0DisableAccessRegion(PCI_ACCESS_REGIONS region); -void pci1DisableAccessRegion(PCI_ACCESS_REGIONS region); +void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); /* PCI arbiter */ -bool pci0ArbiterEnable(void); -bool pci1ArbiterEnable(void); -bool pci0ArbiterDisable(void); -bool pci1ArbiterDisable(void); -bool pci0SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent, +bool pciArbiterEnable(PCI_HOST host); +bool pciArbiterDisable(PCI_HOST host); +bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, PCI_AGENT_PRIO externalAgent0, PCI_AGENT_PRIO externalAgent1, PCI_AGENT_PRIO externalAgent2, PCI_AGENT_PRIO externalAgent3, PCI_AGENT_PRIO externalAgent4, PCI_AGENT_PRIO externalAgent5); -bool pci1SetArbiterAgentsPriority(PCI_AGENT_PRIO internalAgent, +bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, PCI_AGENT_PRIO externalAgent0, PCI_AGENT_PRIO externalAgent1, PCI_AGENT_PRIO externalAgent2, PCI_AGENT_PRIO externalAgent3, PCI_AGENT_PRIO externalAgent4, PCI_AGENT_PRIO externalAgent5); -bool pci0ParkingDisable(PCI_AGENT_PARK internalAgent, +bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, PCI_AGENT_PARK externalAgent0, PCI_AGENT_PARK externalAgent1, PCI_AGENT_PARK externalAgent2, PCI_AGENT_PARK externalAgent3, PCI_AGENT_PARK externalAgent4, PCI_AGENT_PARK externalAgent5); -bool pci1ParkingDisable(PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); -bool pci0EnableBrokenAgentDetection(unsigned char brokenValue); -bool pci1EnableBrokenAgentDetection(unsigned char brokenValue); -bool pci0DisableBrokenAgentDetection(void); -bool pci1DisableBrokenAgentDetection(void); +bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); +bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); /* PCI-to-PCI (P2P) */ -bool pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum); -bool pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum); +bool pciP2PConfig(PCI_HOST host, + unsigned int SecondBusLow,unsigned int SecondBusHigh, + unsigned int busNum,unsigned int devNum); /* PCI Cache-coherency */ -bool pci0SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); -bool pci1SetRegionSnoopMode(PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, +bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, unsigned int baseAddress, unsigned int regionLength); -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0X04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 -#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 -#define PCI_CPU_BASE_ADDRESS 0x21c - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 +PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev); #endif /* __INCpcih */ diff --git a/include/jffs2/compr_rubin.h b/include/jffs2/compr_rubin.h new file mode 100644 index 0000000..b6815d8 --- /dev/null +++ b/include/jffs2/compr_rubin.h @@ -0,0 +1,11 @@ +/* Rubin encoder/decoder header */ +/* work started at : aug 3, 1994 */ +/* last modification : aug 15, 1994 */ +/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */ + +#define RUBIN_REG_SIZE 16 +#define UPPER_BIT_RUBIN (((long) 1)<<(RUBIN_REG_SIZE-1)) +#define LOWER_BITS_RUBIN ((((long) 1)<<(RUBIN_REG_SIZE-1))-1) + +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h new file mode 100644 index 0000000..5ebd214 --- /dev/null +++ b/include/jffs2/jffs2.h @@ -0,0 +1,208 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $ + * + */ + +#ifndef __LINUX_JFFS2_H__ +#define __LINUX_JFFS2_H__ + +#include +#include + +#define JFFS2_SUPER_MAGIC 0x72b6 + +/* Values we may expect to find in the 'magic' field */ +#define JFFS2_OLD_MAGIC_BITMASK 0x1984 +#define JFFS2_MAGIC_BITMASK 0x1985 +#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */ +#define JFFS2_EMPTY_BITMASK 0xffff +#define JFFS2_DIRTY_BITMASK 0x0000 + +/* We only allow a single char for length, and 0xFF is empty flash so + we don't want it confused with a real length. Hence max 254. +*/ +#define JFFS2_MAX_NAME_LEN 254 + +/* How small can we sensibly write nodes? */ +#define JFFS2_MIN_DATA_LEN 128 + +#define JFFS2_COMPR_NONE 0x00 +#define JFFS2_COMPR_ZERO 0x01 +#define JFFS2_COMPR_RTIME 0x02 +#define JFFS2_COMPR_RUBINMIPS 0x03 +#define JFFS2_COMPR_COPY 0x04 +#define JFFS2_COMPR_DYNRUBIN 0x05 +#define JFFS2_COMPR_ZLIB 0x06 +#define JFFS2_NUM_COMPR 7 + +/* Compatibility flags. */ +#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ +#define JFFS2_NODE_ACCURATE 0x2000 +/* INCOMPAT: Fail to mount the filesystem */ +#define JFFS2_FEATURE_INCOMPAT 0xc000 +/* ROCOMPAT: Mount read-only */ +#define JFFS2_FEATURE_ROCOMPAT 0x8000 +/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000 +/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000 + +#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1) +#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2) +#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) + +// Maybe later... +//#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) +//#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) + +/* Same as the non_ECC versions, but with extra space for real + * ECC instead of just the checksum. For use on NAND flash + */ +//#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) +//#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) + +#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at + mount time, don't wait for it to + happen later */ +#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific + compression type */ + + +struct jffs2_unknown_node +{ + /* All start like this */ + __u16 magic; + __u16 nodetype; + __u32 totlen; /* So we can skip over nodes we don't grok */ + __u32 hdr_crc; +} __attribute__((packed)); + +struct jffs2_raw_dirent +{ + __u16 magic; + __u16 nodetype; /* == JFFS_NODETYPE_DIRENT */ + __u32 totlen; + __u32 hdr_crc; + __u32 pino; + __u32 version; + __u32 ino; /* == zero for unlink */ + __u32 mctime; + __u8 nsize; + __u8 type; + __u8 unused[2]; + __u32 node_crc; + __u32 name_crc; + __u8 name[0]; +} __attribute__((packed)); + +/* The JFFS2 raw inode structure: Used for storage on physical media. */ +/* The uid, gid, atime, mtime and ctime members could be longer, but + are left like this for space efficiency. If and when people decide + they really need them extended, it's simple enough to add support for + a new type of raw node. +*/ +struct jffs2_raw_inode +{ + __u16 magic; /* A constant magic number. */ + __u16 nodetype; /* == JFFS_NODETYPE_INODE */ + __u32 totlen; /* Total length of this node (inc data, etc.) */ + __u32 hdr_crc; + __u32 ino; /* Inode number. */ + __u32 version; /* Version number. */ + __u32 mode; /* The file's type or mode. */ + __u16 uid; /* The file's owner. */ + __u16 gid; /* The file's group. */ + __u32 isize; /* Total resultant size of this inode (used for truncations) */ + __u32 atime; /* Last access time. */ + __u32 mtime; /* Last modification time. */ + __u32 ctime; /* Change time. */ + __u32 offset; /* Where to begin to write. */ + __u32 csize; /* (Compressed) data size */ + __u32 dsize; /* Size of the node's data. (after decompression) */ + __u8 compr; /* Compression algorithm used */ + __u8 usercompr; /* Compression algorithm requested by the user */ + __u16 flags; /* See JFFS2_INO_FLAG_* */ + __u32 data_crc; /* CRC for the (compressed) data. */ + __u32 node_crc; /* CRC for the raw inode (excluding data) */ +// __u8 data[dsize]; +} __attribute__((packed)); + +union jffs2_node_union { + struct jffs2_raw_inode i; + struct jffs2_raw_dirent d; + struct jffs2_unknown_node u; +} __attribute__((packed)); + +enum + { + DT_UNKNOWN = 0, +# define DT_UNKNOWN DT_UNKNOWN + DT_FIFO = 1, +# define DT_FIFO DT_FIFO + DT_CHR = 2, +# define DT_CHR DT_CHR + DT_DIR = 4, +# define DT_DIR DT_DIR + DT_BLK = 6, +# define DT_BLK DT_BLK + DT_REG = 8, +# define DT_REG DT_REG + DT_LNK = 10, +# define DT_LNK DT_LNK + DT_SOCK = 12, +# define DT_SOCK DT_SOCK + DT_WHT = 14 +# define DT_WHT DT_WHT + }; + + +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); + +void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, u32 + srclen, u32 destlen); +void rubin_do_decompress(unsigned char *bits, unsigned char *in, unsigned char + *page_out, __u32 destlen); +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); +long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, + __u32 srclen, __u32 destlen); + + + + + +#endif /* __LINUX_JFFS2_H__ */ diff --git a/include/jffs2/jffs2_1pass.h b/include/jffs2/jffs2_1pass.h new file mode 100644 index 0000000..5bc3e66 --- /dev/null +++ b/include/jffs2/jffs2_1pass.h @@ -0,0 +1,3 @@ +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h new file mode 100644 index 0000000..714e23b --- /dev/null +++ b/include/jffs2/load_kernel.h @@ -0,0 +1,67 @@ +#ifndef load_kernel_h +#define load_kernel_h +/*------------------------------------------------------------------------- + * Filename: load_kernel.h + * Version: $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: header for load kernel modules + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* this struct is very similar to mtd_info */ +struct part_info { + u32 size; // Total size of the Partition + + /* "Major" erase size for the device. Naïve users may take this + * to be the only erase size available, or may use the more detailed + * information below if they desire + */ + u32 erasesize; + + /* Where in memory does this partition start? */ + char *offset; +}; + +struct kernel_loader { + + /* Return true if there is a kernel contained at src */ + int (* check_magic)(struct part_info *part); + + /* load the kernel from the partition part to dst, return the number + * of bytes copied if successful, zero if not */ + u32 (* load_kernel)(u32 *dst, struct part_info *part, const char *kernel_filename); + + /* A brief description of the module (ie, "cramfs") */ + char *name; +}; + +#define ldr_strlen strlen +#define ldr_strncmp strncmp +#define ldr_memcpy memcpy +#define putstr(x) printf("%s", x) +#define mmalloc malloc +#define UDEBUG printf + +#define putnstr(str, size) printf("%*.*s", size, size, str) +#define ldr_output_string(x) puts(x) +#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y) +#define led_blink(x, y, z, a) + +#endif /* load_kernel_h */ diff --git a/include/jffs2/mini_inflate.h b/include/jffs2/mini_inflate.h new file mode 100644 index 0000000..1157f98 --- /dev/null +++ b/include/jffs2/mini_inflate.h @@ -0,0 +1,82 @@ +/*------------------------------------------------------------------------- + * Filename: mini_inflate.h + * Version: $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Mini deflate implementation + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +typedef __SIZE_TYPE__ size; + +#define NO_ERROR 0 +#define COMP_UNKNOWN 1 /* The specififed bytype is invalid */ +#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */ +#define TOO_MANY_BITS 3 /* pull_bits was passed an argument that is too + * large */ + +/* This struct represents an entire huffman code set. It has various lookup + * tables to speed decoding */ +struct huffman_set { + int bits; /* maximum bit length */ + int num_symbols; /* Number of symbols this code can represent */ + int *lengths; /* The bit length of symbols */ + int *symbols; /* All of the symbols, sorted by the huffman code */ + int *count; /* the number of codes of this bit length */ + int *first; /* the first code of this bit length */ + int *pos; /* the symbol that first represents (in the symbols + * array) */ +}; + +struct bitstream { + unsigned char *data; /* increments as we move from byte to byte */ + unsigned char bit; /* 0 to 7 */ + void *(*memcpy)(void *, const void *, size); + unsigned long decoded; /* The number of bytes decoded */ + int error; + + int distance_count[16]; + int distance_first[16]; + int distance_pos[16]; + int distance_lengths[32]; + int distance_symbols[32]; + + int code_count[8]; + int code_first[8]; + int code_pos[8]; + int code_lengths[19]; + int code_symbols[19]; + + int length_count[16]; + int length_first[16]; + int length_pos[16]; + int length_lengths[288]; + int length_symbols[288]; + + struct huffman_set codes; + struct huffman_set lengths; + struct huffman_set distance; +}; + +#define NO_COMP 0 +#define FIXED_COMP 1 +#define DYNAMIC_COMP 2 + +long decompress_block(unsigned char *dest, unsigned char *source, + void *(*inflate_memcpy)(void *dest, const void *src, size n)); diff --git a/include/linux/stat.h b/include/linux/stat.h new file mode 100644 index 0000000..abec978 --- /dev/null +++ b/include/linux/stat.h @@ -0,0 +1,67 @@ +#ifndef _LINUX_STAT_H +#define _LINUX_STAT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __S_IFMT 0170000 /* type of file */ +#define __S_IFDIR 0040000 /* directory */ +#define __S_IFCHR 0020000 /* character special */ +#define __S_IFBLK 0060000 /* block special */ +#define __S_IFREG 0100000 /* regular */ +#define __S_IFLNK 0120000 /* symbolic link */ +#define __S_IFSOCK 0140000 /* named socket */ +#define __S_IFIFO 0010000 /* fifo */ + +#define __S_ISLNK(m) (((m)&_IFMT) == _IFLNK) +#define __S_ISSOCK(m) (((m)&_IFMT) == _IFSOCK) + +#define __S_ISUID 0004000 /* set user id on execution */ +#define __S_ISGID 0002000 /* set group id on execution */ +#define __S_ISVTX 0001000 /* save swapped text even after use */ + +#define __S_IRWXU 0000700 /* rwx for owner */ +#define __S_IRUSR 0000400 /* read permission for owner */ +#define __S_IWUSR 0000200 /* write permission for owner */ +#define __S_IXUSR 0000100 /* execute/search permission for owner */ +#define __S_IRWXG 0000070 /* rwx for group */ +#define __S_IRGRP 0000040 /* read permission for group */ +#define __S_IWGRP 0000020 /* write permission for grougroup */ +#define __S_IXGRP 0000010 /* execute/search permission for group */ +#define __S_IRWXO 0000007 /* rwx for other */ +#define __S_IROTH 0000004 /* read permission for other */ +#define __S_IWOTH 0000002 /* write permission for other */ +#define __S_IXOTH 0000001 /* execute/search permission for other */ + +struct stat { + mode_t st_mode; /* ownership/protection */ + ino_t st_ino; /* file id */ + dev_t st_dev; /* file system id */ + dev_t st_rdev; + nlink_t st_nlink; /* number of links */ + uid_t st_uid; /* user id */ + gid_t st_gid; /* group id */ + off_t st_size; /* file size in # of bytes */ + time_t st_atime; /* time file was last accessed */ + time_t st_mtime; /* time file was last modified */ + time_t st_ctime; /* time file status was last changed */ + u_long st_blksize; /* block size */ + u_long st_blocks; /* file size in # of blocks */ + u_long st_attrib; + + u_long st_fYear; + u_long st_fMonth; + u_long st_fDay; + u_long st_fHour; + u_long st_fMinute; + u_long st_fSecond; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/linux/time.h b/include/linux/time.h new file mode 100644 index 0000000..c74c7da --- /dev/null +++ b/include/linux/time.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_TIME_H +#define _LINUX_TIME_H + +#include + +#define _DEFUN(a,b,c) a(c) +#define _CONST const +#define _AND , + +#define _REENT_ONLY + +#define SECSPERMIN 60L +#define MINSPERHOUR 60L +#define HOURSPERDAY 24L +#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) +#define SECSPERDAY (SECSPERHOUR * HOURSPERDAY) +#define DAYSPERWEEK 7 +#define MONSPERYEAR 12 + +#define YEAR_BASE 1900 +#define EPOCH_YEAR 1970 +#define EPOCH_WDAY 4 + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) + + +/* Used by other time functions. */ +struct tm { + int tm_sec; /* Seconds. [0-60] (1 leap second) */ + int tm_min; /* Minutes. [0-59] */ + int tm_hour; /* Hours. [0-23] */ + int tm_mday; /* Day. [1-31] */ + int tm_mon; /* Month. [0-11] */ + int tm_year; /* Year - 1900. */ + int tm_wday; /* Day of week. [0-6] */ + int tm_yday; /* Days in year.[0-365] */ + int tm_isdst; /* DST. [-1/0/1]*/ + +# ifdef __USE_BSD + long int tm_gmtoff; /* Seconds east of UTC. */ + __const char *tm_zone; /* Timezone abbreviation. */ +# else + long int __tm_gmtoff; /* Seconds east of UTC. */ + __const char *__tm_zone; /* Timezone abbreviation. */ +# endif +}; + +static inline char * +_DEFUN (asctime_r, (tim_p, result), + _CONST struct tm *tim_p _AND + char *result) +{ + static _CONST char day_name[7][3] = { + "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" + }; + static _CONST char mon_name[12][3] = { + "Jan", "Feb", "Mar", "Apr", "May", "Jun", + "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" + }; + + sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n", + day_name[tim_p->tm_wday], + mon_name[tim_p->tm_mon], + tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min, + tim_p->tm_sec, 1900 + tim_p->tm_year); + return result; +} + +static inline struct tm * +_DEFUN (localtime_r, (tim_p, res), + _CONST time_t * tim_p _AND + struct tm *res) +{ + static _CONST int mon_lengths[2][MONSPERYEAR] = { + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, + {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31} + } ; + + static _CONST int year_lengths[2] = { + 365, + 366 + } ; + + long days, rem; + int y; + int yleap; + _CONST int *ip; + + days = ((long) *tim_p) / SECSPERDAY; + rem = ((long) *tim_p) % SECSPERDAY; + while (rem < 0) + { + rem += SECSPERDAY; + --days; + } + while (rem >= SECSPERDAY) + { + rem -= SECSPERDAY; + ++days; + } + + /* compute hour, min, and sec */ + res->tm_hour = (int) (rem / SECSPERHOUR); + rem %= SECSPERHOUR; + res->tm_min = (int) (rem / SECSPERMIN); + res->tm_sec = (int) (rem % SECSPERMIN); + + /* compute day of week */ + if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0) + res->tm_wday += DAYSPERWEEK; + + /* compute year & day of year */ + y = EPOCH_YEAR; + if (days >= 0) + { + for (;;) + { + yleap = isleap(y); + if (days < year_lengths[yleap]) + break; + y++; + days -= year_lengths[yleap]; + } + } + else + { + do + { + --y; + yleap = isleap(y); + days += year_lengths[yleap]; + } while (days < 0); + } + + res->tm_year = y - YEAR_BASE; + res->tm_yday = days; + ip = mon_lengths[yleap]; + for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon) + days -= ip[res->tm_mon]; + res->tm_mday = days + 1; + + /* set daylight saving time flag */ + res->tm_isdst = -1; + + return (res); +} + +static inline char * +_DEFUN (ctime_r, (tim_p, result), + _CONST time_t * tim_p _AND + char * result) + +{ + struct tm tm; + return asctime_r (localtime_r (tim_p, &tm), result); +} + +#endif diff --git a/include/mpc74xx.h b/include/mpc74xx.h index 3052916..f36392e 100644 --- a/include/mpc74xx.h +++ b/include/mpc74xx.h @@ -86,10 +86,10 @@ #define BATU_VP 0x00000001 #define BATU_INVALID 0x00000000 -#define BATL_WRITETHROUGH 0x00000080 -#define BATL_CACHEINHIBIT 0x00000040 -#define BATL_COHERENT 0x00000020 -#define BATL_GUARDED 0x00000010 +#define BATL_WRITETHROUGH 0x00000040 /* W */ +#define BATL_CACHEINHIBIT 0x00000020 /* I */ +#define BATL_COHERENT 0x00000010 /* M */ +#define BATL_GUARDED 0x00000008 /* G */ #define BATL_NO_ACCESS 0x00000000 #define BATL_RO 0x00000001 diff --git a/include/mpc824x.h b/include/mpc824x.h index 0dc1905..11a3d5a 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -312,7 +312,7 @@ #define MCCR1_ROMNAL_MSK 0xf0000000 #define MCCR1_ROMFAL_SHIFT 23 #define MCCR1_ROMFAL_MSK 0x0f800000 -#define MCCR1_DBUS_SIZE0TO1_SHIFT 21 +#define MCCR1_DBUS_SIZE0 0x00400000 #define MCCR1_BURST 0x00100000 #define MCCR1_MEMGO 0x00080000 #define MCCR1_SREN 0x00040000 diff --git a/include/ppcboot.h b/include/ppcboot.h index 3eb07c6..27322c6 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -152,6 +152,9 @@ typedef struct init_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif +#if defined(CONFIG_EVB64260) + unsigned int mirror_hack[16]; +#endif #if defined(CONFIG_SANDPOINT) void * console_addr; #endif @@ -208,8 +211,10 @@ void inline setenv (char *, char *); defined(CONFIG_DASA_SIM) || \ defined(CONFIG_DU405) || \ defined(CONFIG_ERIC) || \ + defined(CONFIG_EVB64260) || \ defined(CONFIG_MIP405) || \ defined(CONFIG_MOUSSE) || \ + defined(CONFIG_MUSENKI) || \ defined(CONFIG_OCRTC) || \ defined(CONFIG_PIP405) || \ defined(CONFIG_SANDPOINT) || \ @@ -290,6 +295,11 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif +#ifdef CONFIG_RPXCLASSIC +void rpxclassic_init (void); +void board_get_enetaddr (uchar *addr); +#endif + #ifdef CONFIG_MBX /* $(BOARD)/mbx8xx.c */ void mbx_init (void); @@ -482,6 +492,7 @@ int vsprintf(char *buf, const char *fmt, va_list args); /* ppc/crc32.c */ ulong crc32 (ulong, const unsigned char *, uint); +ulong crc32_no_comp (ulong, const unsigned char *, uint); /* common/console.c */ bd_t *bd_ptr ; diff --git a/net/arp.c b/net/arp.c index c36bda4..ae37960 100644 --- a/net/arp.c +++ b/net/arp.c @@ -43,10 +43,13 @@ int ArpTry = 0; static void ArpHandler(uchar *pkt, unsigned dest, unsigned src, unsigned len) { + /* Check if the frame is really an ARP reply */ + if (memcmp (NetServerEther, NetBcastAddr, 6) != 0) { #ifdef DEBUG - printf("Got good ARP - start TFTP\n"); + printf("Got good ARP - start TFTP\n"); #endif - TftpStart (); + TftpStart (); + } } diff --git a/net/bootp.c b/net/bootp.c index 6535434..eb24fd2 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -37,6 +37,10 @@ #define PORT_BOOTPS 67 /* BOOTP server UDP port */ #define PORT_BOOTPC 68 /* BOOTP client UDP port */ +#ifndef CONFIG_DHCP_MIN_EXT_LEN /* minimal length of extension list */ +#define CONFIG_DHCP_MIN_EXT_LEN 64 +#endif + ulong BootpID; int BootpTry; #ifdef CONFIG_BOOTP_RANDOM_DELAY @@ -68,7 +72,7 @@ extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ #endif -#endif +#endif /* CFG_CMD_DHCP */ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) { @@ -110,8 +114,13 @@ void BootpCopyNetParams(Bootp_t *bp) debug ("Bootfile: %s\n", BootFile); - /* Propagate to environment */ - setenv ("bootfile", BootFile); + /* Propagate to environment: + * don't delete exising entry when BOOTP / DHCP reply does + * not contain a new value + */ + if (*BootFile) { + setenv ("bootfile", BootFile); + } } static int truncate_sz (const char *name, int maxlen, int curlen) @@ -264,7 +273,7 @@ static void BootpVendorProcess(u8 *ext, int size) if (NetOurNISDomain[0]) { printf("NetOurNISDomain : %s\n", NetOurNISDomain); } -#endif +#endif /* DEBUG_BOOTP_EXT */ } /* @@ -408,6 +417,12 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, IPaddr_t Req #endif *e++ = 255; /* End of the list */ + /* Pad to minimal length */ +#ifdef CONFIG_DHCP_MIN_EXT_LEN + while ((e - start) <= CONFIG_DHCP_MIN_EXT_LEN) + *e++ = 0; +#endif + return e - start ; } diff --git a/ppc/crc32.c b/ppc/crc32.c index 49e8719..0a6a1f7 100644 --- a/ppc/crc32.c +++ b/ppc/crc32.c @@ -8,6 +8,10 @@ * For conditions of distribution and use, see copyright notice in zlib.h */ +#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */ +#include /* to get command definitions like CFG_CMD_JFFS2 */ +#endif + #include "zlib.h" #define local static @@ -167,3 +171,29 @@ uLong ZEXPORT crc32(crc, buf, len) } while (--len); return crc ^ 0xffffffffL; } + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +/* No ones complement version. JFFS2 (and other things ?) + * don't use ones compliment in their CRC calculations. + */ +uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len) +{ + if (buf == Z_NULL) return 0L; +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + + return crc; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/rtc/Makefile b/rtc/Makefile index 5df2439..a255f11 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk LIB = librtc.a -OBJS = date.o pcf8563.o mpc8xx.o mc146818.o ds174x.o m48t35ax.o mk48t59.o +OBJS = date.o ds1302.o ds174x.o \ + m48t35ax.o mc146818.o mk48t59.o mpc8xx.o pcf8563.o all: $(LIB) diff --git a/rtc/ds1302.c b/rtc/ds1302.c new file mode 100644 index 0000000..857a27b --- /dev/null +++ b/rtc/ds1302.c @@ -0,0 +1,327 @@ +/* + * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip + * + * Rex G. Feany + * + */ + +#include +#include +#include + +#if defined(CONFIG_RTC_DS1302) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +/* GPP Pins */ +#define DATA 0x200 +#define SCLK 0x400 +#define RST 0x800 + +/* Happy Fun Defines(tm) */ +#define RESET rtc_go_low(RST), rtc_go_low(SCLK) +#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK) + +#define CLOCK_HIGH rtc_go_high(SCLK) +#define CLOCK_LOW rtc_go_low(SCLK) + +#define DATA_HIGH rtc_go_high(DATA) +#define DATA_LOW rtc_go_low(DATA) +#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA) + +#undef RTC_DEBUG + +#ifdef RTC_DEBUG +# define DPRINTF(x,args...) printf("ds1302: " x , ##args) +static inline void DUMP(const char *ptr, int num) +{ + while (num--) printf("%x ", *ptr++); + printf("]\n"); +} +#else +# define DPRINTF(x,args...) +# define DUMP(ptr, num) +#endif + +/* time data format for DS1302 */ +struct ds1302_st +{ + unsigned char CH:1; /* clock halt 1=stop 0=start */ + unsigned char sec10:3; + unsigned char sec:4; + + unsigned char zero0:1; + unsigned char min10:3; + unsigned char min:4; + + unsigned char fmt:1; /* 1=12 hour 0=24 hour */ + unsigned char zero1:1; + unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */ + unsigned char hr:4; + + unsigned char zero2:2; + unsigned char date10:2; + unsigned char date:4; + + unsigned char zero3:3; + unsigned char month10:1; + unsigned char month:4; + + unsigned char zero4:5; + unsigned char day:3; /* day of week */ + + unsigned char year10:4; + unsigned char year:4; + + unsigned char WP:1; /* write protect 1=protect 0=unprot */ + unsigned char zero5:7; +}; + +static int ds1302_initted=0; + +/* Pin control */ +static inline void +rtc_go_high(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_VALUE) | mask; + + GT_REG_WRITE(GPP_VALUE, f); +} + +static inline void +rtc_go_low(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_VALUE) & ~mask; + + GT_REG_WRITE(GPP_VALUE, f); +} + +static inline void +rtc_go_input(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask; + + GT_REG_WRITE(GPP_IO_CONTROL, f); +} + +static inline void +rtc_go_output(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask; + + GT_REG_WRITE(GPP_IO_CONTROL, f); +} + +/* Access data in RTC */ + +static void +write_byte(unsigned char b) +{ + int i; + unsigned char mask=1; + + for(i=0;i<8;i++) { + CLOCK_LOW; /* Lower clock */ + (b&mask)?DATA_HIGH:DATA_LOW; /* set data */ + udelay(1); + CLOCK_HIGH; /* latch data with rising clock */ + udelay(1); + mask=mask<<1; + } +} + +static unsigned char +read_byte(void) +{ + int i; + unsigned char mask=1; + unsigned char b=0; + + for(i=0;i<8;i++) { + CLOCK_LOW; + udelay(1); + if (DATA_READ) b|=mask; /* if this bit is high, set in b */ + CLOCK_HIGH; /* clock out next bit */ + udelay(1); + mask=mask<<1; + } + return b; +} + +static void +read_ser_drv(unsigned char addr, unsigned char *buf, int count) +{ + int i; +#ifdef RTC_DEBUG + char *foo = buf; +#endif + + DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr); + + addr|=1; /* READ */ + N_RESET; + udelay(4); + write_byte(addr); + rtc_go_input(DATA); /* Put gpp pin into input mode */ + udelay(1); + for(i=0;i9) { + printf("ds1302: Year was corrupted, fixing\n"); + bbclk.year10=100; /* 2000 - why not? ;) */ + bbclk.year=0; + mod=1; + } + + /* Write out the changes if needed */ + if (mod) { + /* enable write protect */ + bbclk.WP = 1; + write_ser_drv(0xbe,(unsigned char *)&bbclk,8); + } else { + /* Else just turn write protect on */ + b = 0x80; + write_ser_drv(0x8e,&b,1); + } + DPRINTF("init done\n"); + + ds1302_initted=1; +} + +void +rtc_reset(void) +{ + if(!ds1302_initted) rtc_init(); + /* TODO */ +} + +void +rtc_get(struct rtc_time *tmp) +{ + struct ds1302_st bbclk; + + if(!ds1302_initted) rtc_init(); + + read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); // read burst + + if (bbclk.CH) { + printf("ds1302: rtc_get: Clock was halted, clock probably + corrupt\n"); + } + + tmp->tm_sec=10*bbclk.sec10+bbclk.sec; + tmp->tm_min=10*bbclk.min10+bbclk.min; + tmp->tm_hour=10*bbclk.hr10+bbclk.hr; + tmp->tm_wday=bbclk.day; + tmp->tm_mday=10*bbclk.date10+bbclk.date; + tmp->tm_mon=10*bbclk.month10+bbclk.month; + tmp->tm_year=10*bbclk.year10+bbclk.year + 1900; + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +} + +void +rtc_set(struct rtc_time *tmp) +{ + struct ds1302_st bbclk; + unsigned char b=0; + + if(!ds1302_initted) rtc_init(); + + DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + memset(&bbclk,0,sizeof(bbclk)); + bbclk.CH=0; /* dont halt */ + bbclk.WP=1; /* write protect when we're done */ + + bbclk.sec10=tmp->tm_sec/10; + bbclk.sec=tmp->tm_sec%10; + + bbclk.min10=tmp->tm_min/10; + bbclk.min=tmp->tm_min%10; + + bbclk.hr10=tmp->tm_hour/10; + bbclk.hr=tmp->tm_hour%10; + + bbclk.day=tmp->tm_wday; + + bbclk.date10=tmp->tm_mday/10; + bbclk.date=tmp->tm_mday%10; + + bbclk.month10=tmp->tm_mon/10; + bbclk.month=tmp->tm_mon%10; + + tmp->tm_year -= 1900; + bbclk.year10=tmp->tm_year/10; + bbclk.year=tmp->tm_year%10; + + write_ser_drv(0x8e,&b,1); // disable write protect + write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); // write burst +} + +#endif diff --git a/tools/Makefile b/tools/Makefile index 17d43b5..6331f08 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -23,8 +23,7 @@ BINS = img2srec mkimage envcrc gen_eth_addr bmp_logo -AOBJS = environment.o -COBJS = img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o +OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o LOGO_H = $(TOPDIR)/include/bmp_logo.h @@ -168,8 +167,8 @@ $(LOGO_H): bmp_logo $(LOGO_BMP) ######################################################################### -.depend: Makefile $(COBJS:.o=.c) - $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) $(COBJS:.o=.c) > $@ +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) $(OBJS:.o=.c) > $@ sinclude .depend diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile index 33e4097..1b66390 100644 --- a/tools/gdb/Makefile +++ b/tools/gdb/Makefile @@ -23,7 +23,12 @@ include $(TOPDIR)/config.mk -BINS = gdbsend gdbcont astest +BINS = gdbsend gdbcont + +ifneq ($(HOSTOS),HP-UX) +BINS+= astest +endif + OBJS = gdbsend.o gdbcont.o astest.o error.o remote.o serial.o