From: wdenk Date: Fri, 8 Mar 2002 00:00:48 +0000 (+0000) Subject: * Add support for TQM8xxL modules at 66 MHz clock (CPU/bus 1:1) X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=8f477b51119fdec45cd28753f924deb4ba779544;p=users%2Frw%2Fppcboot.git * Add support for TQM8xxL modules at 66 MHz clock (CPU/bus 1:1) * Patch by Alexandre Guillaume, 04 Mar 2002: Add suport for ST M29F040B flash chip on PCIPPC-2/6 boards. --- diff --git a/CHANGELOG b/CHANGELOG index 8ffa0a1..59e1b18 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,17 @@ Modifications for 1.1.5: ====================================================================== +* Add support for TQM8xxL modules at 66 MHz clock (CPU/bus 1:1) + +* Patch by Alexandre Guillaume, 04 Mar 2002: + Add suport for ST M29F040B flash chip on PCIPPC-2/6 boards. + +* Fix debug output (bdinfo was printed after "fixing" the clock + frequencies), so the debug output was wrong. + +* Added some comments about coding standards and submitting patches + to README file + * Patch by Kári Davíðsson, 2 Mar 2002: - add network configuration for FLAGADM board - fix UPM tables for FLAGADM board diff --git a/Makefile b/Makefile index 1c10329..fbac400 100644 --- a/Makefile +++ b/Makefile @@ -399,25 +399,32 @@ SXNI855T_config: unconfig echo "#include " >config.h # Play some tricks for configuration selection -# All boards can come with 80MHz clock, +# All boards can come with 50 MHz (default), 66MHz or 80MHz clock, # but only 855 and 860 boards may come with FEC # and 823 boards may have LCD support -xtract = $(subst _L2,,$(subst _80MHz,,$(subst _266MHz,,$(subst _LCD,,$(subst _FEC,,$(subst _config,,$1)))))) +xtract = $(subst _L2,,$(subst _66MHz,,$(subst _80MHz,,$(subst _266MHz,,$(subst _LCD,,$(subst _FEC,,$(subst _config,,$1))))))) FPS850L_config \ TQM823L_config \ +TQM823L_66MHz_config \ TQM823L_80MHz_config \ TQM823L_LCD_config \ +TQM823L_LCD_66MHz_config \ TQM823L_LCD_80MHz_config \ TQM850L_config \ +TQM850L_66MHz_config \ TQM850L_80MHz_config \ TQM855L_config \ +TQM855L_66MHz_config \ TQM855L_80MHz_config \ TQM855L_FEC_config \ +TQM855L_FEC_66MHz_config \ TQM855L_FEC_80MHz_config \ TQM860L_config \ +TQM860L_66MHz_config \ TQM860L_80MHz_config \ TQM860L_FEC_config \ +TQM860L_FEC_66MHz_config \ TQM860L_FEC_80MHz_config: unconfig @echo "Configuring for $(call xtract,$@) Board..." ; \ cd ./include ; \ @@ -429,6 +436,10 @@ TQM860L_FEC_80MHz_config: unconfig { echo "#define CONFIG_FEC_ENET" >>include/config.h ; \ echo "... with FEC support" ; \ } + @[ -z "$(findstring _66MHz,$@)" ] || \ + { echo "#define CONFIG_66MHz" >>include/config.h ; \ + echo "... with 66MHz system clock" ; \ + } @[ -z "$(findstring _80MHz,$@)" ] || \ { echo "#define CONFIG_80MHz" >>include/config.h ; \ echo "... with 80MHz system clock" ; \ diff --git a/README b/README index 81ad216..314451a 100644 --- a/README +++ b/README @@ -426,7 +426,7 @@ The following options need to be configured: what you (and your PPCBoot users) are doing. Data cache cannot be enabled on systems like the 8xx or 8260 (where accesses to the IMMR region must be - uncached), and it cannot be enabled on all other + uncached), and it cannot be disabled on all other systems where we (mis-) use the data cache to hold an initial stack and some data. @@ -1872,3 +1872,72 @@ Only after this relocation you have a "normal" C environment; until that you are restricted in several ways, mostly because you are running from ROM, and because the code will have to be relocated to a new address in RAM. + + +Coding Standards: +----------------- + +All contributions to PPCBoot should conform to the Linux kernel +coding style; see the file "Documentation/CodingStyle" in your Linux +kernel source directory. + +Please note that PPCBoot is implemented in C (and to some small parts +in Assembler); no C++ is used, so please do not use C++ style +comments (//) in your code. + +Submissions which do not conform to the standards may be returned +with a request to reformat the changes. + + +Submitting Patches: +------------------- + +Since the number of patches for PPCBoot is growing, we need to +establish some rules. Submissions which do not conform to these rules +may be rejected, even when they contain important and valuable stuff. + + +When you send a patch, please include the following information with +it: + +* For bug fixes: a description of the bug and how your patch fixes + this bug. Please try to include a way of demonstrating that the + patch actually fixes something. + +* For new features: a description of the feature and your + implementation. + +* A CHANGELOG entry as plaintext (separate from the patch) + +* For major contributions, your entry to the CREDITS file + +* When you add support for a new board, don't forget to add this + board to the MAKEALL script, too. + +* If your patch adds new configuration options, don't forget to + document these in the README file. + +* The patch itself. If you are accessing the CVS repository use "cvs + update; cvs diff -puRN"; else, use "diff -purN OLD NEW". If your + version of diff does not support these options, then get the latest + version of GNU diff. + + We accept patches as plain text, MIME attachments or as uuencoded + gzipped text. + +Notes: + +* Before sending the patch, run the MAKEALL script on your patched + source tree and make sure that no errors or warnings are reported + for any of the boards. + +* Keep your modifications to the necessary minimum: A patch + containing several unrelated changes or arbitrary reformats will be + returned with a request to re-formatting / split it. + +* If you modify existing code, make sure that your new code does not + add to the memory footprint of the code ;-) Small is beautiful! + When adding new features, these should compile conditionally only + (using #ifdef), and the resulting code with the new feature + disabled must not need more memory than the old code without your + modification. diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c index 7125e1f..bb4afed 100644 --- a/board/pcippc2/flash.c +++ b/board/pcippc2/flash.c @@ -119,6 +119,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info) info->flash_id = FLASH_MAN_FUJ; break; + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; @@ -212,6 +216,14 @@ static ulong flash_get_size (ulong addr, flash_info_t *info) info->sector_count = 64; info->size = 0x01000000; break; /* => 16Mb */ + + case STM_ID_F040B: + DEBUGF("M29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + default: info->flash_id = FLASH_UNKNOWN; flash_reset (addr); @@ -281,8 +293,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) return 1; } - if (info->flash_id == FLASH_UNKNOWN || - info->flash_id > FLASH_AMD_COMP) { + if (info->flash_id == FLASH_UNKNOWN) { printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); return 1; @@ -511,6 +522,7 @@ void flash_print_info (flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_STM: printf ("SGS THOMSON "); break; default: printf ("Unknown Vendor "); break; } diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index c8bdc8b..dc92e35 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -47,7 +47,11 @@ void pcippc2_wdt_init (void); */ int checkboard (void) { - printf ("PCIPPC-2\n"); +#ifdef CONFIG_PCIPPC2 + printf ("Gespac PCIPPC-2\n"); +#else + printf ("Gespac PCIPPC-6\n"); +#endif return 1; } diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index 58cafa8..a86cdd5 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index ee84e92..925e05b 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -318,6 +318,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, bd_t *bd, int flag, #ifdef DEBUG printf ("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); + + do_bdinfo (NULL, kbd, 0, 0, NULL); #endif *kbd = *bd; @@ -498,8 +500,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, bd_t *bd, int flag, } #ifdef DEBUG - do_bdinfo (NULL, kbd, 0, 0, NULL); - printf ("## Transferring control to Linux (at address %08lx) ...\n", (ulong)kernel); #endif diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 6619650..2eac2f0 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -245,7 +245,7 @@ _back: .globl _end_of_vectors _end_of_vectors: - . = 0x3000 + . = 0x2000 boot_cold: boot_warm: @@ -804,7 +804,7 @@ trap_init: /* enable execptions from RAM vectors */ mfmsr r7 - li r8,MSR_IP + li r8,MSR_IP andc r7,r7,r8 mtmsr r7 diff --git a/include/config_TQM823L.h b/include/config_TQM823L.h index c0e979d..2bb06e8 100644 --- a/include/config_TQM823L.h +++ b/include/config_TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000, 2001 + * (C) Copyright 2000, 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -317,9 +317,22 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) +/* + * FLASH timing: + */ +#if defined(CONFIG_80MHz) +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#elif defined(CONFIG_66MHz) +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#else /* 50 MHz */ +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -356,12 +369,46 @@ /* * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 */ +#if defined(CONFIG_80MHz) +#define CFG_MAMR_PTA 156 +#elif defined(CONFIG_66MHz) +#define CFG_MAMR_PTA 129 +#else /* 50 MHz */ +#define CFG_MAMR_PTA 98 +#endif /*CONFIG_??MHz */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ diff --git a/include/config_TQM850L.h b/include/config_TQM850L.h index de315ec..6d5d42e 100644 --- a/include/config_TQM850L.h +++ b/include/config_TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -310,9 +310,22 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) +/* + * FLASH timing: + */ +#if defined(CONFIG_80MHz) +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#elif defined(CONFIG_66MHz) +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#else /* 50 MHz */ +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -349,12 +362,46 @@ /* * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 */ +#if defined(CONFIG_80MHz) +#define CFG_MAMR_PTA 156 +#elif defined(CONFIG_66MHz) +#define CFG_MAMR_PTA 129 +#else /* 50 MHz */ +#define CFG_MAMR_PTA 98 +#endif /*CONFIG_??MHz */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ diff --git a/include/config_TQM855L.h b/include/config_TQM855L.h index 06661b3..419b554 100644 --- a/include/config_TQM855L.h +++ b/include/config_TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -310,9 +310,22 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) +/* + * FLASH timing: + */ +#if defined(CONFIG_80MHz) +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#elif defined(CONFIG_66MHz) +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#else /* 50 MHz */ +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -349,12 +362,46 @@ /* * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 */ +#if defined(CONFIG_80MHz) +#define CFG_MAMR_PTA 156 +#elif defined(CONFIG_66MHz) +#define CFG_MAMR_PTA 129 +#else /* 50 MHz */ +#define CFG_MAMR_PTA 98 +#endif /*CONFIG_??MHz */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ diff --git a/include/config_TQM860L.h b/include/config_TQM860L.h index 12c4c70..4397e84 100644 --- a/include/config_TQM860L.h +++ b/include/config_TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -318,9 +318,22 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) +/* + * FLASH timing: + */ +#if defined(CONFIG_80MHz) +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#elif defined(CONFIG_66MHz) +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +#else /* 50 MHz */ +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -357,12 +370,46 @@ /* * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 */ +#if defined(CONFIG_80MHz) +#define CFG_MAMR_PTA 156 +#elif defined(CONFIG_66MHz) +#define CFG_MAMR_PTA 129 +#else /* 50 MHz */ +#define CFG_MAMR_PTA 98 +#endif /*CONFIG_??MHz */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ diff --git a/include/flash.h b/include/flash.h index 153dd81..b44043c 100644 --- a/include/flash.h +++ b/include/flash.h @@ -148,6 +148,9 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */ #define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */ +#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */ + /* 8 64K x 8 uniform sectors */ + #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ @@ -193,6 +196,7 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B * Bright Micro BM29F040 * Fujitsu MBM29F040A + * SGS Thomson M29F040B * 8 64K x 8 uniform sectors */ #define FLASH_AM400T 0x0002 /* AMD AM29LV400 */