From: Raju Rangoju Date: Wed, 25 Sep 2024 13:36:40 +0000 (+0530) Subject: spi: spi_amd: Updates to set tx/rx count functions X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=8cd9141ad4e053d361c854cc24a18a9ca050e0a1;p=users%2Fjedix%2Flinux-maple.git spi: spi_amd: Updates to set tx/rx count functions AMD SPI TX and RX counter registers are 1-byte length registers. The existing value will be overwritten during register write, so masking is not required. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 1d1a18ee0bb5..7841f3292a62 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -180,12 +180,12 @@ static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count) { - amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); + amd_spi_writereg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count); } static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) { - amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); + amd_spi_writereg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count); } static int amd_spi_busy_wait(struct amd_spi *amd_spi)