From: Rajmohan Mani Date: Wed, 18 Nov 2015 08:48:20 +0000 (+0200) Subject: xhci: Workaround to get Intel xHCI reset working more reliably X-Git-Tag: v4.1.12-92~189^2 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=898611cf6c8089b7839d2b126200f2041b53b9e9;p=users%2Fjedix%2Flinux-maple.git xhci: Workaround to get Intel xHCI reset working more reliably Orabug: 22805913 Existing Intel xHCI controllers require a delay of 1 mS, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 5000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang. Signed-off-by: Rajmohan Mani Tested-by: Joe Lawrence Cc: stable Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman (cherry picked from commit a5964396190d0c40dd549c23848c282fffa5d1f2) Signed-off-by: Dan Duval --- diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index c502c2277aebf..87f274462da64 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -174,6 +174,16 @@ int xhci_reset(struct xhci_hcd *xhci) command |= CMD_RESET; writel(command, &xhci->op_regs->command); + /* Existing Intel xHCI controllers require a delay of 1 mS, + * after setting the CMD_RESET bit, and before accessing any + * HC registers. This allows the HC to complete the + * reset operation and be ready for HC register access. + * Without this delay, the subsequent HC register access, + * may result in a system hang very rarely. + */ + if (xhci->quirks & XHCI_INTEL_HOST) + udelay(1000); + ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, 10 * 1000 * 1000); if (ret)