From: Ingo Molnar Date: Tue, 16 Sep 2025 06:24:22 +0000 (+0200) Subject: Merge branch 'x86/urgent' into x86/apic, to resolve conflict X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=85df1cd15ff5d775e88e23b9fc2a9f429fa5b504;p=users%2Fhch%2Fmisc.git Merge branch 'x86/urgent' into x86/apic, to resolve conflict Conflicts: arch/x86/include/asm/sev.h Signed-off-by: Ingo Molnar --- 85df1cd15ff5d775e88e23b9fc2a9f429fa5b504 diff --cc arch/x86/include/asm/sev.h index d7be1ff3f7e0,465b19fd1a2d..44dae7472246 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@@ -567,19 -560,26 +567,37 @@@ enum es_result sev_es_ghcb_hv_call(stru u64 exit_code, u64 exit_info_1, u64 exit_info_2); +bool sev_es_negotiate_protocol(void); +bool sev_es_check_cpu_features(void); + +extern u16 ghcb_version; extern struct ghcb *boot_ghcb; +extern bool sev_snp_needs_sfw; + +struct psc_desc { + enum psc_op op; + struct svsm_ca *ca; + u64 caa_pa; +}; + static inline void sev_evict_cache(void *va, int npages) + { + volatile u8 val __always_unused; + u8 *bytes = va; + int page_idx; + + /* + * For SEV guests, a read from the first/last cache-lines of a 4K page + * using the guest key is sufficient to cause a flush of all cache-lines + * associated with that 4K page without incurring all the overhead of a + * full CLFLUSH sequence. + */ + for (page_idx = 0; page_idx < npages; page_idx++) { + val = bytes[page_idx * PAGE_SIZE]; + val = bytes[page_idx * PAGE_SIZE + PAGE_SIZE - 1]; + } + } + #else /* !CONFIG_AMD_MEM_ENCRYPT */ #define snp_vmpl 0 @@@ -621,10 -623,7 +639,11 @@@ static inline int snp_send_guest_reques static inline int snp_svsm_vtpm_send_command(u8 *buffer) { return -ENODEV; } static inline void __init snp_secure_tsc_prepare(void) { } static inline void __init snp_secure_tsc_init(void) { } + static inline void sev_evict_cache(void *va, int npages) {} +static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED; } +static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; } +static inline void savic_ghcb_msr_write(u32 reg, u64 value) { } +static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; } #endif /* CONFIG_AMD_MEM_ENCRYPT */