From: Ville Syrjälä Date: Tue, 2 Sep 2025 13:31:10 +0000 (+0300) Subject: drm/i915/dram: Move 16Gb DIMM detection fully to the skl/icl codepaths X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=84b72b545c0fe1fc3ecbe80a499f27da1de9a9e5;p=users%2Fhch%2Fmisc.git drm/i915/dram: Move 16Gb DIMM detection fully to the skl/icl codepaths We are incorrectly applying the 16Gb DIMM w/a (adding 1 extra usec to WM0 latency) on MTL+ even though the w/a is only needed for SKL/ICL. The current way of setting this is up is a bit of a disaster: 1. always set has_16gb_dimms=true for all platforms except BXT/GLK 2. has_16gb_dimms potentially gets overwritten with something else * BXT/GLK don't do anything since we never set has_16gb_dimms to begin with * skl_get_dram_info() overwrites has_16gb_dimms with the actual detection results for SKL/ICL/derivatives * gen12_get_dram_info() (correctly) resets has_16gb_dimms for TGL/ADL/derivatives * xelpdp_get_dram_info() doesn't do anything, leaving has_16gb_dimms incorrectly set for MTL+ Clean up the whole mess by only setting has_16gb_dimms in the SKL/ICL codepaths where we have the actual detection code for it. This avois applying the w/a incorrectly on MTL+. v2: Rewrite commit msg (Jani) Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250902133113.18778-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index efb72e137748..bf3ba874f8c5 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -406,6 +406,9 @@ skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram u32 val; int ret; + /* Assume 16Gb DIMMs are present until proven otherwise */ + dram_info->has_16gb_dimms = true; + val = intel_uncore_read(&i915->uncore, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); ret = skl_dram_get_channel_info(i915, &ch0, 0, val); @@ -435,6 +438,9 @@ skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n", str_yes_no(dram_info->symmetric_memory)); + drm_dbg_kms(&i915->drm, "16Gb DIMMs: %s\n", + str_yes_no(dram_info->has_16gb_dimms)); + return 0; } @@ -673,8 +679,6 @@ static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info * static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) { - dram_info->has_16gb_dimms = false; - return icl_pcode_read_mem_global_info(i915, dram_info); } @@ -736,12 +740,6 @@ int intel_dram_detect(struct drm_i915_private *i915) i915->dram_info = dram_info; - /* - * Assume 16Gb DIMMs are present until proven - * otherwise, this w/a is not needed by bxt/glk. - */ - dram_info->has_16gb_dimms = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915); - if (DISPLAY_VER(display) >= 14) ret = xelpdp_get_dram_info(i915, dram_info); else if (GRAPHICS_VER(i915) >= 12) @@ -766,9 +764,6 @@ int intel_dram_detect(struct drm_i915_private *i915) drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels); - drm_dbg_kms(&i915->drm, "16Gb DIMMs: %s\n", - str_yes_no(dram_info->has_16gb_dimms)); - return 0; }