From: Lucas De Marchi Date: Mon, 6 Mar 2023 16:57:57 +0000 (-0800) Subject: drm/xe: Fix ROW_CHICKEN2 define X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=7dae750dde42459483054384a5d234b54e643cdd;p=linux.git drm/xe: Fix ROW_CHICKEN2 define When this register was added in xe for some workarounds, it was copied from i915 before the registers got changed to add the MCR annotation. The register 0xe4f4 is MCR since gen8, long before any GPU supported by the xe driver. Replace all occurrences with the right register. Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20230306165757.633796-1-lucas.demarchi@intel.com Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 6a728d2809c5..d3b862e4cd0d 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -230,7 +230,7 @@ #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) -#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) +#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4) #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15) #define GEN12_DISABLE_EARLY_READ REG_BIT(14) #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 71e9e1a111f8..03c5b01a14e4 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -191,7 +191,7 @@ static const struct xe_rtp_entry engine_was[] = { }, { XE_RTP_NAME("1606931601"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ, + XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), @@ -213,7 +213,7 @@ static const struct xe_rtp_entry engine_was[] = { XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER), IS_INTEGRATED), - XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS, + XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14010229206, 1409085225"),