From: hydra <hydra>
Date: Thu, 14 Sep 2000 11:13:50 +0000 (+0000)
Subject: Preliminary FADS support.
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=7d9ba9962aa9d397de85af93f939920eea97a17e;p=users%2Frw%2Fppcboot.git

Preliminary FADS support.
Tested:  FADS850SAR
Working:  serial, flash
Not working:  net
Questionable:  clock configuration - ppcboot reports it is running
at 20Mhz while it should be 50Mhz.
---

diff --git a/Makefile b/Makefile
index b410cfd..48f85da 100644
--- a/Makefile
+++ b/Makefile
@@ -75,10 +75,10 @@ install:	all
 	cp ppcboot.srec /net/gatekeeper/tftpboot/moni.srec
 
 ppcboot.srec:	ppcboot
-	$(OBJCOPY) -O srec $< $@
+	$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
 
 ppcboot.bin:	ppcboot
-	$(OBJCOPY) -O binary $< $@
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 
 ppcboot:	depend $(SUBDIRS) $(OBJS) $(LDSCRIPT)
 	$(LD) $(LDFLAGS) $(OBJS) -Map ppcboot.map -o ppcboot
@@ -121,11 +121,12 @@ ETX094_config	:	unconfig
 	echo "CPU   = mpc8xx"	>>config.mk ;	\
 	echo "#include <config_$(@:_config=).h>" >config.h
 
-FADS_config:	unconfig
+FADS850SAR_config \
+FADS860T_config:	unconfig
 	@echo "Configuring for $(@:_config=) Board..." ; \
 	cd include ;				\
 	echo "ARCH  = ppc"	> config.mk ;	\
-	echo "BOARD = FADS"	>>config.mk ;	\
+	echo "BOARD = fads"	>>config.mk ;	\
 	echo "CPU   = mpc8xx"	>>config.mk ;	\
 	echo "#include <config_$(@:_config=).h>" >config.h
 
diff --git a/common/board.c b/common/board.c
index ddb4909..28e904c 100644
--- a/common/board.c
+++ b/common/board.c
@@ -83,7 +83,7 @@ board_init_f (ulong bootflag)
     cpu_speed = get_gclk_freq () / 1000 / 1000;		/* in MHz */
 
     s = getenv ("baudrate");
-    baudrate = s ? (int)simple_strtoul(s, NULL, 10) : 9600;
+    baudrate = s ? (int)simple_strtoul(s, NULL, 10) : CONFIG_BAUDRATE;
 
     /* set up serial port */
     serial_init (cpu_speed, baudrate);
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 4ad89b4..013c117 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -53,7 +53,9 @@ static uchar default_environment[] = {
 #if (CONFIG_BOOTDELAY >= 0)
 	"bootdelay="	MK_STR(CONFIG_BOOTDELAY)	"\0"
 #endif
+#if (CONFIG_BAUDRATE >= 0)
 	"baudrate="	MK_STR(CONFIG_BAUDRATE)		"\0"
+#endif
 	"\0"
 };
 
diff --git a/common/environment.S b/common/environment.S
index eb077ac..72829de 100644
--- a/common/environment.S
+++ b/common/environment.S
@@ -3,7 +3,11 @@
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 
+#if defined(CONFIG_FADS)
+	.section	".ppcenv"
+#else
 	.text
+#endif
 	.globl	environment
 environment:
 	.ascii	"bootargs="
@@ -26,6 +30,9 @@ environment:
 	.ascii		"\0"
 	. = environment + CFG_FLASH_ENV_SIZE
 .L_end:
+#if defined(CONFIG_FADS)
+	.text
+#endif
 	.globl  env_size
 env_size:
 	.long	.L_end - environment
diff --git a/config.mk b/config.mk
index 3728297..3f25d9e 100644
--- a/config.mk
+++ b/config.mk
@@ -83,13 +83,13 @@ AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS)
 
 LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
 
-OBJCFLAGS = --remove-section=.stab			\
-	--remove-section=.comment			\
-	--remove-section=.stabstr			\
-	--change-section-lma=.data+$(TEXT_BASE)		\
-	--change-section-lma=__ex_table+$(TEXT_BASE)	\
-	--change-section-lma=.bss+$(TEXT_BASE)		\
-	--set-section-flags=.bss=contents,alloc,load,data
+#OBJCFLAGS = --remove-section=.stab			\
+#	--remove-section=.comment			\
+#	--remove-section=.stabstr			\
+#	--change-section-lma=.data+$(TEXT_BASE)		\
+#	--change-section-lma=__ex_table+$(TEXT_BASE)	\
+#	--change-section-lma=.bss+$(TEXT_BASE)		\
+#	--set-section-flags=.bss=contents,alloc,load,data
 
 #########################################################################
 
diff --git a/fads/Makefile b/fads/Makefile
new file mode 100644
index 0000000..e842c11
--- /dev/null
+++ b/fads/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o lamp.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+	
+sinclude .depend
+
+#########################################################################
diff --git a/fads/config.mk b/fads/config.mk
new file mode 100644
index 0000000..a9dbb8e
--- /dev/null
+++ b/fads/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# FADS boards
+#
+
+#TEXT_BASE = 0xFE000000
+TEXT_BASE = 0x02800000
+OBJCFLAGS =	--set-section-flags=.ppcenv=contents,alloc,load,data
diff --git a/fads/fads.c b/fads/fads.c
new file mode 100644
index 0000000..d20e910
--- /dev/null
+++ b/fads/fads.c
@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <config.h>
+#include "mpc8xx.h"
+#include "fads.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+#define PCMCIA_MAP 0xf0130000
+volatile unsigned char *pcmcia_mem = (unsigned char*)PCMCIA_MAP;
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+#if defined(CONFIG_DRAM_50MHZ)
+/* 50MHz tables */
+const uint dram_60ns[] =
+{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
+  0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff,
+  0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
+  0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
+  0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
+  0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff, 
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint dram_70ns[] =
+{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+  0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff,
+  0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+  0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
+  0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
+  0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+  0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_60ns[] =
+{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
+  0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff,
+  0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
+  0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
+  0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_70ns[] =
+{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
+  0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff,
+  0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
+  0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
+  0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
+  0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+  0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+#elif defined(CONFIG_DRAM_25MHZ)
+
+/* 25MHz tables */
+
+const uint dram_60ns[] =
+{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint dram_70ns[] =
+{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_60ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
+  0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
+  0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_70ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
+  0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
+  0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+  0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+  0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+
+#else
+#error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ * 
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	uint k;
+
+	k = (*((uint *)BCSR3) >> 24) & 0x3f;
+
+	switch(k)
+	{
+		case 0x03 :
+		case 0x20 :
+		case 0x21 :
+		case 0x22 :
+		case 0x23 :
+		case 0x24 : 
+		case 0x3f :
+			printf("FADS"); 
+			break;
+
+		default :  
+			printf("unknown board (0x%02x)\n", k); 
+			return -1;
+	}
+
+	printf(" with db ");
+
+	switch(k)
+	{
+		case 0x03 : 
+			printf("MPC823"); 
+			break;
+		case 0x20 : 
+			printf("MPC801"); 
+			break;
+		case 0x21 : 
+			printf("MPC850");
+			break;
+		case 0x22 : 
+			printf("MPC821, MPC860 / MPC860SAR / MPC860T");
+			break;
+		case 0x23 : 
+			printf("MPC860SAR"); 
+			break;
+		case 0x24 : 
+			printf("MPC860T");
+			break;
+		case 0x3f : 
+			printf("MPC850SAR"); 
+			break;
+	}
+
+	printf(" rev ");
+
+	k = (((*((uint *)BCSR3) >> 23) & 1) << 3) 
+	| (((*((uint *)BCSR3) >> 19) & 1) << 2)
+	| (((*((uint *)BCSR3) >> 16) & 3));
+
+	switch(k)
+	{
+		case 0x01 : 
+			printf("ENG or PILOT\n"); 
+			break;
+	
+		default:
+			printf("unknown (0x%x)\n", k); 
+			return -1;
+	}
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Size of FLASH memory
+ */
+int checkflash (void)
+{
+    /* TODO: XXX XXX XXX */
+    printf ("8 MB ## Test not implemented yet ##\n");
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+int _draminit(uint base, uint noMbytes, uint edo, uint delay)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;	 
+ 
+	/* init upm */
+
+	switch(delay)
+	{
+		case 70: 
+		{
+			if(edo)
+			{
+				upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint));
+			}
+			else
+			{
+				upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint));
+			}
+
+			break;
+		}
+
+		case 60: 
+		{
+			if(edo)
+			{
+				upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
+			}
+			else
+			{
+				upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint));
+			}
+
+			break;
+		}
+
+		default : 
+			return -1;
+	}
+	
+	memctl->memc_mptpr = 0x0400; /* divide by 16 */
+
+	switch(noMbytes)
+	{
+
+		case 8:  /* 8 Mbyte uses both CS3 and CS2 */
+		{
+			memctl->memc_mamr = 0x13a01114;
+			memctl->memc_or3 = 0xffc00800;
+			memctl->memc_br3 = 0x00400081 + base;        
+			memctl->memc_or2 = 0xffc00800;
+			break;
+		}
+    
+		case 4: /* 4 Mbyte uses only CS2 */
+		{
+			memctl->memc_mamr = 0x13a01114;
+			memctl->memc_or2 = 0xffc00800;
+			break;
+		}
+
+		case 32: /* 32 Mbyte uses both CS3 and CS2 */
+		{
+			memctl->memc_mamr = 0x13b01114;
+			memctl->memc_or3 = 0xff000800;
+			memctl->memc_br3 = 0x01000081 + base;        
+			memctl->memc_or2 = 0xff000800;
+			break;
+		}
+ 
+		case 16: /* 16 Mbyte uses only CS2 */
+		{
+			memctl->memc_mamr = 0x13b01114;
+			memctl->memc_or2 = 0xff000800;
+			break;
+		}
+	
+		default:
+		    return -1;
+	}
+
+	memctl->memc_br2 = 0x81 + base;     /* use upma */
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void _dramdisable(void)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;	 
+
+	memctl->memc_br2 = 0x00000000;
+	memctl->memc_br3 = 0x00000000;
+
+	/* maybe we should turn off upma here or something */
+}
+
+#if defined(CONFIG_SDRAM_100MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table by Dan Malek                                                  */
+
+/* This has the stretched early timing so the 50 MHz
+ * processor can make the 100 MHz timing.  This will
+ * work at all processor speeds.
+ */
+
+#define SDRAM_MPTPRVALUE 0x0400
+
+#define SDRAM_MBMRVALUE0 0xc3802114  /* (16-14) 50 MHz */
+#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
+
+#define SDRAM_OR4VALUE   0xffc00a00
+#define SDRAM_BR4VALUE   0x000000c1   /* base address will be or:ed on */
+
+#define SDRAM_MARVALUE   0x88
+
+#define SDRAM_MCRVALUE0  0x80808111   /* run pattern 0x11 */
+#define SDRAM_MCRVALUE1  SDRAM_MCRVALUE0 
+
+
+const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
+	0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
+	0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
+	0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
+	0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
+
+	/* single write. (offset 18 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
+	0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
+	0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff };
+
+#elif defined(CONFIG_SDRAM_50MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table stolen from the fads manual                                   */
+/* for chip MB811171622A-100                                                 */
+
+/* this table is for 32-50MHz operation */
+
+#define _not_used_ 0xffffffff
+
+#define SDRAM_MPTPRVALUE 0x0400
+
+#define SDRAM_MBMRVALUE0 0x80802114   /* refresh at 32MHz */
+#define SDRAM_MBMRVALUE1 0x80802118
+
+#define SDRAM_OR4VALUE   0xffc00a00
+#define SDRAM_BR4VALUE   0x000000c1   /* base address will be or:ed on */
+
+#define SDRAM_MARVALUE   0x88
+
+#define SDRAM_MCRVALUE0  0x80808105
+#define SDRAM_MCRVALUE1  0x80808130
+
+const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47, 
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_, 
+	_not_used_, _not_used_, _not_used_, _not_used_, 
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_, 
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, 
+	_not_used_, _not_used_, _not_used_, _not_used_, 
+	_not_used_, _not_used_, _not_used_, _not_used_, 
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_, 
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+#else
+#error SDRAM not correctly configured
+#endif
+
+int _initsdram(uint base, uint noMbytes)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;	 
+
+	if(noMbytes != 4)
+	{
+		return -1;
+	}
+
+	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
+
+	/* Configure the refresh (mostly).  This needs to be
+	* based upon processor clock speed and optimized to provide
+	* the highest level of performance.  For multiple banks,
+	* this time has to be divided by the number of banks.
+	* Although it is not clear anywhere, it appears the
+	* refresh steps through the chip selects for this UPM
+	* on each refresh cycle.
+	* We have to be careful changing
+	* UPM registers after we ask it to run these commands.
+	*/
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE0;
+	memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */
+
+	udelay(200);
+
+	/* Now run the precharge/nop/mrs commands.
+	*/
+
+	memctl->memc_mcr = 0x80808111;   /* run pattern 0x11 */
+
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+
+	memctl->memc_mcr = SDRAM_MCRVALUE0;
+
+	udelay(200);
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE1;
+	memctl->memc_mcr = SDRAM_MCRVALUE1;
+
+	udelay(200);
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE0;
+
+	memctl->memc_or4 = SDRAM_OR4VALUE;
+	memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void _sdramdisable(void)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;	 
+
+	memctl->memc_br4 = 0x00000000;
+
+	/* maybe we should turn off upmb here or something */
+}
+
+/* ------------------------------------------------------------------------- */
+
+int initsdram(uint base, uint *noMbytes)
+{
+	uint m = 4;
+
+	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
+								  /* _fads_sdraminit needs access to sdram */
+	*noMbytes = m;
+
+	if(!_initsdram(base, m))
+	{
+
+		return 0;
+	}
+	else
+	{
+		*((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
+
+		_sdramdisable();
+
+		return -1;
+	}
+}
+
+void initflash(uint *noMbytes, uint *delay)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;	
+ 
+	uint k, m;
+
+	k = *((uint *)BCSR2) >> 28;
+
+	switch(k)
+	{
+#ifdef CONFIG_FADS
+		/* "SM732A2000 / SM73228" */
+		case 0x04 : 
+			m = 8; 
+			break; 
+		/* "SM732A1000A / SM73218" */
+		case 0x05 : 
+			m = 4; 
+			break; 
+#endif
+		/* "MCM29080" */
+		case 0x06 : 
+			m = 8; 
+			break; 
+		/* "MCM29040" */
+		case 0x07 : 
+			m = 4; 
+			break; 
+		/* "MCM29020" */
+		case 0x08 : 
+			m = 2; 
+			break; 
+#ifdef CONFIG_ADS
+		/* "SM732A1000A" */
+		case 0x0a :
+			m = 4; 
+			break; 
+		/* "SM732A2000" */
+		case 0x0b :
+			m = 8; 
+			break; 
+#endif
+		default : 
+			printf("unknown flashsize (0x%x) - defaulting to 2 Mbyte", k); 
+			m = 2;
+			break;
+	}
+
+	k = (*((uint *)BCSR3) >> 20) & 0x07;
+
+	switch(k)
+	{
+		case 0x01 : 
+			k = 150; 
+			break;
+		case 0x02 : 
+			k = 120; 
+			break;
+		case 0x03 : 
+			k = 90; 
+			break;
+		default : 
+			printf("unknown flashdelay(0x%x) - defaulting to 150 ns", k); 
+			k = 150; 
+			break;
+	}
+    
+	/* we're supposed to set the correct number of waitstates
+	* but today we just set it to maximum, no hurry */
+
+	/* set or0 to the correct size */
+
+	memctl->memc_or0 = ~((m << 20) - 1) | 0xdf4;
+
+	*noMbytes = m;
+	*delay = k;
+  
+}
+
+long int initdram (int board_type)
+{
+	uint base = (unsigned long)0x00400000;
+	uint k, m, s;
+
+	k = (*((uint *)BCSR2) >> 23) & 0x0f;
+
+	m = 0;
+
+	switch(k & 0x3)
+	{
+		/* "MCM36100 / MT8D132X" */
+		case 0x00 : 
+			m = 4; 
+			break; 
+		
+		/* "MCM36800 / MT16D832X" */
+		case 0x01 : 
+			m = 32; 
+			break; 
+		/* "MCM36400 / MT8D432X" */
+		case 0x02 : 
+			m = 16; 
+			break; 
+		/* "MCM36200 / MT16D832X ?" */
+		case 0x03 : 
+			m = 8; 
+			break;
+
+	}
+
+	switch(k >> 2)
+	{
+		case 0x02 : 
+			k = 70; 
+			break;
+		
+		case 0x03 : 
+			k = 60; 
+			break;
+	
+		default : 
+			printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k); 
+			k = 70; 
+	}
+
+#ifdef CONFIG_FADS
+	/* the FADS is missing this bit, all rams treated as non-edo */
+	s = 0;  
+#else
+	s = (*((uint *)BCSR2) >> 27) & 0x01;
+#endif
+
+	if(!_draminit(base, m, s, k))
+	{
+		uint	sdramsz;
+
+	    *((uint *)BCSR1) &= ~BCSR1_DRAM_EN;  /* enable dram */
+
+#ifdef CONFIG_FADS
+		if (!initsdram(0x00000000, &sdramsz)) {
+				m += sdramsz;
+				printf("(%u MB SDRAM) ", sdramsz);
+		} else {
+				_dramdisable();
+
+				/********************************
+				*DRAM ERROR, HALT PROCESSOR
+				*********************************/
+				while(1);
+				
+				return -1; 
+		}
+#endif
+
+		return (m << 20);
+	}
+	else
+	{
+		_dramdisable();
+
+		/********************************
+		*DRAM ERROR, HALT PROCESSOR
+		*********************************/
+		while(1);
+		
+		return -1; 
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+    /* TODO: XXX XXX XXX */
+    printf ("test: 16 MB - ok\n");
+
+    return (0);
+}
+
+int pcmciacheck(void)
+{
+	volatile pcmconf8xx_t	*pcmp;
+	uint v;
+
+	/* Enable the PCMCIA for a Flash card.
+	*/
+
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+	pcmp->pcmc_pbr0 = PCMCIA_MAP;
+	pcmp->pcmc_por0 = 0xc00ff05d;
+	/* Set all slots to zero by default. */
+	pcmp->pcmc_pgcra = 0;
+	pcmp->pcmc_pgcrb = 0;
+#ifdef PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0x40;
+#endif
+#ifdef PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0x40;
+#endif
+
+	/* enable PCMCIA buffers */
+	*((uint *)BCSR1) &= ~BCSR1_PCCEN;
+
+	/* Check if any PCMCIA card is luged in. */
+	if (pcmp->pcmc_pipr & 0x18001800)
+	{
+		printf("No card present.\n");
+#ifdef PCMCIA_SLOT_A
+		pcmp->pcmc_pgcra = 0;
+#endif
+#ifdef PCMCIA_SLOT_B
+		pcmp->pcmc_pgcrb = 0;
+#endif
+		return -1;
+	}
+
+	v = 0;
+
+	/* both the ADS and the FADS have a 5V keyed pcmcia connector (?)*/ 
+
+#if defined(CONFIG_MPC860)
+	switch( (pcmp->pcmc_pipr >> 30) & 3 )
+#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
+	switch( (pcmp->pcmc_pipr >> 14) & 3 )
+#endif
+	{
+		case 0x00 : 
+			printf("5V\n"); 
+			v = 5; 
+			break;
+		case 0x01 : 
+			printf("5V and 3V\n"); 
+			v = 5; 
+			break;
+		case 0x03 : 
+			printf("5V, 3V and x.xV\n"); 
+			v = 5; 
+			break;
+	}
+
+	if(v == 5)
+	{
+
+#ifdef CONFIG_ADS  
+		/* Enable 5 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
+#endif
+#ifdef CONFIG_FADS
+	/* Enable 5 volt Vcc.
+	*/
+	*((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
+	*((uint *)BCSR1) |= BCSR1_PCCVCC1;
+#if 0
+	/* Enable PCMCIA drivers and 3.3 voltage.
+	*/
+	*((uint *)BCSR1) |=  0x00400000;
+	*((uint *)BCSR1) &= ~0x00b10000;
+#endif
+#endif
+	}
+	else
+	{
+		*((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */
+
+		printf("unknown voltage\n");
+		return -1;
+	}
+
+	/* disable pcmcia reset after a while */
+
+	udelay(20);
+
+#ifdef MPC860
+	pcmp->pcmc_pgcra = 0;
+#elif MPC823
+	pcmp->pcmc_pgcrb = 0;
+#endif
+
+	/* If you using a real hd you should give a short
+	* spin-up time. */
+#ifdef CONFIG_DISK_SPINUP_TIME
+	udelay(CONFIG_DISK_SPINUP_TIME);
+#endif
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    volatile long int	 *addr;
+    long int		  cnt, val;
+
+    memctl->memc_mamr = mamr_value;
+
+    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	*addr = ~cnt;
+    }
+
+    /* write 0 to base address */
+    addr = base;
+    *addr = 0;
+
+    /* check at base address */
+    if ((val = *addr) != 0) 
+	{
+		return (0);
+    }
+
+    for (cnt = 1; ; cnt <<= 1) 
+	{
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+
+		if (val != (~cnt)) 
+		{
+			return (cnt * sizeof(long));
+		}
+    }
+    /* NOTREACHED */
+}
diff --git a/fads/fads.h b/fads/fads.h
new file mode 100644
index 0000000..0bd8e84
--- /dev/null
+++ b/fads/fads.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by FADS Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
+ * | MON8xx code           | 0xFE00_0100     Reset Vector
+ * +-----------------------+ 0xFE0?_????
+ * | (unused)              |
+ * +-----------------------+ 0xFE01_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0xFE01_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0xFE01_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0xFE01_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0xFE02_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/fads/flash.c b/fads/flash.c
new file mode 100644
index 0000000..ce28b44
--- /dev/null
+++ b/fads/flash.c
@@ -0,0 +1,754 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+
+int flash_write (uchar *, ulong, ulong);
+flash_info_t *addr2info (ulong);
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+static int  flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) 
+	{
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) 
+	{
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
+	}
+
+	if (FLASH_BASE1_PRELIM != 0x0) {
+		size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+		if (size_b1 > size_b0) {
+			printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",size_b1, size_b1<<20,size_b0, size_b0<<20);
+
+			flash_info[0].flash_id	= FLASH_UNKNOWN;
+			flash_info[1].flash_id	= FLASH_UNKNOWN;
+			flash_info[0].sector_count	= -1;
+			flash_info[1].sector_count	= -1;
+			flash_info[0].size		= 0;
+			flash_info[1].size		= 0;
+			return (0);
+		}
+	} else {
+		size_b1 = 0;
+	}
+
+	/* Remap FLASH according to real size */
+    memctl->memc_or0 = CFG_OR0_PRELIM;
+    memctl->memc_br0 = CFG_BR0_PRELIM;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+
+	if (size_b1) 
+	{
+		memctl->memc_or1 = CFG_OR1_PRELIM;
+		memctl->memc_br1 = CFG_BR1_PRELIM;
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[1]);
+	} 
+	else 
+	{
+	    memctl->memc_or1 = CFG_OR1_PRELIM;
+		memctl->memc_br1 = CFG_BR1_PRELIM;
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Check or set protection status for monitor sectors
+ *
+ * The monitor always occupies the _first_ part of the _first_ Flash bank.
+ */
+static int  flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
+{
+	ulong b_end = info->start[0] + info->size - 1;	/* bank end address */
+	int rc    =  0;
+	int first = -1;
+	int last  = -1;
+	int i;
+
+	if (to < info->start[0]) {
+		return (0);
+	}
+
+	for (i=0; i<info->sector_count; ++i) {
+		ulong end;		/* last address in current sect	*/
+		short s_end;
+
+		s_end = info->sector_count - 1;
+
+		end = (i == s_end) ? b_end : info->start[i + 1] - 1;
+
+		if (from > end) {
+			continue;
+		}
+		if (to < info->start[i]) {
+			continue;
+		}
+
+		if (from == info->start[i]) {
+			first = i;
+			if (last < 0) {
+				last = s_end;
+			}
+		}
+		if (to  == end) {
+			last  = i;
+			if (first < 0) {
+				first = 0;
+			}
+		}
+	}
+
+	for (i=first; i<=last; ++i) {
+		if (flag & FLAG_PROTECT_CLEAR) {
+			info->protect[i] = 0;
+		} else if (flag & FLAG_PROTECT_SET) {
+			info->protect[i] = 1;
+		}
+		if (info->protect[i]) {
+			rc = 1;
+		}
+	}
+	return (rc);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) 
+	{
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++) 
+		{
+			info->start[i] = base + (i * 0x00040000);
+		}
+	} 
+	else 
+	{
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		for (; i >= 0; i--) 
+		{
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) 
+	{
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) 
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) 
+	{
+		case FLASH_AM040B:	printf ("AM29F040B (4 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM040T:	printf ("AM29F040T (4 Mbit, top boot sect)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) 
+	{
+		if ((i % 5) == 0)
+		{
+			printf ("\n   ");
+		}
+		
+		printf (" %08lX%s",	info->start[i],info->protect[i] ? " (RO)" : "     "	);
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	uchar value;
+
+	/* Write auto select command: read Manufacturer ID */
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x90909090;
+#endif
+
+	value = addr[0];
+
+	switch (value) 
+	{
+		case AMD_MANUFACT:case 0x01:
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+	
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) 
+	{
+		case AMD_ID_F040B:
+			info->flash_id += FLASH_AM040B;
+			info->sector_count = 8;
+			info->size = 0x00200000;
+			break;				/* => 2 MB		*/
+
+		case AMD_ID_LV400T:
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;				/* => 1 MB		*/
+
+		case AMD_ID_LV400B:
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;				/* => 1 MB		*/
+
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;				/* => 2 MB		*/
+
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;				/* => 2 MB		*/
+
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;				/* => 4 MB		*/
+
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+		case AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;				/* => 8 MB		*/
+
+		case AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;				/* => 8 MB		*/
+#endif
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+#if 0
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#else
+	flash_get_offsets (addr, &flash_info[0]);
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) 
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) 
+	{
+		addr = (volatile unsigned long *)info->start[0];
+#if 0
+		*addr = 0x00F000F0;	/* reset bank */
+#else
+		*addr = 0xF0F0F0F0;	/* reset bank */
+#endif
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x80808080;
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+#endif
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+#if 0
+			addr[0] = 0x00300030;
+#else
+			addr[0] = 0x30303030;
+#endif
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+#if 0
+	while ((addr[0] & 0x00800080) != 0x00800080)
+#else
+	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+#endif
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#if 0
+	addr[0] = 0x00F000F0;	/* reset bank */
+#else
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+#endif
+
+	printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+		ulong b_end = info->start[0] + info->size;	/* bank end addr */
+		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+	/* finally write data to flash */
+	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+		
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0xA0A0A0A0;
+#endif
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+#if 0
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+#else
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+#endif
+	{
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/fads/lamp.c b/fads/lamp.c
new file mode 100644
index 0000000..e8bc2a0
--- /dev/null
+++ b/fads/lamp.c
@@ -0,0 +1,42 @@
+#include <config.h>
+#include <ppcboot.h>
+
+void
+signal_delay(unsigned int n)
+{
+  while (n--);
+}
+
+void
+signal_on(void)
+{
+  *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */
+}
+
+void
+signal_off(void)
+{
+  *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */
+}
+
+void
+slow_blink(unsigned int n)
+{
+  while (n--) {
+    signal_on();
+    signal_delay(0x00400000);
+    signal_off();
+    signal_delay(0x00400000);
+  }
+}
+
+void
+fast_blink(unsigned int n)
+{
+  while (n--) {
+    signal_on();
+    signal_delay(0x00100000);
+    signal_off();
+    signal_delay(0x00100000);
+  }
+}
diff --git a/fads/ppcboot.lds b/fads/ppcboot.lds
new file mode 100644
index 0000000..ab5dd07
--- /dev/null
+++ b/fads/ppcboot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+/*
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    ppc/ppcstring.o	(.text)
+    ppc/vsprintf.o	(.text)
+    ppc/crc32.o		(.text)
+    ppc/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got) 
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = 0x02840000;
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/fads/ppcboot.lds.dan b/fads/ppcboot.lds.dan
new file mode 100644
index 0000000..5ec0872
--- /dev/null
+++ b/fads/ppcboot.lds.dan
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    ppc/ppcstring.o	(.text)
+    ppc/vsprintf.o	(.text)
+    ppc/crc32.o		(.text)
+    ppc/zlib.o		(.text)
+
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got) 
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = 0x2840000;
+  .ppcenv 	:
+  {
+/*
+    . = env_offset;
+*/
+    common/environment.o(.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/fads/ppcboot.lds.debug b/fads/ppcboot.lds.debug
new file mode 100644
index 0000000..f19c233
--- /dev/null
+++ b/fads/ppcboot.lds.debug
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    ppc/vsprintf.o	(.text)
+    ppc/crc32.o		(.text)
+    ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got) 
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
diff --git a/include/commproc.h b/include/commproc.h
index 7022389..86b88a4 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -426,6 +426,27 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x00003d00)
 #endif	/* CONFIG_RPXLITE */
 
+/***  FADS850SAR  ********************************************************/
+
+#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
+/* This ENET stuff is for the MPC850SAR with ethernet on SCC2.  Some of
+ * this may be unique to the FADS850SAR configuration.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD		((ushort)0x0004)
+#define PA_ENET_TXD		((ushort)0x0008)
+#define PA_ENET_RCLK	((ushort)0x0200)
+#define PA_ENET_TCLK	((ushort)0x0800)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003d00)
+#endif	/* CONFIG_FADS850SAR */
+
 /***  BSEIP  **********************************************************/
 
 #ifdef CONFIG_BSEIP
diff --git a/include/config_FADS850SAR.h b/include/config_FADS850SAR.h
new file mode 100644
index 0000000..67800c2
--- /dev/null
+++ b/include/config_FADS850SAR.h
@@ -0,0 +1,410 @@
+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * 1999-nov-26: The FADS is using the following physical memorymap:
+ *
+ * ff020000 -> ff02ffff : pcmcia   
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom 
+ * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_MPC850		1
+#define CONFIG_MPC850SAR	1
+#define CONFIG_FADS			1	
+
+#define CONFIG_8xx_CPUCLOCK	50
+#define CONFIG_8xx_BUSCLOCK	(CONFIG_8xx_CPUCLOCK)
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_BAUDRATE		9600
+
+#if 0
+#define MPC8XX_FACT	10				/* Multiply by 10		*/
+#define MPC8XX_XIN	50000000		/* 50 MHz in	*/
+#else
+#define MPC8XX_FACT	12				/* Multiply by 12 */
+#define MPC8XX_XIN	4000000			/* 4 MHz in */
+#endif
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#if 1
+#define CONFIG_8xx_BOOTDELAY	-1	/* autoboot disabled		*/
+#define CONFIG_8xx_TFTP_MODE
+#else
+#define CONFIG_8xx_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#undef	CONFIG_8xx_TFTP_MODE
+#endif
+
+#define CONFIG_DRAM_SPEED	(CONFIG_8xx_BUSCLOCK)	/* MHz		*/
+#define CONFIG_BOOTCOMMAND	"bootm 02880000"	/* autoboot command */
+#define CONFIG_BOOTARGS		" "
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		8		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00800000	/* 4 ... 8 MB in DRAM	*/
+
+#define CFG_TFTP_LOADADDR	0x00100000	/* default load address */
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR			0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x02800000
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#if 0
+#define	CFG_MONITOR_LEN		(256 << 10)					/* Reserve 128 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(512 << 10)					/* Reserve 512 kB for Monitor	*/
+#endif
+#define	CFG_MALLOC_LEN		(256 << 10)					/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1			/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8			/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_ENV_OFFSET 0x00040000	/* Offset of Environment Sector */
+#define	CFG_FLASH_ENV_SIZE	0x40000	/* Total Size of Environment Sector	*/
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+/* values according to the manual */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16			/* For all MPC8xx CPUs			*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration						11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer  *
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR       (SCCR_TBS     | \
+				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+				SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ * 
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+
+#define BCSR_ADDR		((uint) 0x02100000)
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+
+/* values according to the manual */
+
+
+#define PCMCIA_MEM_ADDR		((uint)0xff020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+ 
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+ 
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      (23)
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+ 
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+ 
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VCCO               ((uint)0x02000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC850
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC50 */
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*
+ * MPC8xx CPM Options
+ */
+#define CONFIG_SCC_ENET 1
+#define CONFIG_SCC1_ENET 1
+#define CONFIG_FEC_ENET 1
+#undef  CONFIG_CPM_IIC
+#undef  CONFIG_UCODE_PATCH
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    2
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/config_FADS860T.h b/include/config_FADS860T.h
new file mode 100644
index 0000000..1020f25
--- /dev/null
+++ b/include/config_FADS860T.h
@@ -0,0 +1,367 @@
+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * 1999-nov-26: The FADS is using the following physical memorymap:
+ *
+ * ff020000 -> ff02ffff : pcmcia   
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom 
+ * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_FADS			1	
+
+#define CONFIG_8xx_CPUCLOCK	50
+#define CONFIG_8xx_BUSCLOCK	(CONFIG_8xx_CPUCLOCK)
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_BAUDRATE		9600
+
+#define MPC8XX_FACT	10				/* Multiply by 10		*/
+#define MPC8XX_XIN	50000000		/* 50 MHz in	*/
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#if 1
+#define CONFIG_8xx_BOOTDELAY	-1	/* autoboot disabled		*/
+#define CONFIG_8xx_TFTP_MODE
+#else
+#define CONFIG_8xx_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#undef	CONFIG_8xx_TFTP_MODE
+#endif
+
+#define CONFIG_DRAM_SPEED	(CONFIG_8xx_BUSCLOCK)	/* MHz		*/
+#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command */
+#define CONFIG_BOOTARGS		" "
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		8		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0800000	/* 4 ... 8 MB in DRAM	*/
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR			0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define	CFG_MONITOR_LEN		(256 << 10)					/* Reserve 128 kB for Monitor	*/
+#define CFG_HWINFO_LEN		0x0040						/* Length of HW Info Data	*/
+#define CFG_HWINFO_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
+#define	CFG_MALLOC_LEN		(256 << 10)					/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2			/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8			/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_FLASH_ENV_ALIGN	15	/*  Bitshift for Environment Sector	*/
+#define	CFG_FLASH_ENV_SIZE	0x4000	/* Total Size of Environment Sector	*/
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+/* values according to the manual */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16			/* For all MPC8xx CPUs			*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration						11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29) 
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << 20) | 0x4000)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ * 
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+
+#define BCSR_ADDR		((uint) 0xFF010000)
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFF010000	/* FLASH bank #0	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFF00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+
+/* values according to the manual */
+
+
+#define PCMCIA_MEM_ADDR		((uint)0xff020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+ 
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+ 
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      (23)
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+ 
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+ 
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#define BCSR4_VCCO               ((uint)0x02000000)
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*
+ * MPC8xx CPM Options
+ */
+#define CONFIG_SCC_ENET 1
+#define CONFIG_SCC1_ENET 1
+#define CONFIG_FEC_ENET 1
+#undef  CONFIG_CPM_IIC
+#undef  CONFIG_UCODE_PATCH
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    2
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/flash.h b/include/flash.h
index aeb112a..e3f0142 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -61,6 +61,8 @@ void	flash_erase	 (flash_info_t *, int, int);
 #define FUJ_MANUFACT	0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
 #define SST_MANUFACT	0x00BF00BF	/* SST     manuf. ID in D23..D16, D7..D0 */
 
+#define AMD_ID_F040B	0xA4		/* 29F040B ID  ( 4 M, bottom boot sect)	*/
+
 #define AMD_ID_LV400T	0x22B922B9	/* 29LV400T ID ( 4 M, top boot sector)	*/
 #define AMD_ID_LV400B	0x22BA22BA	/* 29LV400B ID ( 4 M, bottom boot sect)	*/
 
@@ -82,17 +84,19 @@ void	flash_erase	 (flash_info_t *, int, int);
  * Internal FLASH identification codes
  */
 
-#define FLASH_AM400T	0x00		/* AMD AM29LV400			*/
-#define FLASH_AM400B	0x01
-#define FLASH_AM800T	0x02		/* AMD AM29LV800			*/
-#define FLASH_AM800B	0x03
-#define FLASH_AM160T	0x04		/* AMD AM29LV160			*/
-#define FLASH_AM160B	0x05
-#define FLASH_AM320T	0x06		/* AMD AM29LV320			*/
-#define FLASH_AM320B	0x07
-
-#define	FLASH_SST200A	0x08		/* SST 39xF200A ID ( 2M = 128K x 16 )	*/
-#define	FLASH_SST400A	0x0A		/* SST 39xF400A ID ( 4M = 256K x 16 )	*/
+#define FLASH_AM040T	0x00		/* AMD AM29F040			*/
+#define FLASH_AM040B	0x01
+#define FLASH_AM400T	0x02		/* AMD AM29LV400			*/
+#define FLASH_AM400B	0x03
+#define FLASH_AM800T	0x04		/* AMD AM29LV800			*/
+#define FLASH_AM800B	0x05
+#define FLASH_AM160T	0x06		/* AMD AM29LV160			*/
+#define FLASH_AM160B	0x07
+#define FLASH_AM320T	0x08		/* AMD AM29LV320			*/
+#define FLASH_AM320B	0x09
+
+#define	FLASH_SST200A	0x0A		/* SST 39xF200A ID ( 2M = 128K x 16 )	*/
+#define	FLASH_SST400A	0x0B		/* SST 39xF400A ID ( 4M = 256K x 16 )	*/
 #define	FLASH_SST800A	0x0C		/* SST 39xF800A ID ( 8M = 512K x 16 )	*/
 
 #define FLASH_UNKNOWN	0xFF		/* unknown flash type			*/
diff --git a/mpc8xx/cpu_init.c b/mpc8xx/cpu_init.c
index 757ca9f..f9b2b3b 100644
--- a/mpc8xx/cpu_init.c
+++ b/mpc8xx/cpu_init.c
@@ -79,7 +79,7 @@ cpu_init_f (volatile immap_t *immr)
      */
 
     /* perform BR0 reset that MPC850 Rev. A can't guarantee */
-    memctl->memc_br0 = 0x00000001;	/* just "bank valid" bit */
+    memctl->memc_br0 |= 0x00000001;	/* just "bank valid" bit */
 
     /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
      * addresses - these have to be modified later when FLASH size
diff --git a/mpc8xx/interrupts.c b/mpc8xx/interrupts.c
index 412354a..5a27489 100644
--- a/mpc8xx/interrupts.c
+++ b/mpc8xx/interrupts.c
@@ -292,7 +292,10 @@ void timer_interrupt(struct pt_regs *regs)
 	printf ("*** Timer Interrupt *** ");
 #endif
 	/* Reset Timer Expired and Timers Interrupt Status */
-	immr->im_clkrst.car_plprcr = PLPRCR_TEXPS | PLPRCR_TMIST;
+	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+	__asm__("nop");
+	immr->im_clkrst.car_plprcr = PLPRCR_TEXPS | PLPRCR_TMIST |
+			(immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK);
 	/* Restore Decrementer Count */
 	set_dec (decrementer_count);
 
diff --git a/mpc8xx/scc.c b/mpc8xx/scc.c
index 535ffd5..007be1a 100644
--- a/mpc8xx/scc.c
+++ b/mpc8xx/scc.c
@@ -174,7 +174,7 @@ int eth_rx(void)
 
 /**************************************************************
   *
-  * SCC2 Ethernet Initializtion Routine
+  * SCC2 Ethernet Initialization Routine
   *
   *************************************************************/
 
@@ -368,6 +368,10 @@ int eth_init(bd_t *bis)
    immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
                                      /* | SCC_PMSR_BRO | SCC_PMSR_PRO */);
 
+#if defined(CONFIG_FADS)
+   *((uint *) BCSR1) &= ~BCSR1_ETHEN;
+   *((uint *) BCSR4) |= BCSR4_DATA_VOICE;
+#endif
 
     /*
      * Configure Ethernet TENA Signal
@@ -379,7 +383,8 @@ int eth_init(bd_t *bis)
     immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
 #endif
 
-#if (defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || defined(CONFIG_TQM855L))
+#if (defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
+	 defined(CONFIG_TQM855L) || defined(CONFIG_MPC850SAR))
     immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
     immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
 #endif
diff --git a/mpc8xx/serial.c b/mpc8xx/serial.c
index 6d6c471..13a81cf 100644
--- a/mpc8xx/serial.c
+++ b/mpc8xx/serial.c
@@ -29,14 +29,12 @@
 #define	SMC_INDEX	0
 #define PROFF_SMC	PROFF_SMC1
 #define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
-#define FADS_BCSR1	0x01000000
 
 #elif defined(CONFIG_8xx_CONS_SMC2)	/* Console on SMC2 */
 
 #define SMC_INDEX	1
 #define PROFF_SMC	PROFF_SMC2
 #define CPM_CR_CH_SMC	CPM_CR_CH_SMC2
-#define FADS_BCSR1	0x00040000
 
 #else /* CONFIG_8xx_CONS_SMC? */
 #error "console not correctly defined"
@@ -93,6 +91,15 @@ serial_init (ulong cpu_clock, int baudrate)
 	cp->cp_pbdir &= ~0x00000c00;
 	cp->cp_pbodr &= ~0x00000c00;
 # endif	
+#endif
+
+#if defined(CONFIG_FADS)
+	/* Enable RS232 */
+#if defined(CONFIG_8xx_CONS_SMC1)
+	*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
+#else
+	*((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
+#endif
 #endif
 
 	/* Allocate space for two buffer descriptors in the DP ram.
diff --git a/mpc8xx/start.S b/mpc8xx/start.S
index d3de5e9..d35d405 100644
--- a/mpc8xx/start.S
+++ b/mpc8xx/start.S
@@ -71,6 +71,9 @@
 
 	GOT_ENTRY(_end)
 	GOT_ENTRY(.bss)
+#if defined(CONFIG_FADS)
+	GOT_ENTRY(environment)
+#endif
 	END_GOT
 
 /*
@@ -644,7 +647,16 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(.bss)
+#if defined(CONFIG_FADS)
+	/*
+	 * For the FADS - the environment is the very last item in flash.
+	 * The real .bss stops just before environment starts, so only
+	 * clear up to that point.
+	 */
+	lwz r4,GOT(environment)
+#else
 	lwz	r4,GOT(_end)
+#endif
 
 	cmplw	0, r3, r4
 	beq	6f