From: Charlene Liu <charlene.liu@amd.com>
Date: Mon, 29 Jul 2019 15:59:33 +0000 (-0400)
Subject: drm/amd/display: enable dcn_mem_pwr as golden setting updates
X-Git-Tag: v5.4-rc1~106^2~7^2~144
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=79e005204f75b54db9e42a39b3f66fac2ba190b9;p=users%2Fwilly%2Fxarray.git

drm/amd/display: enable dcn_mem_pwr as golden setting updates

Enable dcn_mem_pwr as golden setting updates

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4e9ac051d3d8..fa8a73f6c8e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -142,8 +142,7 @@ void dcn20_display_init(struct dc *dc)
 	/* DCCG */
 	dcn20_dccg_init(hws);
 
-	/* Disable all memory low power mode. All memories are enabled. */
-	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
+	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
 
 	/* DCHUB/MMHUBBUB
 	 * set global timer refclk divider