From: wdenk Date: Tue, 24 Apr 2001 23:52:48 +0000 (+0000) Subject: Added support for CU824 board (work in progress) X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=774dc34a365543363f4cfddea31d398f1a77b3f3;p=users%2Frw%2Fppcboot.git Added support for CU824 board (work in progress) --- diff --git a/CHANGELOG b/CHANGELOG index bd95537..09e7df7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,10 @@ To do: Modifications for 0.9.1: ====================================================================== +* Added support for CU824 board (work in progress) + +* Added support for PCU_E board (work in progress) + * Fix for ppc405gp ethernet code (Patch by Stefan Roese 24 Apr 2001) diff --git a/MAKEALL b/MAKEALL index 994b8d7..512b228 100755 --- a/MAKEALL +++ b/MAKEALL @@ -44,6 +44,7 @@ LIST="$LIST \ LIST="$LIST \ Sandpoint8240 \ + CU824 \ " ######################################################################### diff --git a/Makefile b/Makefile index 1d8d021..7112eba 100644 --- a/Makefile +++ b/Makefile @@ -340,6 +340,14 @@ Sandpoint8240_config: unconfig echo "CPU = mpc8240" >>config.mk ; \ echo "#include " >config.h +CU824_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = cu824" >>config.mk ; \ + echo "CPU = mpc8240" >>config.mk ; \ + echo "#include " >config.h + ######################################################################### ## MPC8260 Systems ######################################################################### diff --git a/board/cu824/Makefile b/board/cu824/Makefile new file mode 100644 index 0000000..0ab337c --- /dev/null +++ b/board/cu824/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ns16550.o serial.o speed.o dc2114x.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cu824/config.mk b/board/cu824/config.mk new file mode 100644 index 0000000..a5b7e16 --- /dev/null +++ b/board/cu824/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Sandpoint boards +# + +TEXT_BASE = 0xFF000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c new file mode 100644 index 0000000..53f476b --- /dev/null +++ b/board/cu824/cu824.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define BOARD_REV_REG 0xFE80002B + +int checkboard(void) +{ + char revision = *(volatile char *)(BOARD_REV_REG); + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("CU824 "); + printf("Revision %d ", revision); + printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); + + return 0; +} + +long int initdram(int board_type) +{ +#if 0 + int val; + + printf("\n"); +#if 1 + CONFIG_READ_HALFWORD(PCICR, val); + printf("PCICR = 0x%04X\n", val); + CONFIG_READ_WORD(PICR1, val); + printf("PICR1 = 0x%08X\n", val); + CONFIG_READ_HALFWORD(PCISR, val); + printf("PCISR = 0x%04X\n", val); + CONFIG_READ_WORD(PICR2, val); + printf("PICR2 = 0x%08X\n", val); + CONFIG_READ_WORD(EUMBBAR, val); + printf("EMUMBAR = 0x%08X\n", val); + CONFIG_READ_WORD(MCCR1, val); + printf("MCCR1 = 0x%08X\n", val); + CONFIG_READ_WORD(MCCR2, val); + printf("MCCR2 = 0x%08X\n", val); + CONFIG_READ_WORD(MCCR3, val); + printf("MCCR3 = 0x%08X\n", val); + CONFIG_READ_WORD(MCCR4, val); + printf("MCCR4 = 0x%08X\n", val); + CONFIG_READ_WORD(MSAR1, val); + printf("MSAR1 = 0x%08X\n", val); + CONFIG_READ_WORD(EMSAR1, val); + printf("EMSAR1 = 0x%08X\n", val); + CONFIG_READ_WORD(MSAR2, val); + printf("MSAR2 = 0x%08X\n", val); + CONFIG_READ_WORD(EMSAR2, val); + printf("EMSAR2 = 0x%08X\n", val); + CONFIG_READ_WORD(MEAR1, val); + printf("MEAR1 = 0x%08X\n", val); + CONFIG_READ_WORD(EMEAR1, val); + printf("EMEAR1 = 0x%08X\n", val); + CONFIG_READ_WORD(MEAR2, val); + printf("MEAR2 = 0x%08X\n", val); + CONFIG_READ_WORD(EMEAR2, val); + printf("EMEAR2 = 0x%08X\n", val); + CONFIG_READ_BYTE(ODCR, val); + printf("ORCR = 0x%02X\n", val); + CONFIG_READ_BYTE(MBER, val); + printf("MBER = 0x%02X\n", val); +#endif + CONFIG_READ_WORD(MCCR1, val); + CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); //set memory access going + __asm__ __volatile__("eieio"); + CONFIG_READ_WORD(MCCR1, val); + printf("MCCR1 = 0x%08X\n", val); + + printf("IBAT0L = 0x%08X\n", mfspr(IBAT0L)); + printf("IBAT0U = 0x%08X\n", mfspr(IBAT0U)); + printf("IBAT1L = 0x%08X\n", mfspr(IBAT1L)); + printf("IBAT1U = 0x%08X\n", mfspr(IBAT1U)); + printf("IBAT2L = 0x%08X\n", mfspr(IBAT2L)); + printf("IBAT2U = 0x%08X\n", mfspr(IBAT2U)); + printf("IBAT3L = 0x%08X\n", mfspr(IBAT3L)); + printf("IBAT3U = 0x%08X\n", mfspr(IBAT3U)); + printf("DBAT0L = 0x%08X\n", mfspr(DBAT0L)); + printf("DBAT0U = 0x%08X\n", mfspr(DBAT0U)); + printf("DBAT1L = 0x%08X\n", mfspr(DBAT1L)); + printf("DBAT1U = 0x%08X\n", mfspr(DBAT1U)); + printf("DBAT2L = 0x%08X\n", mfspr(DBAT2L)); + printf("DBAT2U = 0x%08X\n", mfspr(DBAT2U)); + printf("DBAT3L = 0x%08X\n", mfspr(DBAT3L)); + printf("DBAT3U = 0x%08X\n", mfspr(DBAT3U)); + + printf("huy = 0x%08X\n", (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | + (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); + printf("huy = 0x%08X\n", (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | + (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO); +#endif + + return CFG_RAM_SIZE; +} + + diff --git a/board/cu824/dc2114x.c b/board/cu824/dc2114x.c new file mode 100644 index 0000000..9910c55 --- /dev/null +++ b/board/cu824/dc2114x.c @@ -0,0 +1,381 @@ +#include +#include +#include + + /* PCI Registers. + */ +#define PCI_VENDOR_ID 0x00 +#define PCI_COMMAND 0x04 +#define PCI_CLASS_REVISION 0x08 +#define PCI_LATENCY_TIMER 0x0d +#define PCI_BASE_ADDRESS_0 0x10 +#define PCI_CFDA_PSM 0x43 + +#define PCI_COMMAND_IO 0x1 +#define PCI_COMMAND_MASTER 0x4 + +#define CFRV_RN 0x000000f0 /* Revision Number */ +#define CBIO_MASK -128 + +#define WAKEUP 0x00 /* Power Saving Wakeup */ +#define SLEEP 0x80 /* Power Saving Sleep Mode */ + + +#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ +#define DC2114x_DID 0x1900 /* Unique Device ID # */ +#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ +#define DC21142 (DC2114x_DID | 0x0010) +#define DC21143 (DC2114x_DID | 0x0030) + +#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) + + /* Ethernet chip registers. + */ +#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */ +#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */ +#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */ +#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */ +#define DE4X5_STS iobase + 0x028 /* Status Register */ +#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */ +#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */ + + + /* Register bits. + */ +#define BMR_SWR 0x00000001 /* Software Reset */ +#define STS_TS 0x00700000 /* Transmit Process State */ +#define STS_RS 0x000e0000 /* Receive Process State */ +#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ +#define OMR_SR 0x00000002 /* Start/Stop Receive */ + + + /* Descriptor bits. + */ +#define R_OWN 0x80000000 /* Own Bit */ +#define RD_RER 0x02000000 /* Receive End Of Ring */ +#define TD_TER 0x02000000 /* Transmit End Of Ring */ +#define T_OWN 0x80000000 /* Own Bit */ +#define TD_LS 0x40000000 /* Last Segment */ +#define TD_FS 0x20000000 /* First Segment */ +#define R_OWN 0x80000000 /* Own Bit */ +#define RD_LS 0x00000100 /* Last Descriptor */ +#define RD_ES 0x00008000 /* Error Summary */ + +#define POLL_DEMAND 1 + +#define RESET_DE4X5 {\ + int i;\ + i=inl(DE4X5_BMR);\ + udelay(1000);\ + outl(i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ + outl(i, DE4X5_BMR);\ + udelay(1000);\ + for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\ + udelay(1000);\ +} + +#define START_DE4X5 {\ + s32 omr; \ + omr = inl(DE4X5_OMR);\ + omr |= OMR_ST | OMR_SR;\ + outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ +} + +#define STOP_DE4X5 {\ + s32 omr; \ + omr = inl(DE4X5_OMR);\ + omr &= ~(OMR_ST|OMR_SR);\ + outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ +} + +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 1 /* Number of TX descriptors */ +#define RX_BUFF_SZ PKTSIZE + +#define TOUT_LOOP 1000000 + +struct de4x5_desc { + volatile s32 status; + u32 des1; + u32 buf; + u32 next; +}; + + +static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ +static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ +static int rx_new; /* RX descriptor ring pointer */ +static int tx_new; /* TX descriptor ring pointer */ + +static char rxRingSize; +static char txRingSize; + +static u_long iobase; + +static inline int inl(u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr + 0xfe000000)); +} + +static inline void outl (int command, u_long addr) +{ + *(volatile u_long *)(addr + 0xfe000000) = cpu_to_le32(command); +} + +int eth_init(bd_t *bis) +{ + int i, status = 0; + int vendor, device, l; + int cfrv; + unsigned char timer; + + + CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, l); + + l >>= 8; + + if (l != 0x00020000) + { + printf("Error: Can not find an ethernet card on the PCI bus %d " + "in slot %d\n", CFG_ETH_DEV_FN >> 16, + (CFG_ETH_DEV_FN & 0xFFFF) >> 11); + goto Done; + } + + CONFIG_READ_WORD(0x80000000 | PCI_VENDOR_ID | CFG_ETH_DEV_FN, vendor); + + device = (vendor >> 16) & 0xffff; + vendor = vendor & 0xffff; + device = device << 8; + + if (! is_DC2114x) + { + printf("Error: The chip is not DC2114x.\n"); + goto Done; + } + + /* Get the chip configuration revision register. + */ + CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, + cfrv); + + device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); + + if (device != DC21143) + { + printf("Error: The chip is not DC21143.\n"); + goto Done; + } + + /* Check if I/O accesses and Bus Mastering are enabled. + */ + CONFIG_READ_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, status); + + if (!(status & PCI_COMMAND_IO)) + { + status |= PCI_COMMAND_IO; + CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, + status); + CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, + status); + } + + if (!(status & PCI_COMMAND_IO)) + { + printf("Error: Can not enable I/O access.\n"); + goto Done; + } + + if (!(status & PCI_COMMAND_MASTER)) + { + status |= PCI_COMMAND_MASTER; + CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, + status); + CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, + status); + } + if (!(status & PCI_COMMAND_MASTER)) + { + printf("Error: Can not enable Bus Mastering.\n"); + goto Done; + } + + /* Check the latency timer for values >= 0x60. + */ + CONFIG_READ_BYTE(0x80000000 | PCI_LATENCY_TIMER | CFG_ETH_DEV_FN, + timer); + if (timer < 0x60) + { + CONFIG_WRITE_BYTE(0x80000000 | PCI_LATENCY_TIMER | + CFG_ETH_DEV_FN, + 0X60); + } + + /* Set I/O base register. + */ + CONFIG_WRITE_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN, + CFG_ETH_IOBASE); + + CONFIG_READ_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN, + iobase); + + if (iobase == 0xffffffff) + { + printf("Error: Can not set I/O base register.\n"); + goto Done; + } + + iobase &= CBIO_MASK; + + /* Ensure we're not sleeping. + */ + CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, WAKEUP); + + udelay(10 * 1000); + + RESET_DE4X5; + + if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) + { + printf("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + for (i = 0; i < NUM_RX_DESC; i++) + { + rx_ring[i].status = cpu_to_le32(R_OWN); + rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); + rx_ring[i].buf = cpu_to_le32((u_long)NetRxPackets[i]); + rx_ring[i].next = 0; + } + + for (i=0; i < NUM_TX_DESC; i++) + { + tx_ring[i].status = 0; + tx_ring[i].des1 = 0; + tx_ring[i].buf = 0; + tx_ring[i].next = 0; + } + + rxRingSize = NUM_RX_DESC; + txRingSize = NUM_TX_DESC; + + /* Write the end of list marker to the descriptor lists. + */ + rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); + tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); + + /* Tell the adapter where the TX/RX rings are located. + */ + outl((u_long)&rx_ring, DE4X5_RRBA); + outl((u_long)&tx_ring, DE4X5_TRBA); + + START_DE4X5; + + tx_new = 0; + rx_new = 0; + +Done: + + return 0; +} + +int eth_send(volatile void *packet, int length) +{ + int status = 0; + int i; + + if (length <= 0) + { + printf("eth: bad packet size: %d\n", length); + goto out; + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) + { + if (i >= TOUT_LOOP) + { + printf("eth: tx error buffer not ready\n"); + goto out; + } + } + + tx_ring[tx_new].buf = cpu_to_le32((u_long)packet); + tx_ring[tx_new].des1 |= cpu_to_le32(TD_TER | TD_LS | TD_FS | length); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + outl(POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) + { + if (i >= TOUT_LOOP) + { + printf("eth: tx buffer not ready\n"); + goto out; + } + } + + out: + return status; +} + +int eth_rx(void) +{ + s32 status; + int length = 0; + + for ( ; ; ) + { + status = (s32)le32_to_cpu(rx_ring[rx_new].status); + + if (status & R_OWN) + { + break; + } + + if (status & RD_LS) + { + /* Valid frame status. + */ + if (status & RD_ES) + { + /* There was an error. + */ + printf("RX error status = 0x%08X\n", status); + } + else + { + /* A valid frame received. + */ + length = (le32_to_cpu(rx_ring[rx_new].status) >> + 16); + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive(NetRxPackets[rx_new], length - 4); + } + + /* Change buffer ownership for this frame, back + * to the adapter. + */ + rx_ring[rx_new].status = cpu_to_le32(R_OWN); + } + + /* Update entry information. + */ + rx_new = (++rx_new) % rxRingSize; + } + + return length; +} + +void eth_halt(void) +{ + STOP_DE4X5; + outl(0, DE4X5_SICR); + CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, SLEEP); +} + + diff --git a/board/cu824/flash.c b/board/cu824/flash.c new file mode 100644 index 0000000..ff4e09b --- /dev/null +++ b/board/cu824/flash.c @@ -0,0 +1,393 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x40000 +#define PARAM_SECT_SIZE 0x8000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static int write_data (flash_info_t *info, ulong dest, uchar *data); +static void write_via_fpu(volatile ulong *addr, uchar *data); +static __inline__ unsigned long get_msr(void); +static __inline__ void set_msr(unsigned long msr); + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + int i, j; + unsigned long size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + flash_info[i].flash_id = 0x008988F4; + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + for (j = 0; j < flash_info[i].sector_count; j++) + { + if (j <= 7) + { + flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * PARAM_SECT_SIZE; + } + else + { + flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + (j - 7) * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("Intel: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) + { + case 0x88F4: + printf("28F160F3B (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) + { + if ((i % 5) == 0) + { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +void flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + printf ("Can erase only Intel flash types - aborted\n"); + return; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00500050; /* clear status register */ + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & 0x00800080) != 0x00800080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00B000B0; /* suspend erase */ + *addr = 0x00FF00FF; /* reset to read mode */ + return; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 8 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp, msr; + int l, rc; + unsigned char data[8]; + u_long *datah = (u_long *)&data[0]; + u_long *datal = (u_long *)&data[4]; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { +#if 0 + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + *datah = *(u_long *)src; + *datal = *(u_long *)(src + 4); + if ((rc = write_data(info, wp, data)) != 0) { + set_msr(msr); + return (rc); + } + wp += FLASH_WIDTH; + cnt -= FLASH_WIDTH; + src += FLASH_WIDTH; + } + set_msr(msr); + + if (cnt == 0) { + return (0); + } + +#if 0 + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i CFG_FLASH_WRITE_TOUT) { + *addr = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + */ +static void write_via_fpu(volatile ulong *addr, uchar *data) +{ +__asm__ __volatile__ ( + "lfd 1, 0(%0)\n + stfd 1, 0(%1)\n" + : + : "r" (data), "r" (addr) +); +} +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + + diff --git a/board/cu824/ns16550.c b/board/cu824/ns16550.c new file mode 100644 index 0000000..1875b70 --- /dev/null +++ b/board/cu824/ns16550.c @@ -0,0 +1,61 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ + +#include +#include "ns16550.h" + +typedef struct NS16550 *NS16550_t; + +const NS16550_t COM_PORTS[] = { (NS16550_t) (0xfe8000a0), + (NS16550_t) (0xfe8000e0) }; + +volatile struct NS16550 * +NS16550_init(int chan, int baud_divisor) +{ + volatile struct NS16550 *com_port; + com_port = (struct NS16550 *) COM_PORTS[chan]; + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; /* Access baud rate */ + com_port->dll = baud_divisor & 0xff; /* 9600 baud */ + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ + com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ +return (com_port); +} + +void +NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; /* Access baud rate */ + com_port->dll = baud_divisor & 0xff; /* 9600 baud */ + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ + com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ +} + +void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c) +{ + while ((com_port->lsr & LSR_THRE) == 0) ; + com_port->thr = c; +} + +unsigned char +NS16550_getc(volatile struct NS16550 *com_port) +{ + while ((com_port->lsr & LSR_DR) == 0) ; + return (com_port->rbr); +} + +int NS16550_tstc(volatile struct NS16550 *com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} + + + diff --git a/board/cu824/ns16550.h b/board/cu824/ns16550.h new file mode 100644 index 0000000..cd8815c --- /dev/null +++ b/board/cu824/ns16550.h @@ -0,0 +1,74 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + */ + + +struct NS16550 + { + unsigned long rbr; /* 0 */ + unsigned long ier; /* 1 */ + unsigned long fcr; /* 2 */ + unsigned long lcr; /* 3 */ + unsigned long mcr; /* 4 */ + unsigned long lsr; /* 5 */ + unsigned long msr; /* 6 */ + unsigned long scr; /* 7 */ + }; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +#define FCR_FIFO_EN 0x01 /*fifo enable*/ +#define FCR_RXSR 0x02 /*reciever soft reset*/ +#define FCR_TXSR 0x04 /*transmitter soft reset*/ + + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + + +#define LCR_WLS_MSK 0x03 /* character length slect mask*/ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble*/ +#define LCR_EPS 0x10 /* Even Parity Select*/ +#define LCR_STKP 0x20 /* Stick Parity*/ +#define LCR_SBRK 0x40 /* Set Break*/ +#define LCR_BKSE 0x80 /* Bank select enable*/ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +/* useful defaults for LCR*/ +#define LCR_8N1 0x03 + + +#define COM1 0x03F8 +#define COM2 0x02F8 + +volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); +void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); +unsigned char NS16550_getc(volatile struct NS16550 *com_port); +int NS16550_tstc(volatile struct NS16550 *com_port); +void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); + diff --git a/board/cu824/ppcboot.lds b/board/cu824/ppcboot.lds new file mode 100644 index 0000000..77d9da0 --- /dev/null +++ b/board/cu824/ppcboot.lds @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8240/start.o (.text) + common/board.o (.text) + ppc/ppcstring.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/zlib.o (.text) + + . = env_offset; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/cu824/serial.c b/board/cu824/serial.c new file mode 100644 index 0000000..d12297c --- /dev/null +++ b/board/cu824/serial.c @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "ns16550.h" + +volatile struct NS16550 *console; + +void +serial_init (unsigned long dummy, int baudrate) +{ + int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate; + + console = NS16550_init(CONFIG_CONS_INDEX - 1, clock_divisor); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + { + serial_putc ('\r'); + } + NS16550_putc(console, c); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + + +int +serial_getc(void) +{ + return NS16550_getc(console); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(console); +} + +void +serial_setbrg (unsigned long dummy, int baudrate) +{ + int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate; + + NS16550_reinit(console, clock_divisor); +} diff --git a/board/cu824/speed.c b/board/cu824/speed.c new file mode 100644 index 0000000..c122687 --- /dev/null +++ b/board/cu824/speed.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +static char pll_to_bus_factor[] = +{ + 3, 0, 0, 0, 0, + 0, 0, 0, 1, 0, + 0, 0, 2, 0, 2, + 0, 3, 0, 0, 0, + 2, 0, 0, 0 +}; + +#define PLL_STATE_REG 0xFE80002F + +ulong get_bus_freq(ulong ignore) +{ + unsigned char pll = *(volatile char *) (PLL_STATE_REG); + + if (pll == 24) + { + return CONFIG_SYS_CLK_FREQ * 5 / 2; + } + else + { + return CONFIG_SYS_CLK_FREQ * pll_to_bus_factor[pll]; + } +} + +/* ------------------------------------------------------------------------- */ + +/* + * Measure CPU clock speed + */ + +/* Table to convert pllratio to actual processor clock scaling factor (*10) + */ +#ifdef CONFIG_MPC8240 +short pllratio_to_factor[] = { + 00, 00, 00, 10, 20, 20, 25, 00, 00, 00, 00, 00, 00, 00, 00, 00, + 00, 00, 00, 10, 00, 00, 00, 45, 30, 00, 40, 00, 00, 00, 35, 00, +}; +#endif + +ulong get_gclk_freq(void) +{ + uint hid1 = mfspr(HID1); + +#ifdef CONFIG_MPC8240 + + /* 5 bits for PLL ration on 8240 + */ + hid1 = (hid1 >> (32-5)) & 0x1f; +#else + + /* 4 bits on everythings else + */ + hid1 = (hid1 >> (32-4)) & 0xf; +#endif + + return (pllratio_to_factor[hid1] * get_bus_freq(0)) / 10; +} + +/* ------------------------------------------------------------------------- */ + diff --git a/cpu/mpc8240/config.mk b/cpu/mpc8240/config.mk index 05222ea..00f3988 100644 --- a/cpu/mpc8240/config.mk +++ b/cpu/mpc8240/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -ffixed-r14 +PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 PLATFORM_CPPFLAGS += -DCONFIG_MPC8240 -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc8240/cpu.c b/cpu/mpc8240/cpu.c index ceeda07..dc5fb6e 100644 --- a/cpu/mpc8240/cpu.c +++ b/cpu/mpc8240/cpu.c @@ -30,6 +30,7 @@ int checkcpu(long clock) unsigned int pvr = get_pvr(); unsigned int version = pvr >>16; unsigned int revision = pvr &0xffff; + char buf[32]; switch(version) { @@ -46,10 +47,13 @@ int checkcpu(long clock) printf(" Revsion %d.%d",revision>>8, revision & 0xff); } - printf(" at %lu MHz:", clock); + printf(" at %s MHz:", strmhz(buf, clock)); printf(" %u kB I-Cache", checkicache() >> 10); printf(" %u kB D-Cache", checkdcache() >> 10); + + printf("\n"); + return 0; } @@ -117,7 +121,11 @@ unsigned long get_tbclk (void) init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET); +#ifdef CONFIG_CU824 + tbclk = CONFIG_SYS_CLK_FREQ; +#else tbclk = (idata->cpu_clk + 3L) / 4L; +#endif return (tbclk); } diff --git a/cpu/mpc8240/cpu_init.c b/cpu/mpc8240/cpu_init.c index 7aae577..c3f67fb 100644 --- a/cpu/mpc8240/cpu_init.c +++ b/cpu/mpc8240/cpu_init.c @@ -35,12 +35,12 @@ void cpu_init_f (void) { register unsigned long val; - CONFIG_WRITE_WORD( PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ + CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); *//*reset PCISR*/ CONFIG_READ_WORD(PICR1, val); CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_ADDRESS_NAP | PICR1_RCS0)) | + (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | PIRC1_MSK | PICR1_PROC_TYPE_603E | PICR1_FLASH_WR_EN | PICR1_MCP_EN | PICR1_CF_DPARK | PICR1_EN_PCS | @@ -49,9 +49,10 @@ cpu_init_f (void) val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ CONFIG_WRITE_WORD(PICR2, val | PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS); /*1 wait state*/ CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); -#ifndef DEBUG +#ifndef CFG_RAMBOOT CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); +#endif CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); @@ -60,6 +61,18 @@ cpu_init_f (void) (CFG_REFREC << MCCR3_REFREC_SHIFT) | (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); +#ifdef CONFIG_CU824 + CONFIG_WRITE_WORD(MCCR4, + (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + MCCR4_BIT21 | + (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CFG_BSTOPRE & 0x0003) <> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); +#else CONFIG_WRITE_WORD(MCCR4, (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | @@ -68,47 +81,48 @@ cpu_init_f (void) ((CFG_BSTOPRE & 0x0003) <> MICR_ADDR_SHIFT) | + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMSAR1, - ( CFG_BANK0_START & MICR_EADDR_MASK) | - ((CFG_BANK1_START & MICR_EADDR_MASK) << 8) | - ((CFG_BANK2_START & MICR_EADDR_MASK) << 16) | - ((CFG_BANK3_START & MICR_EADDR_MASK) << 24)); + ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MSAR2, - ( CFG_BANK4_START & MICR_ADDR_MASK) | - ((CFG_BANK5_START & MICR_ADDR_MASK) << 8) | - ((CFG_BANK6_START & MICR_ADDR_MASK) << 16) | - ((CFG_BANK7_START & MICR_ADDR_MASK) << 24)); + ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMSAR2, - ( CFG_BANK4_START & MICR_EADDR_MASK) | - ((CFG_BANK5_START & MICR_EADDR_MASK) << 8) | - ((CFG_BANK6_START & MICR_EADDR_MASK) << 16) | - ((CFG_BANK7_START & MICR_EADDR_MASK) << 24)); + ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MEAR1, - ( CFG_BANK0_END & MICR_ADDR_MASK) | - ((CFG_BANK1_END & MICR_ADDR_MASK) << 8) | - ((CFG_BANK2_END & MICR_ADDR_MASK) << 16) | - ((CFG_BANK3_END & MICR_ADDR_MASK) << 24)); + ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMEAR1, - ( CFG_BANK0_END & MICR_EADDR_MASK) | - ((CFG_BANK1_END & MICR_EADDR_MASK) << 8) | - ((CFG_BANK2_END & MICR_EADDR_MASK) << 16) | - ((CFG_BANK3_END & MICR_EADDR_MASK) << 24)); + ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MEAR2, - ( CFG_BANK4_END & MICR_ADDR_MASK) | - ((CFG_BANK5_END & MICR_ADDR_MASK) << 8) | - ((CFG_BANK6_END & MICR_ADDR_MASK) << 16) | - ((CFG_BANK7_END & MICR_ADDR_MASK) << 24)); + ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMEAR2, - ( CFG_BANK4_END & MICR_EADDR_MASK) | - ((CFG_BANK5_END & MICR_EADDR_MASK) << 8) | - ((CFG_BANK6_END & MICR_EADDR_MASK) << 16) | - ((CFG_BANK7_END & MICR_EADDR_MASK) << 24)); + ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); CONFIG_WRITE_BYTE(MBER, @@ -132,7 +146,6 @@ cpu_init_f (void) CONFIG_READ_WORD(MCCR1, val); CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); //set memory access going __asm__ __volatile__("eieio"); -#endif /*map BAT areas - I think this should go somewhere else, *but it'll be fine here for now diff --git a/cpu/mpc8240/start.S b/cpu/mpc8240/start.S index 8fd23da..47fc91d 100644 --- a/cpu/mpc8240/start.S +++ b/cpu/mpc8240/start.S @@ -124,6 +124,7 @@ boot_warm: /* * Calculate absolute address in FLASH and jump there *----------------------------------------------------------------------*/ +#ifndef CONFIG_CU824 #ifndef DEBUG lis r3, CFG_FLASH_BASE@h ori r3, r3, CFG_FLASH_BASE@l @@ -131,6 +132,7 @@ boot_warm: mtlr r3 blr #endif +#endif in_flash: @@ -429,12 +431,17 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ +#ifdef CONFIG_CU824 + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l +#else #ifdef DEBUG lis r4, CFG_SDRAM_BASE@h /* Source Address */ ori r4, r4, CFG_SDRAM_BASE@l #else lis r4, CFG_FLASH_BASE@h /* Source Address */ ori r4, r4, CFG_FLASH_BASE@l +#endif #endif lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */ ori r5, r5, CFG_MONITOR_LEN@l diff --git a/include/config_CU824.h b/include/config_CU824.h new file mode 100644 index 0000000..475de1b --- /dev/null +++ b/include/config_CU824.h @@ -0,0 +1,247 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the CU824 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8240 1 +#define CONFIG_CU824 1 + +#define STOP_HERE __asm__ __volatile__ ( "trap" ) +#define CFG_RAMBOOT + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ +#define CONFIG_BOOTARGS " " +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_COMMANDS CONFIG_CMD_DFL + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 8 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFCE00000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00100000 /* 0 ... 32 MB in DRAM */ + + /* Total amount of RAM. + */ +#define CFG_RAM_SIZE 0x04000000 + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + + /* Size in bytes reserved for initial data + */ +#define CFG_INIT_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR (CFG_RAM_SIZE - CFG_INIT_DATA_SIZE) +#define CFG_INIT_DATA_OFFSET 0 + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_SERIAL_CLOCK (14745600 / 2) +#define CFG_HZ 1000 + +#define CFG_ETH_DEV_FN 0x7800 +#define CFG_ETH_IOBASE 0x00104000 + + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 7 + + /* Bit-field values for MCCR2. + */ +#define CFG_REFINT 430 /* Refresh interval */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 192 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* Data latancy from read command */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 +#define CFG_REGISTERD_TYPE_BUFFER 1 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L 0 +#define CFG_IBAT0U 0 +#define CFG_IBAT1L 0 +#define CFG_IBAT1U 0 +#define CFG_IBAT2L 0 +#define CFG_IBAT2U 0 +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_DBAT0L 0 +#define CFG_DBAT0U 0 +#define CFG_DBAT1L 0 +#define CFG_DBAT1U 0 +#define CFG_DBAT2L 0 +#define CFG_DBAT2U 0 +#define CFG_DBAT3L 0 +#define CFG_DBAT3U 0 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ +#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif /* __CONFIG_H */ diff --git a/include/mpc8240.h b/include/mpc8240.h index f1b8f3a..f2cc8be 100755 --- a/include/mpc8240.h +++ b/include/mpc8240.h @@ -94,7 +94,7 @@ : /* no output */ \ : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ "r" (CONFIG_DATA), "r" (data), \ - "n" ((addr) & 3)); + "n" (3 - ((addr) & 3))); #define CONFIG_WRITE_HALFWORD( addr, data ) \ __asm__ ( \ @@ -103,9 +103,9 @@ stwbrx %3, %4, %2\n \ sync " \ : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (addr), \ + : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ "r" (CONFIG_DATA), "r" (data), \ - "n" ((addr) & 3)); + "r" ((addr) & 3)); /* this assumes it's writeing on word boundaries*/ #define CONFIG_WRITE_WORD( addr, data ) \ @@ -128,7 +128,7 @@ sync " \ : "=r" (reg) \ : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ - "r" (CONFIG_DATA), "n" ((addr) & 3)); + "r" (CONFIG_DATA), "n" ((3 - (addr)) & 3)); #define CONFIG_READ_HALFWORD( addr , reg ) \ @@ -138,9 +138,9 @@ lhbrx %0, %4, %3\n \ sync " \ : "=r" (reg) \ - : "r" (addr), "r" (CONFIG_ADDR), \ + : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ "r" (CONFIG_DATA), \ - "n" ((addr)&3)); + "r" ((addr) & 3)); /* this assumes it's reading on word boundaries*/ #define CONFIG_READ_WORD( addr , reg ) \ @@ -217,7 +217,7 @@ #define PICR1_CF_DPARK 0x00000200 #define PICR1_MCP_EN 0x00000800 #define PICR1_FLASH_WR_EN 0x00001000 -#define PICR1_ADDRESS_NAP 0x00010000 +#define PICR1_ADDRESS_MAP 0x00010000 #define PICR1_PROC_TYPE_MSK 0x00060000 #define PICR1_PROC_TYPE_603E 0x00040000 #define PICR1_RCS0 0x00100000 @@ -300,7 +300,9 @@ #define MCCR4_BSTOPRE6TO9_SHIFT 0 #define MICR_ADDR_MASK 0x0ff00000 +#define MICR_ADDR_SHIFT 20 #define MICR_EADDR_MASK 0x30000000 +#define MICR_EADDR_SHIFT 28 #define BATU_BEPI_MSK 0xfffe0000 #define BATU_BL_MSK 0x00001ffc