From: Thomas Gleixner Date: Sat, 12 May 2018 18:49:16 +0000 (+0200) Subject: x86/bugs: Expose x86_spec_ctrl_base directly X-Git-Tag: v4.1.12-124.31.3~738 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=762a0107fea47f27aad656a8568873b79bb0b5a5;p=users%2Fjedix%2Flinux-maple.git x86/bugs: Expose x86_spec_ctrl_base directly x86_spec_ctrl_base is the system wide default value for the SPEC_CTRL MSR. x86_spec_ctrl_get_default() returns x86_spec_ctrl_base and was intended to prevent modification to that variable. Though the variable is read only after init and globaly visible already. Remove the function and export the variable instead. Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Reviewed-by: Konrad Rzeszutek Wilk Orabug: 28063992 CVE: CVE-2018-3639 (cherry picked from commit fa8ac498) Signed-off-by: Mihai Carabas Reviewed-by: Konrad Rzeszutek Wilk Reviewed-by: Darren Kenny Signed-off-by: Brian Maly Conflicts: arch/x86/include/asm/nospec-branch.h arch/x86/include/asm/spec-ctrl.h arch/x86/kernel/cpu/bugs.c [Contextual changes: things weren't in the expected place] Signed-off-by: Brian Maly --- diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 5bbf1e789557c..182dc7bc88a69 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -172,16 +172,10 @@ enum spectre_v2_mitigation { SPECTRE_V2_IBRS_LFENCE, }; -/* - * The Intel specification for the SPEC_CTRL MSR requires that we - * preserve any already set reserved bits at boot time (e.g. for - * future additions that this kernel is not currently aware of). - * We then set any additional mitigation bits that we want - * ourselves and always use this as the base for SPEC_CTRL. - * We also use this when handling guest entry/exit as below. - */ extern void x86_spec_ctrl_set(u64); -extern u64 x86_spec_ctrl_get_default(void); + +/* The Intel SPEC CTRL MSR base value cache */ +extern u64 x86_spec_ctrl_base; /* The Speculative Store Bypass disable variants */ enum ssb_mitigation { diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h index 39cc7aba3af85..1672ea544158d 100644 --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -47,9 +47,6 @@ void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) extern u64 x86_amd_ls_cfg_base; extern u64 x86_amd_ls_cfg_ssbd_mask; -/* The Intel SPEC CTRL MSR base value cache */ -extern u64 x86_spec_ctrl_base; - static inline u64 ssbd_tif_to_spec_ctrl(u32 tifn) { BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c index b74889d16fa47..75138e7e62363 100644 --- a/arch/x86/kernel/cpu/bugs_64.c +++ b/arch/x86/kernel/cpu/bugs_64.c @@ -254,16 +254,6 @@ void x86_spec_ctrl_set(u64 val) } EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); -u64 x86_spec_ctrl_get_default(void) -{ - u64 msrval = x86_spec_ctrl_base; - - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) - msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); - return msrval; -} -EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default); - void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) { diff --git a/arch/x86/kernel/cpu/spec_ctrl.c b/arch/x86/kernel/cpu/spec_ctrl.c index 5cbc0945afbc2..57d495c31c320 100644 --- a/arch/x86/kernel/cpu/spec_ctrl.c +++ b/arch/x86/kernel/cpu/spec_ctrl.c @@ -216,7 +216,7 @@ late_initcall(debugfs_spec_ctrl); void unprotected_firmware_begin(void) { if (retpoline_enabled() && ibrs_firmware) { - u64 val = x86_spec_ctrl_get_default() | SPEC_CTRL_FEATURE_ENABLE_IBRS; + u64 val = x86_spec_ctrl_base | SPEC_CTRL_FEATURE_ENABLE_IBRS; native_wrmsrl(MSR_IA32_SPEC_CTRL, val); } else { @@ -232,7 +232,7 @@ EXPORT_SYMBOL_GPL(unprotected_firmware_begin); void unprotected_firmware_end(void) { if (retpoline_enabled() && ibrs_firmware) { - u64 val = x86_spec_ctrl_get_default(); + u64 val = x86_spec_ctrl_base; native_wrmsrl(MSR_IA32_SPEC_CTRL, val); }